Video encoding and decoding method and device

Abstract

A method and apparatus for video coding and decoding are disclosed. According to the method, a bit stream corresponding to coded data of a video sequence is generated at an encoder side or received at a decoder side, wherein the bit stream includes a first syntax associated with a precision of an adaptive motion vector difference resolution (AMVR), and wherein the syntax associated with the AMVR precision is encoded and decoded by context coding bins having at least two contexts. Using information including the AMVR precision, one or more motion vectors for the target block are encoded at the encoder side or decoded at the decoder side.

Description

[0001] Cross-references

[0002] The present invention claims priority to U.S. Provisional Patent Application Serial No. 62 / 933,578, filed on November 11, 2019. The U.S. Provisional Patent Application is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to video coding and decoding. More particularly, the present invention discloses a technique for signaling Adaptive Motion Vector Difference Resolution (AMVR) information in video coding and decoding. Background Art

[0004] Adaptive intra / inter video coding has been widely used in various video coding standards, such as MPEG-2, AVC (Advanced Video Coding) and HEVC (High Efficiency Video Coding). In adaptive intra / inter video coding, an input signal is predicted by intra / inter predictors to generate prediction residuals. The residuals are usually processed by two-dimensional transformation and quantization. The quantized transform coefficients are then encoded. The standard for High Efficiency Video Coding (HEVC) was developed by the Video Coding Experts Group (VCEG) of the International Telecommunication Union Telecommunication Standardization Sector and the Moving Picture Experts Group (MPEG) of the International Organization for Standardization / International Commission on Electrical and Electronics under the Joint Video Project, and in particular in cooperation with the Joint Collaborative Team on Video Coding (JCT-VC). In HEVC, a slice is split into multiple Coding Tree Units (CTUs). In the main profile, the minimum and maximum sizes of CTUs are specified by syntax elements in the Sequence Parameter Set (SPS). The allowed CTU sizes can be 8x8, 16x16, 32x32, or 64x64. For each slice, the CTUs within the slice are processed according to the raster scan order.

[0005] The CTU is further partitioned into multiple coding units (CUs) to accommodate various local characteristics. A CTU can be further partitioned into multiple coding units (CUs) through quad-tree or quadtree (QT) partitioning. QT partitioning partitions a block of size 4Nx4N into 4 2Nx2N sub-blocks of the same size. A CTU can be a single CU (i.e., no partitioning) or can be partitioned into four smaller units of the same size, which correspond to the nodes of the codec tree. If these units are leaf nodes of the codec tree, these units become CUs. Otherwise, the quadtree partitioning process can be repeatedly calculated until the size of a node reaches the minimum allowable CU size specified in the sequence parameter set (SPS).

[0006] According to HEVC, each CU can be divided into one or more prediction units (PUs). In combination with the CU, the PU serves as a basic representation block that shares common prediction information. Within each PU, the same prediction process can be applied, and relevant information is sent to the decoder on a PU basis. Depending on the PU partition type, the CU can be partitioned into one, two or four PUs. HEVC defines eight shapes for partitioning a CU into PUs, including 2Nx2N, 2NxN, Nx2N, NxN, 2NxnU, 2NxnD, nLx2N and nRx2N partition types. Unlike the CU, according to HEVC, the PU can only be partitioned once.

[0007] Based on the PU partition type, after obtaining the residual block through the prediction process, the prediction residual of a CU can be partitioned into transform units (TUs) according to another quadtree structure (which is similar to the codec tree for CU). TU is a basic representative block with residual or transform coefficients for applying integer transform and quantization. For each TU, an integer transform with the same size as the TU is applied to obtain the residual coefficients. After quantization on a TU basis, these coefficients are transmitted to the decoder.

[0008] Figure 1An exemplary block diagram of a video encoder is shown, wherein the video encoder incorporates intra / inter prediction, transform and quantization processes. For inter prediction, motion estimation (ME) / motion compensation (MC) 112 is used to provide prediction data based on video data from one or more other frames. Switch 114 selects intra-prediction 110 or inter-prediction data, and the selected prediction data is provided to adder 116 to form a prediction error, also known as residual. The prediction error is processed by a transform (T) 118 and then a quantization (Q) 120. The transformed and quantized residual is encoded by entropy encoder 122 to be included in a video bitstream corresponding to the compressed video data. The bitstream associated with the transform coefficients is packed together with side information such as motion, codec mode, and other information associated with the image area. The side information can be compressed by entropy coding to reduce the required bandwidth. Therefore, the data associated with the side information is provided to Figure 1 Entropy encoder 122 is shown. When inter-prediction mode is used, one or more reference pictures must also be reconstructed at the encoder. Therefore, the transformed and quantized residual is processed by inverse quantization (IQ) 124 and inverse transformation (IT) 126 to restore the residual. The residual is added back to the prediction data 136 at reconstruction (REC) 128 to reconstruct the video data. The reconstructed video data can then be stored in the reference picture buffer (Reference Picture Buffer) 134 and used to predict other frames.

[0009] like Figure 1As shown, the input video data will go through a series of processing steps in the encoding system. Due to the series of processing steps, the reconstructed video data from REC128 may suffer various damages. Therefore, before the reconstructed video data is stored in the reference picture buffer 134, a loop filter (Loop filter) 130 is usually applied to process the reconstructed video data to improve the video quality. For example, deblocking filter (de-blocking Filter, DF) and sample adaptive offset (Sample Adaptive Offset, SAO) have been used in the High Efficiency Video Coding (High Efficiency Video Coding, HEVC) standard. The loop filter may also include ALF (Adaptive Loop Filter. The loop filter information may need to be merged into the bitstream so that a decoder can properly restore the required information. Therefore, the loop filter information is provided to the entropy encoder 122 to be merged into the bitstream. In Figure 1 In , the loop filter 130 is applied to the reconstructed video before the reconstructed samples are stored in the reference picture buffer 134. Figure 1 The system in is intended to illustrate an exemplary structure of a typical video encoder, which may correspond to the High Efficiency Video Codec (HEVC) system or H.264.

[0010] Figure 2 Draw for Figure 1 A system block diagram of a corresponding video decoder in an encoder system. Since the encoder also includes a local decoder to reconstruct the video data, some decoder elements are already used in the encoder (except for the entropy decoder 210). In addition, only motion compensation 220 is required on the decoder side. Switch 146 selects intra-frame prediction or inter-frame prediction, and the selected prediction data is provided to reconstruction (REC) 128 to be combined with the restored residual. In addition to entropy decoding the compressed residual, the entropy decoder 210 is also responsible for entropy decoding the side information and providing the side information to the corresponding blocks. For example, intra-frame mode information is provided to intra-frame prediction 110, inter-frame mode information is provided to motion compensation 220, loop filter information is provided to loop filter 130, and the residual is provided to inverse quantization 124. The residual is processed by IQ124, IT126 and subsequent reconstruction processes to reconstruct the video data. The reconstructed video data from REC128 is again subjected to a series of processing processes, including such as Figure 2 The reconstructed video data is further processed by loop filter 130 .

[0011] Advanced Motion Vector Prediction Mode (AMVP)

[0012] In most codec standards, adaptive inter / intra prediction is used on a block basis. In inter prediction mode, one or two motion vectors are determined for each block to select a reference block (i.e., unidirectional prediction) or two reference blocks (i.e., bidirectional prediction). The motion vector or motion vectors are determined and encoded for each individual block. In HEVC, inter motion compensation is supported in two different ways: explicit signaling or implicit signaling. In explicit signaling, the motion vector for a block (i.e., PU) is signaled using a predictive codec method. The motion vector predictor corresponds to the motion vector associated with the spatial and temporal neighbors of the current block. The best MVP with the smallest motion vector difference (MVD) compared to the corresponding MV can be selected for efficient encoding and decoding. Since the encoder and decoder maintain the same set of MVPs, an MVP index is signaled to specify the best MVP. After an MV predictor is determined, the motion vector difference (MVD) is encoded, decoded and transmitted. This mode is also called AMVP (advanced motion vector prediction) mode. In implicit signaling, a predictor from a set of candidate predictors is selected as the motion vector for the current block (i.e., PU). Since both the encoder and decoder will derive the candidate set and select the final motion vector in the same way, no MV or MVD needs to be signaled in implicit mode. This mode is also called Merge mode. Forming the predictor set in Merge mode is also called Merge candidatelist construction. An index, also called Merge index, is signaled to indicate the predictor selected as the MV for the current block.

[0013] Affine Model

[0014] The motion that occurs across the frames along the time axis can be described by a number of different models. Assuming A(x,y) is the original pixel under consideration at position (x,y), and A'(x',y') is the corresponding pixel at position (x',y') in a reference frame for a current pixel A(x,y), the affine motion model can be described as follows.

[0015] Since traditional motion estimation can only describe translational motion

[0016] (translational motion), the affine model can describe the two-dimensional block rotation and two-dimensional deformation to transform a square (or rectangle) into a parallelogram. This model can be described as follows:

[0017] x' = a0 + a1 * x + a2 * y, and

[0018] y'=b0+b1*x+b2*y. (1)

[0020] In the contribution ITU-T13-SG16-C1016 submitted to ITU-VCEG (Lin et al. "Affine transform prediction for next generation video coding", ITU-U, Study Group 16 Question Q6 / 16, Contribution C1016, September 2015, Geneva, Switzerland), four-parameter affine prediction has been revealed, including the affine merge mode. When an affine motion block is moving, the motion vector field of the block can be described by the following two control point motion vectors or four parameters, where (vx, vy) represents the motion vector.

[0021]

[0022] An example of a four-parameter affine model is shown in Figure 3A , where block 310 corresponds to the current block. The converted block is a rectangular block. Figure 3B As shown, the four-parameter affine model can handle object rotation, where rectangle 310 is rotated to rectangle 320. The position of rectangle 320 after rotation can be determined by the motion vectors at the two control points (i.e. and ) to be made explicit. The four-parameter affine model can handle object rotations with scaled sizes.

[0023] The motion vector field of each point in this moving block can be described by the following equation:

[0024]

[0025] In the above equation, (v 0x ,v 0y ) is the control point motion vector (i.e. v0) at the top left corner of the block, and (v 1x ,v 1y ) is the control point motion vector (i.e. v1) at the upper right corner of the block.

[0026] In addition to the four-parameter affine model, a six-parameter affine model has also been adopted in advanced video coding standards, such as HEVC.

[0027] Intra-block copy (IBC) / Current Picture Referencing

[0028] For some video content, the spatial correlation between pixels in the same frame is different for the frame content. For typical videos with text and graphics, there are often repeated patterns in the same frame. Therefore, intra-frame (frame) block compensation has been observed to be very effective. A new prediction mode, the intra block copy (IBC) mode or also called current picture referencing (CPR) has been introduced for frame content coding to exploit this property. In the CPR mode, a prediction unit (PU) is predicted from a previously reconstructed block in the same frame. In addition, a displacement vector (also called Block Vector or BV) is used to signal the relative displacement from the current block position to the reference block position. The prediction error is then coded and decoded using transform, quantization, and entropy coding.

[0029] Intra-block copy (IBC) is adopted in HEVC extensions in Screen Content Codec (SCC) and in the emerging video codec standard, Versatile Video Coding (VVC). As is well known, it can greatly enhance the coding efficiency of screen content materials. Since the IBC mode is a block-level codec mode, block matching (BM) is implemented at the encoder to find the best block vector (or motion vector) for each CU. Here, a block vector is used to indicate the displacement from the current block to a reference block that has been reconstructed in the current picture. The luma block vector of an IBC-coded CU is in integer precision. The chroma block vector is also rounded to integer precision. When combined with AMVR, the IBC mode can switch between 1-pixel (1-pel) and 4-pixel (4-pel) motion vector precision. An IBC-coded CU is treated as a third prediction mode in addition to intra or inter prediction mode. IBC mode is applicable to CUs with width and height both less than or equal to 64 luma samples.

[0030] Advanced Motion Vector Resolution (AMVR)

[0031] Adaptive motion vector difference resolution (AMVR) supports three MV resolutions, including quarter-luma sample, integer-luma sample, and quad-luma sample, to reduce the side information of motion vector difference (MVD). Flags signaled at the SPS-level and CU-level are used to indicate whether AMVR is enabled and which MV resolution is selected for the current CU. In advanced motion vector prediction mode (AMVP), motion vectors (MVs) are generated by unidirectional or bidirectional prediction, and then one or a group of motion vector predictors (MVPs) are generated simultaneously. The best MVP with the smallest motion vector difference (MVD) compared to the corresponding MV can be selected for efficient encoding and decoding. With AMVR enabled, both MV and MVP are adjusted according to the selected MV resolution, and MVD is also aligned with the resolution.

[0032] In HEVC, AMVP mode uses an MVP index to select among motion vector predictors in the MVP candidate list. If AMVR is enabled, both the AMVR flag and the MVP index must be signaled.

[0033] In the VVC Draft 7 standard, in JVET-P2001 (“Versatile Video Coding (Draft 7)” by B. Bross et al., Joint Video Experts Group (JVET) under the International Telecommunication Union - Telecommunication Standardization Sector, Study Group 16, Working Group 3 (ITU-TSG16 WP3) and the International Organization for Standardization / International Electrotechnical Commission Technical Committee 1, Subcommittee 29, Working Group 11 (ISO / IEC JTC1 / SC29 / WG11), 16th meeting: Geneva, CH, October 1–11, 2019, document JVET-P2001-vB), some AMVR parameters are signaled at the CU level as shown in Table 1.

[0034] Table 1 Some AMVR parameters signaled at the CU level according to VVC Draft 7

[0035] amvr_flag[x0][y0] specifies the resolution of the motion vector differences. The array index x0, y0 specifies the position (x0, y0) of the top left luma sample of the considered codec block relative to the top left luma sample of the picture. amvr_flag[x0][y0] equal to 0 specifies that the resolution of the motion vector differences is 1 / 4 of a luma sample. amvr_flag[x0][y0] equal to 1 specifies that the resolution of the motion vector differences is further specified by amvr_precision_idx[x0][y0].

[0036] When amvr_flag[x0][y0] is not present, it is inferred as follows:

[0037] – If CuPredMode[chType][x0][y0] is equal to MODE_IBC, amvr_flag[x0][y0] is inferred to be equal to 1.

[0038] – Otherwise (CuPredMode[chType][x0][y0] is not equal to MODE_IBC), amvr_flag[x0][y0] is inferred to be equal to 0.

[0039] amvr_precision_idx[x0][y0] indicates the resolution of motion vector differences with AmvrShift as defined in Table 16 of VVC Draft 7. The array index x0, y0 indicates the position (x0, y0) of the top left luma sample of the considered codec block relative to the top left luma sample of the picture.

[0040] When amvr_precision_idx[x0][y0] is not present, it is inferred to be equal to 0.

[0041] Specifying ctxInc as a syntax element with context coded bins for amvr_flag[x0][y0] and amvr_precision_idx[][] is shown in Table 2.

[0042] Table 2 specifies ctxInc to the syntax element with context codec

[0043] Summary of the invention

[0044] A method and apparatus for encoding and decoding a video sequence supported by an adaptive motion vector difference resolution (AMVR) mode are disclosed. According to the present invention, a bitstream corresponding to coded data of the video sequence is generated at an encoder side or received at a decoder side, wherein the bitstream includes a syntax associated with AMVR precision, and wherein the syntax associated with the AMVR precision is encoded and decoded by context coding bins having at least two contexts. Using information including the AMVR precision, one or more motion vectors for the target block are encoded at the encoder side or decoded at the decoder side.

[0045] In one embodiment, the syntax associated with the AMVR precision is encoded at a codec unit (CU) level.

[0046] In one embodiment, the at least two contexts include: a first context corresponding to an intra block copy (IBC) mode, and a second context corresponding to a non-IBC mode.

[0047] In one embodiment, the at least two contexts include: a first context corresponding to the affine mode, and a second context corresponding to the non-affine mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 An exemplary block diagram of a video encoder is shown, wherein the video encoder combines intra / inter prediction, conversion and quantization processes.

[0049] Figure 2 An exemplary block diagram of a video decoder is shown, wherein the video decoder combines intra / inter prediction, inverse transformation and de-quantization processes.

[0050] Figure 3A An example of a four-parameter affine model is shown.

[0051] Figure 3B An example of a four-parameter affine model that can handle object rotation is shown.

[0052] Figure 4 A flow chart of an exemplary video coding system according to an embodiment of the present invention is provided, wherein the system uses context coding bins having at least two contexts to encode and decode a syntax associated with adaptive motion vector difference resolution (AMVR) information. DETAILED DESCRIPTION

[0053] The following description is the best contemplated way to implement the present invention. The purpose of this description is to illustrate the general principles of the present invention and should not be viewed from a limiting perspective. The best mode of the present invention is determined by referring to the scope of the attached claims.

[0054] The syntax amvr_flag and amvr_precision_idx are used to indicate different resolutions for the decoded MVD. When amvr_flag is equal to 0, quarter-pixel luma samples are used to decode the MVD. In addition, if amvr_flag is equal to 1, amvr_precision_idx is signaled to indicate which integer-pixel resolution of luma samples is used. Adaptive Motion Vector Resolution (AMVR) can be applied to inter mode (non-affine), affine mode, and IBC mode. In affine mode, three MV resolutions are supported, including quarter-pixel, 1 / 16-pixel, and integer-pixel, which are encoded and decoded with codewords {0, 10, 11} according to an embodiment of the present invention. The first bin is associated with amvr_flag and the second bin is associated with amvr_precision_idx. In IBC mode, only two MV resolutions are supported, including integer-pixel and 4-pixel resolutions, which are encoded and decoded with codewords {10, 11} according to an embodiment of the present invention. The first bit is related to amvr_flag and is always inferred to be 1 when encoded and decoded in IBC mode, and the second bit is related to amvr_precision_idx to indicate whether 4-pixel is used. In non-affine inter mode, four MV resolutions are supported, including quarter-pixel, half-pixel, integer-pixel, and 4-pixel, which are encoded and decoded with codewords {0, 10, 110, 111} according to an embodiment of the present invention. The first bit is related to amvr_flag and the other two bits are related to amvr_precision_idx.

[0055] According to embodiments of the present invention, the context variable design in the above three modes can be further aligned. For example, the use of the second bit described above can always be used to distinguish between fractional and integer MV resolutions. In one embodiment, amvr_precision_idx can be split into two syntax elements, such as amvr_precision_int and amvr_precision_rest. In this way, in IBC mode, the 2MV resolution supported by IBC can be encoded and decoded with the codeword {110,111}. The first bit is related to amvr_flag and it will be inferred to be 1. The second bit is related to amvr_precision_int and it is also inferred to be 1 in IBC mode. Only the third bit related to amvr_precision_rest needs to be signaled. In affine mode, 3MV resolution is supported and is encoded and decoded with the codeword {0,10,11}. Only amvr_flag and amvr_precision_int need to be signaled. amvr_precision_rest is not needed in affine mode. In non-affine inter mode, 4 MV resolutions are supported, including quarter-pixel, half-pixel, integer-pixel, and 4-pixel, and are encoded and decoded with codewords {0,10,110,111}. The first bit used to indicate quarter-pixel resolution is for amvr_flag. The second bit used to indicate fractional resolution is for amvr_precision_int. The third bit used to indicate 1-pixel resolution is for amvr_precision_rest.

[0056] In another embodiment, a syntax (e.g., amvr_precision_flag) may be encoded with more than one context variable via context encoding. For example, one variable for affine mode and other variables for non-affine mode may be used according to an embodiment of the present invention. In another example, one variable is used for IBC mode and other variables are used for non-IBC mode.

[0057] Any of the methods proposed above can be implemented in an encoder and / or a decoder. For example, any of the methods proposed above can be implemented in a module in an encoder and / or a decoder that is responsible for encoding and decoding AMVR precision information. Alternatively, any of the methods proposed above can also be implemented as a circuit coupled to a module in an encoder and / or a decoder that is responsible for encoding and decoding AMVR precision information.

[0058] Figure 4The present invention is a flowchart of an exemplary video coding system according to an embodiment of the present invention, wherein the system uses a context codec with at least two contexts to encode a syntax associated with AMVR information. The steps shown in the flowchart can be implemented as program codes and can be executed in one or more processors (e.g., one or more CPUs) at the encoder side. The steps shown in the flowchart can be implemented based on hardware, such as one or more electronic devices or processors arranged to implement the steps of the flowchart. According to this method, in step 410, a bit stream corresponding to coded data of a video sequence is generated at an encoder side or received at a decoder side, wherein the bit stream includes a syntax associated with AMVR precision, and wherein the syntax associated with the AMVR precision is encoded and decoded by a context codec with at least two contexts. In step 420, one or more motion vectors for the target block are encoded at the encoder side or decoded at the decoder side using the information including the AMVR precision.

[0059] The flowchart shown is used to illustrate an example of video encoding and decoding according to the present invention. Without departing from the spirit of the present invention, a person skilled in the art can modify each step, reorganize the steps, separate a step, or combine the steps to implement the present invention. In this disclosure, specific syntax and semantics have been used to illustrate examples of implementing embodiments of the present invention. Without departing from the spirit of the present invention, a person skilled in the art can implement the present invention by replacing the syntax and semantics with equivalent syntax and semantics.

[0060] The above description enables those skilled in the art to implement the present invention in the context of a particular application and its requirements. Various variations of the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described, but will be given the maximum scope consistent with the principles and novel features disclosed herein. In the above detailed description, various specific details are described in order to thoroughly understand the present invention. Nevertheless, it will be understood by those skilled in the art that the present invention can be put into practice.

[0061] The embodiments of the present invention as described above can be implemented in various hardware, software codes or a combination of the two. For example, an embodiment of the present invention can be a circuit integrated in a video compression chip, or a program code integrated into a video compression software to perform the processing described herein. An embodiment of the present invention can also be a program code executed on a digital signal processor (DSP) to perform the processing described herein. The present invention can also include several functions executed by a computer processor, a digital signal processor, a microprocessor or a field programmable gate array (FPGA). According to the present invention, these processors can be configured to perform specific tasks by executing machine-readable software code or firmware code that defines the specific method implemented by the present invention. The software code or firmware code can be developed by different programming languages ​​and different formats or styles. The software code can also be compiled for different target platforms. However, different code formats, styles and languages ​​of software codes and other forms of configuration codes for performing the tasks of the present invention will not deviate from the spirit and scope of the present invention.

[0062] Without departing from the spirit or essential features of the present invention, the present invention may be implemented in other specific forms. The described examples are considered to be illustrative and not restrictive in all aspects only. Therefore, the scope of the present invention is indicated by the appended claims rather than the previous description. All changes within the meaning and scope of the equivalents belonging to the claims will be included within their scope.

Claims

1. A method for encoding and decoding a video sequence supported by an adaptive motion vector difference resolution mode, the method comprising: A bitstream of coded data corresponding to a target block is generated at an encoder side or received at a decoder side, wherein the bitstream includes a syntax associated with the precision of the adaptive motion vector difference resolution, and wherein the syntax associated with the precision of the adaptive motion vector difference resolution is encoded and decoded by a context codec having at least two contexts, wherein the at least two contexts include: a first context corresponding to an intra block copy mode, and a second context corresponding to a non-intra block copy mode; and One or more motion vectors for the target block are encoded at an encoder side or decoded at a decoder side using information including the accuracy of the adaptive motion vector difference resolution.

2. The method for encoding and decoding a video sequence according to claim 1, characterized in that: The syntax associated with the accuracy of the adaptive motion vector difference resolution is encoded at a codec unit level.

3. The method for encoding and decoding a video sequence according to claim 1, characterized in that: The at least two contexts include: a first context corresponding to the affine mode, and a second context corresponding to the non-affine mode.

4. An apparatus for encoding and decoding a video sequence supported by an adaptive motion vector difference resolution mode, the apparatus comprising one or more electronic circuits or processors arranged to: A bitstream of coded data corresponding to a target block is generated at an encoder side or received at a decoder side, wherein the bitstream includes a syntax associated with the precision of the adaptive motion vector difference resolution, and wherein the syntax associated with the precision of the adaptive motion vector difference resolution is encoded and decoded by a context codec having at least two contexts, wherein the at least two contexts include: a first context corresponding to the intra block copy mode, and a second context corresponding to the non-intra block copy mode; as well as One or more motion vectors for the target block are encoded at an encoder side or decoded at a decoder side using information including the accuracy of the adaptive motion vector difference resolution.

5. The device for encoding and decoding a video sequence according to claim 4, characterized in that: The syntax associated with the accuracy of the adaptive motion vector difference resolution is encoded at a codec unit level.

6. The apparatus for encoding and decoding a video sequence according to claim 4, wherein the at least two contexts include: A first context corresponds to the affine mode, and a second context corresponds to the non-affine mode.

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