A test board for detecting a general payload manager

Abstract

The present invention discloses a detection test board card for a general payload manager, which is deployed between a host computer and the payload manager of a device under test and is used to test the common function interfaces of payload managers of different mission models. It is characterized in that the test board card includes: a payload configuration management module and a common function interface module; wherein, the payload configuration management module is used to store the payload format configuration table sent by the host computer in the external payload configuration table Flash; is used to read the configuration information pre-stored in the external payload configuration table Flash and perform corresponding processing according to the command sent by the host computer; is used to send the generated scientific data, control signals and acquisition signals to the external common function interface module, and is also used to send the execution result of the detection test board card to the host computer; the common function interface module is used to implement the connection circuit with the common function interfaces of the payload manager.

Description

Technical Field

[0001] The present invention relates to the technical field of aerospace electronic integration, and particularly to a test board for a general payload manager on the ground. Background Art

[0002] When developing on-orbit products, it is also necessary to purchase or design corresponding ground test equipment (referred to as ground test for short) to test the functions and performances of on-orbit products to ensure that the on-orbit products meet the mission requirements.

[0003] Since the interfaces, protocols, etc. of the satellite platform and payloads are different in each mission, a payload manager will be configured for the satellite for communication between the satellite and the payloads. This results in different functions and interfaces of the payload managers for different mission models. Therefore, the hardware and software for the ground test of the payload managers for different mission models also need to be designed specifically. The generality of the ground test of the payload manager has always been a difficult point in the design of the ground test.

[0004] The external electrical interfaces of the satellite platform generally include power supply and distribution interfaces, bus interfaces, scientific data input interfaces, direct telemetry input interfaces, remote control output interfaces, second pulse output interfaces, etc. The external electrical interfaces of the payloads generally include power supply and distribution interfaces, bus interfaces, scientific data output interfaces, direct telemetry output interfaces, remote control input interfaces, second pulse input interfaces, etc. The payload manager is connected to both the satellite platform and multiple payloads, so the interfaces of the payload manager are divided into interfaces for the platform and for the payloads. Classified by the transmission rate of the electrical interfaces, they can be divided into high-speed interfaces and low-speed interfaces; the high-speed interfaces are generally several hundred Mbps to several Gbps, and are generally coaxial cable or optical fiber interfaces; the low-speed interfaces generally have a rate less than 100 Mbps, as well as some discrete telemetry and remote control interfaces.

[0005] The on-orbit bus interfaces generally include 1553B bus, CAN bus, RS422 bus, RS485 bus, etc. The on-orbit low-speed scientific data interfaces generally include LVDS interfaces or RS422 interfaces in single-wire or three-wire systems.

[0006] Generally, the ground test solutions for the payload manager purchase off-the-shelf products such as industrial control computers and 1553B boards, RS422 boards, LVDS boards, analog acquisition boards, OC boards, etc. with PCIE interfaces. There is a programmable device FPGA on each board, and it is necessary to design the upper computer interface and the interface and logic design with the FPGA of each board in the industrial control computer. The disadvantages of this solution are high cost, complex software design, a large number of FPGAs that need to be programmed, and poor generality. Summary of the Invention

[0007] The object of the present invention is to overcome the defects of the prior art and propose a test board for a general payload manager on the ground.

[0008] To achieve the above object, the present invention proposes a test board for a general payload manager, which is deployed between the host computer and the payload manager of the device under test, and is used to test the common function interfaces of payload managers of different mission models. The test board includes: a payload configuration management module and a common function interface module; wherein,

[0009] The payload configuration management module is used to store the payload format configuration table sent by the host computer in the external payload configuration table Flash; to read the configuration information pre-stored in the external payload configuration table Flash and perform corresponding processing according to the command sent by the host computer; to send the generated scientific data, control signals and acquisition signals to the external common function interface module, and is also used to send the execution result of the test board to the host computer;

[0010] The common function interface module is used to implement the connection circuit with the common function interfaces of the payload manager.

[0011] As an improvement of the above board, the configuration information includes: scientific data format, payload instruction format, engineering response format, communication protocol selection and configuration, configuration of the common function interface module, and configuration of the payload configuration management module.

[0012] As an improvement of the above board, the payload configuration management module is implemented based on FPGA and non-volatile flash technology NOR Flash, and specifically includes: a configuration interface unit, a configuration control unit, a scientific data function unit, an instruction / engineering function unit, and a control logic unit; wherein

[0013] The configuration interface unit is used to receive the command and payload format configuration table sent by the host computer and send them to the configuration control unit; it is also used to send the execution result of the test board to the host computer;

[0014] The configuration control unit is used to receive the command and / or payload format configuration table of the host computer, perform corresponding parsing and write the parsed command into the corresponding register, write the parsed configuration information into the external payload configuration table Flash, and is also used to read the command from the register to the instruction / engineering function unit, and read the configuration information from the external payload configuration table Flash to the scientific data function unit and the control logic unit;

[0015] The scientific data function unit is used to generate scientific data in the corresponding format according to the configuration information;

[0016] The instruction / engineering function unit is used to generate payload instructions in the corresponding format according to the command;

[0017] The control logic unit is used to implement the control logic of the external functional chip according to the configuration information and store the results, where the results include AD acquisition results, pulse detection results, GPIO detection results, and second pulses.

[0018] As an improvement to the above board, the scientific data function unit includes 16 channels, and different data formats and different output levels are selected through registers. The data formats include UART, 8b / 10b encoding, and three-wire system, and the output levels include RS422 level and LVDS level.

[0019] As an improvement to the above board, the instruction / engineering function unit includes 16 channels corresponding to different data formats. The data formats include UART, duplex, and half-duplex bus modes, and UART is adopted by default.

[0020] As an improvement to the above board, the payload configuration table Flash pre-allocates the address space according to the registers corresponding to each unit set by the payload management module.

[0021] As an improvement to the above board, the common function interface module is implemented based on interface chips, and the interface chips include RS422 transmit / receive chips, LVDS transmit / receive chips, AD chips, DA chips, OC gates, and bus buffer chips.

[0022] As an improvement to the above board, serial communication is adopted between the test board and the host computer, including half-word write operation, half-word read operation, continuous write operation, and continuous read operation; among them,

[0023] The half-word write operation includes: 1-byte write command, 3-byte write address, and 2-byte write data, using the high byte order;

[0024] The half-word read operation includes: 1-byte read command, 3-byte read address, and 2-byte response data of the FPGA, using the high byte order;

[0025] The continuous write operation includes: 1-byte write command, 3-byte starting write address, 3-byte number of write data, and write data;

[0026] The continuous read operation includes: 1-byte read command, 3-byte starting read address, 3-byte number of read data, and response data of the FPGA.

[0027] Compared with the prior art, the advantages of the present invention are as follows:

[0028] 1. The board designed by the present invention reduces the number of boards and programmable FPGAs, relieves the burden on developers, reduces the design cost, and ensures the research and development progress of the task;

[0029] 2. The board card designed by the present invention is reconfigurable and reusable, and can adapt to different model tasks;

[0030] 3. The data format of the board card designed by the present invention is configurable and can adapt to different model tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is the system design scheme of the general payload manager's ground test board card of the present invention;

[0032] Figure 2 is the software working process of the general payload manager's ground test board card of the present invention;

[0033] Figure 3 is the Flash address division of the payload configuration table of the general payload manager's ground test board card of the present invention;

[0034] Figure 4 is the design block diagram of the instruction / working parameter function unit of the general payload manager's ground test board card of the present invention;

[0035] Figure 5 is the design block diagram of the scientific data function unit of the general payload manager's ground test board card of the present invention;

[0036] Figure 6 is the definition of the serial communication protocol between the ground test PC and the ground test FPGA of the general payload manager's ground test board card of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The general payload manager's ground test board card is deployed between the upper computer and the payload manager of the device under test, and is used to test the common function interfaces of the payload managers of different task models. The test board card includes: a payload configuration management module and a common function interface module; wherein,

[0038] The payload configuration management module is used to store the payload format configuration table sent by the upper computer in the external payload configuration table Flash; to read the configuration information pre-stored in the external payload configuration table Flash and perform corresponding processing according to the command sent by the upper computer; to send the generated scientific data, control signals and acquisition signals to the external common function interface module, and is also used to send the execution result of the ground test board card to the upper computer;

[0039] The common function interface module is used to implement communication with the common function interfaces of the payload manager.

[0040] The load configuration management module is implemented based on FPGA and non-volatile flash technology NOR Flash, and specifically includes: a configuration interface unit, a configuration control unit, a scientific data function unit, an instruction / engineering function unit, and a control logic unit; among them

[0041] The configuration interface unit is used to receive commands and load format configuration tables sent by the host computer and send them to the configuration control unit; it is also used to send the execution results of the ground test board card to the host computer;

[0042] The configuration control unit is used to receive commands and / or load format configuration tables from the host computer, perform corresponding parsing, write the parsed commands into the corresponding registers, write the parsed configuration information into the external load configuration table Flash, and is also used to read commands from the registers to the instruction / engineering function unit, and read configuration information from the external load configuration table Flash to the scientific data function unit and the control logic unit;

[0043] The scientific data function unit is used to generate scientific data in a corresponding format according to the configuration information;

[0044] The instruction / engineering function unit is used to generate load instructions in a corresponding format according to the commands;

[0045] The control logic unit is used to implement the control logic of the external functional chip according to the configuration information and store the results, and the results include AD acquisition results, pulse detection results, GPIO detection results, and second pulses.

[0046] The technical solution of the present invention will be described in detail below with reference to the drawings and embodiments.

[0047] Embodiment 1

[0048] The present invention proposes a system design solution for a ground test board card of a general load manager, as Figure 1 shown, the hardware consists of a ground test board card for the load manager. The ground test board card is connected to the ground test PC host computer and the load manager of the device under test, and is used to test the common function interfaces of the load managers of different mission models.

[0049] The ground test PC is configured with bus boards, such as 1553B boards, CAN bus boards, RS422 boards, or LVDS boards; the platform bus and high-speed data interfaces are directly connected to the ground test PC of the simulation platform using traditional solutions, and the host computer tests the load management. Other common function interfaces of the load manager, such as telemetry and remote control input / output interfaces, load scientific data interfaces, and load instruction / engineering response interfaces, are completed by the ground test board card of the general load manager of the present invention.

[0050] The general load manager ground test board card of the present invention realizes the following functions: configuration interface function for communicating with the PC host computer, configuration control function for configuring each functional module, scientific data output function for analog load, analog load command response function, analog load analog quantity output function, analog platform AD acquisition function, analog platform OC control function, analog load pulse detection function, analog platform second pulse generation function, and GPIO input / output function.

[0051] The general load manager ground test board card of the present invention is characterized in that the hardware implementation platform for the designed functions is composed of a ground test FPGA, a load configuration table FLASH, and various common function interface chips. Among them, the ground test FPGA realizes the digital logic of the above functions; the load configuration table Flash is used to store the configuration information of each functional unit in the FPGA; various common function interface chips are used for the hardware interfaces of the board card interface functions, such as RS422 transmit / receive chips, LVDS transmit / receive chips, AD chips, DA chips, OC gates, bus buffers SN74LVTH162245 and other chips.

[0052] The general load manager ground test board card of the present invention is characterized in that its general design is realized by the ground test FPGA and the load configuration table Flash: when applying specific model tasks, the registers of the ground test FPGA need to be configured according to the type, quantity, and data format of the interfaces of the platform and the load, and these information are stored in the load configuration table Flash according to the predefined addresses; subsequent power-on does not require the ground test PC to reconfigure, and the ground test FPGA automatically reads the configuration information from the load configuration table Flash to configure each functional module.

[0053] The specific software working process of the general load manager ground test board card of the present invention is as Figure 2 shown: for specific model tasks, the load commands and scientific data formats are determined, and the load command and scientific format configuration tables are formed according to this format; the host computer sends the load commands and scientific format configuration tables to the FPGA through the serial port, and the FPGA writes them into the load configuration table Flash. After the subsequent FPGA is powered on, it first checks the address 0 of the load configuration table Flash to verify whether the data in the configuration Flash is available: if available, it configures the register groups of each functional unit according to the data in the load configuration table Flash, and then waits for the start command from the host computer and responds to the processing results according to the command of the host computer; if not available, it enters the waiting configuration command mode.

[0054] The general load manager ground test board card of the present invention is characterized in that the configuration information stored in the load configuration table Flash is indexed according to the Flash hardware address space, and the configuration information includes: scientific data format, instruction and engineering response format, communication protocol selection and configuration, external interface chip selection, configuration information of modules such as AD / DA / OC / GPIO, etc.

[0055] As Figure 3 shown is the address division of the load configuration table Flash. The system register address is 0x00 - 0x1f, the AD acquisition control register is 0x20 - 0x3f, the OC control register address is 0x40 - 0x5f, the DA control register address is 0x60 - 0x7f, the pulse detection register address is 0x80 - 0x9f, the GPIO control register address is 0xa0 - 0xbf, and the reserved address for subsequent function expansion is 0xc0 - 0xfff. The scientific data transmission configuration address is 0x1000 - 0x1fff, where the address of channel 1 is 0x1000 - 0x10ff, and the address of channel 2 is 0x1100 - 0x11ff. Each channel occupies 256 addresses; the instruction and engineering parameter configuration address is 0x2000 - 0x2fff, where the address of channel 1 is 0x2000 - 0x20ff, and the address of channel 2 is 0x2100 - 0x21ff. Each channel occupies 256 addresses.

[0056] The general load manager ground test board card of the present invention is characterized in that the ground test FPGA design consists of a configuration interface unit 1, a configuration control unit 2, a scientific data function unit 3, an instruction / engineering function unit 4, a DA control unit 5, an AD acquisition unit 6, an OC control unit 7, a pulse detection unit 8, a GPIO control unit 9, and a second pulse generation unit 10; among them

[0057] 1) The configuration interface unit 1 is used to implement the serial bus protocol for communicating with the PC, such as USB or serial port UART;

[0058] 2) The configuration control unit 2 is used to implement the parsing of PC commands and configuration information, write them to the corresponding registers and the external load configuration table Flash, and read the register and external load configuration table Flash data for output; the system register is in this module;

[0059] 3) The scientific data function unit 3, as Figure 4 shown, is used to generate scientific data in the corresponding format according to the PC configuration information. There are 16 channels in total, which can be set to different formats. The data format is stored in the RAM of each channel, and the register is used to select the output data format, such as UART, 8b / 10b encoding, or three - wire system. The register is used to select the output level as RS422 level or LVDS level;

[0060] 4) The instruction / engineering function unit 4, as Figure 5 shown, is used to generate payload instructions in a corresponding format according to the PC configuration information. There are 16 channels in total, which can be set to different formats. The data format is stored in the RAM of each channel. The default output data format is UART, and the output can be configured as a duplex or half-duplex bus mode;

[0061] 5) The DA control unit 5, AD acquisition unit 6, OC control unit 7, pulse detection unit 8, GPIO control unit 9, and second pulse generation unit 10 are used to implement the control logic of the external function chips according to the configuration information and store the results.

[0062] The ground test board of the general payload manager of the present invention is characterized in that the ground test PC communicates with the ground test FPGA through a serial bus (USB or serial port): the ground test PC sends configuration information or commands to the ground test FPGA, such as sending scientific data, starting an AD acquisition once, sending a certain OC, or modifying the parameters of a certain DA; the ground test FPGA feeds back the execution results to the ground test PC, which are parsed and displayed by the PC. The execution results include: AD acquisition results, pulse detection results, GPIO detection results, etc.

[0063] As Figure 6 shown, there are the following four types defined for the serial communication protocol between the ground test PC and the ground test FPGA. The external payload configuration table Flash uses a NOR Flash with 24 address lines and a bit width of 16 bits (a non-volatile flash memory technology), or a Flash with a smaller address space can also be used, and the operating principle is the same. The serial communication protocol between the ground test PC and the ground test FPGA is defined as follows:

[0064] 1) Half-word write operation: write command + write address + write data, where the write command is 1 byte, defined as 0xE2; the write address is 3 bytes, and the address order is defined as A[23:16], A[15:8], A[7:0]; the write data is 2 bytes, and the byte order is D[15:8], D[7:0].

[0065] 2) Half-word read operation: read command + read address, waiting for the FPGA to send response data; where the read command is 1 byte, defined as 0xD2; the read address is 3 bytes, and the address order is defined as A[23:16], A[15:8], A[7:0]; the FPGA sends response data of 2 bytes, and the byte order is D[15:8], D[7:0].

[0066] 3) Continuous write operation: Write command + write start address + number of write data + write data. Among them, the write command is 1 byte, defined as 0xEE; the start write address is 3 bytes, and the address order is defined as A[23:16], A[15:8], A[7:0]; the number of write data is 3 bytes, and at most 2 24 data can be written; the write data is in ascending order of address. First, write the high 8 bits of the half word and then the low 8 bits.

[0067] 4) Continuous read operation: Read command + read address + number of read data, wait for the FPGA to send response data; among them, the read command is 1 byte, defined as 0xDD; the start read address is 3 bytes, and the address order is defined as A[23:16], A[15:8], A[7:0]; the number of read data is 3 bytes, and at most 2 24 data can be read; the FPGA sends response data, and the read data is in ascending order of address. First, read the high 8 bits of the half word and then the low 8 bits.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A test board for a general payload manager, deployed between the host computer and the payload manager of the device under test, is used to test the common function interfaces of the payload managers of different mission models, and is characterized in that The test board card includes: a payload configuration management module and a common function interface module; among which, The payload configuration management module is used to store the payload format configuration table sent by the host computer in the external payload configuration table Flash; to read the configuration information pre-stored in the external payload configuration table Flash, and perform corresponding processing according to the command sent by the host computer; to send the generated scientific data, control signals and acquisition signals to the common function interface module, and also to send the execution result of the ground detection test board card to the host computer; The common function interface module is used to implement the connection circuit with the common function interface of the payload manager; It includes: an AD acquisition unit, an OC control unit, a pulse detection unit, a GPIO control unit and a second pulse generation unit; The configuration information includes: scientific data format, payload instruction format, working parameter response format, communication protocol selection and configuration, configuration of the common function interface module and configuration of the payload configuration management module; The payload configuration management module is implemented based on FPGA and non-volatile flash technology NOR Flash, and specifically includes: a configuration interface unit, a configuration control unit, a scientific data function unit, an instruction / working parameter function unit and a control logic unit; among which, The configuration interface unit is used to receive the command and payload format configuration table sent by the host computer and send them to the configuration control unit; it is also used to send the execution result of the ground detection test board card to the host computer; The configuration control unit is used to receive the command and / or payload format configuration table from the host computer, perform corresponding parsing and write the parsed command into the corresponding register, write the parsed configuration information into the external payload configuration table Flash, and is also used to read the command from the register to the instruction / working parameter function unit, and read the configuration information from the external payload configuration table Flash to the scientific data function unit and the control logic unit; The scientific data function unit is used to generate scientific data in the corresponding format according to the configuration information; The instruction / working parameter function unit is used to generate payload instructions in the corresponding format according to the command; The control logic unit is used to implement the control logic of the external function chip according to the configuration information and store the results, and the results include AD acquisition results, pulse detection results, GPIO detection results and second pulses; The scientific data function unit includes 16 channels, and different data formats and different output levels are selected through registers. The data formats include UART, 8b / 10b encoding and three-wire system, and the output levels include RS422 level and LVDS level; The instruction / working parameter function unit includes 16 channels, corresponding to different data formats. The data formats include UART, duplex and half-duplex bus modes, and UART is adopted by default.

2. The test board card of the general load manager according to claim 1, characterized in that, The address space of the payload configuration table Flash is pre-allocated according to the registers corresponding to the units set by the payload management module.

3. The test board card for detecting the general load manager according to claim 1, characterized in that, The common function interface module includes an RS422 sending / receiving chip, an LVDS sending / receiving chip, an AD chip, a DA chip, an OC gate and a bus buffer chip.

4. The test board card for detecting the general load manager according to claim 1, characterized in that, Serial communication is adopted between the test board and the host computer, including half-word write operation, half-word read operation, continuous write operation and continuous read operation; among them, The half-word write operation includes: 1-byte write command, 3-byte write address and 2-byte write data, using the big-endian order; The half-word read operation includes: 1-byte read command, 3-byte read address and 2-byte response data of the FPGA, using the big-endian order; The continuous write operation includes: 1-byte write command, 3-byte starting write address, 3-byte number of write data and write data; The continuous read operation includes: 1-byte read command, 3-byte starting read address, 3-byte number of read data and response data of the FPGA.

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