Multi-channel audio acquisition timing control method and device

Abstract

The present application relates to the technical field of timing control, in particular to a multi-channel audio acquisition timing control method and device, the method uses timing control algorithm and SPI interface, and the sampling clock frequency is set to be consistent with the audio file playing frequency; when the Ram reading and writing address timing is performed, Ram1 is read according to the assignment of the counter Counter_AD_I and the assignment of the counter Counter_AD_O; when the Ram reading and writing alternate timing is performed, Ram1_A and Ram1_B appear alternately in reading and writing, and the relationship between Counter_AD_I and 1023 is used to further judge whether to use beat A or beat B for reading and writing alternation, wherein Counter_AD_I is the address of writing Ram, and Counter_AD_O is the address of reading Ram. The microphone can obtain higher quality audio data; the microphone and the transmission optical fiber have insulation and explosion-proof characteristics; the optical fiber has small long-distance transmission loss.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of timing control, in particular to a multi-channel audio acquisition timing control method and device. BACKGROUND

[0002] Multi-channel audio acquisition system is widely used in monitoring system. However, Windows / Linux operating system generally only supports one sound card hardware, so when multiple audio inputs are needed, the operating system kernel program needs to be modified, which increases the difficulty of system development.

[0003] However, the system in this paper uses high-precision AD chip to collect audio signals, which can obtain higher audio signal-to-noise ratio, but the interface cannot be compatible with the sound card interface of the operating system, which makes it more difficult for the operating system to read multi-channel audio signals.

[0004] It can be considered to use the external interface (such as SPI interface) of the operating system to directly read AD data. However, the real-time performance of Windows / Linux operating system is poor, and once the data reading time lags, it will affect the audio quality. At the same time, uninterrupted reading of audio data will also occupy the resources of the operating system.

[0005] Therefore, this paper proposes a multi-channel audio acquisition timing control method, which uses SPI interface to greatly simplify the reading timing of the operating system and reduce its resource consumption. SUMMARY

[0006] In view of the shortcomings of the prior art, the present application discloses a multi-channel audio acquisition timing control method and device, which is used to solve the above problems.

[0007] The present application is realized by the following technical solutions:

[0008] In a first aspect, the present application provides a multi-channel audio acquisition timing control method, which uses timing control algorithm and SPI interface, and sets the sampling clock frequency consistent with the audio file playback frequency;

[0009] When performing Ram read-write address timing, read Ram1 according to the assignment of Counter_AD_I and the assignment of Counter_AD_O;

[0010] When performing Ram read-write alternating timing, Ram1_A and Ram1_B appear alternately in reading and writing, and according to the size relationship between Counter_AD_I and 1023, it is further judged to use beat A or beat B for reading and writing alternation, wherein Counter_AD_I is the address of writing Ram, and Counter_AD_O is the address of reading Ram.

[0011] Further, in the method, the rising edge of the reset signal, the Counter_AD_I is assigned 0, and the Counter_AD_O is assigned 1024.

[0012] Further, in the method, the falling edge of the sampling clock starts to judge whether Counter_AD_I≤2047, if yes, the Counter_AD_I is added by one; if no, the Counter_AD_I is assigned 0 and the Counter_AD_O is assigned 1024.

[0013] The falling edge of the Ram1 reading clock drives the Counter_AD_O to be added by one.

[0014] Further, in the method, the user program reads the Ram1 after the rising edge of the SPI reading start signal to prevent the user program of the Raspberry Pi from assigning the Counter_AD_O at the same time.

[0015] Further, in the method, it is judged whether Counter_AD_I≤1023, if yes, it is the beat A, at this time, the Ram1_A interface is configured to write audio data:

[0016] Address<-Counter_AD_I;

[0017] Clock<-sampling clock;

[0018] Data<-audio input data 1;

[0019] Wren<-1;

[0020] Q is suspended;

[0021] At the same time, the Ram1_B interface is configured to read audio data:

[0022] Address<-Counter_AD_O-1024;

[0023] Clock<-Ram1 reading clock;

[0024] Data is suspended;

[0025] Wren<-0;

[0026] Q->audio output data 1;

[0027] Wherein, the symbols “<-” and “->” represent the interface connection relationship and signal direction.

[0028] Further, in the method, it is judged whether Counter_AD_I≤1023, if not, it is the beat B, at this time, the Ram1_A interface is configured to read the audio data:

[0029] Address<-Counter_AD_O;

[0030] Clock<-Ram1 reading clock;

[0031] Data is suspended;

[0032] Wren<-0;

[0033] Q->audio output data 1;

[0034] At the same time, the Ram1_B interface is configured to write the audio data:

[0035] Address<-Counter_AD_I-1024;

[0036] Clock<-sampling clock;

[0037] Data<-audio input data 1;

[0038] Wren<-1;

[0039] Q is suspended;

[0040] Wherein, the symbol "<-" and "->" represents the interface connection relationship and signal direction.

[0041] Further, in the method, if 1≤Counter_AD_I≤500 or 1025≤Counter_AD_I≤1525, the SPI read start is high, otherwise, the SPI read start is low.

[0042] In the second aspect, the application provides a multi-channel audio acquisition timing control device, which is used for realizing the multi-channel audio acquisition timing control method in the first aspect, and comprises a storage module, a chip selection gating module and a Ram interface.

[0043] Further, the storage module comprises:

[0044] A main frequency clock, 1bit input signal, greater than 50MHz;

[0045] A reset signal, 1bit input signal, becomes 0 after generating a 100us positive pulse after power-on;

[0046] Sampling clock, 1bit output signal, which is obtained by dividing the main frequency clock, the sampling clock is 24KHz or 48KHz;

[0047] Audio input data N, 16bits input signal, is the N channel audio data collected, which is generated by an analog-digital conversion chip.

[0048] Further, the Ram interface comprises

[0049] Single Ram block, storage depth is 1024, storage width is 16bits;

[0050] The external interface comprises

[0051] Address, 10bits input and output, read and write address;

[0052] Clock, 1bit input, rising edge drives data input or output;

[0053] Data, 16bits input, write data;

[0054] Wren, 1bit input, controls Ram read and write mode, 1 for writing, 0 for reading;

[0055] Q, 16bits output, read data.

[0056] The present application has the beneficial effects of:

[0057] The present application utilizes sound wave vibration to generate light interference to obtain audio signals, and the microphone is a passive device; the transmission between the microphone and the storage device is optical signal transmission, so that the microphone of the present application can obtain higher quality audio data; the microphone and the transmission optical fiber have insulation and explosion-proof characteristics; the optical fiber has small long-distance transmission loss. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description, and obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0059] Figure 1 is the control flow chart of the multi-channel audio acquisition timing control algorithm of the embodiment of the present application;

[0060] Figure 2 is the beat A connection relationship diagram of the storage module of the embodiment of the present application;

[0061] Figure 3is a beat B connection relationship diagram of the storage module of the embodiment of the present application;

[0062] Figure 4 is a single-channel write and read timing diagram of the embodiment of the present application;

[0063] Figure 5 is a Counter_AD_O curve diagram of the embodiment of the present application;

[0064] Figure 6 is an embedded device block diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0066] Embodiment 1

[0067] Referring to Figure 1 , the present embodiment provides a multi-channel audio acquisition timing control algorithm. The storage module and the chip selection strobe module in the present embodiment, the Raspberry Pi and the user program need to read audio data according to the agreed timing.

[0068] In the present embodiment, as long as the SPI interface program needs to read audio data according to the agreed timing, the user program can also run on other Linux development boards or in Windows.

[0069] The present embodiment further provides a multi-channel audio acquisition timing control method according to the algorithm. The method uses the timing control algorithm and the SPI interface, and sets the sampling clock frequency to be consistent with the audio file playback frequency.

[0070] When the present embodiment performs the Ram read and write address timing, the Ram1 is read according to the assignment of the counter Counter_AD_I and the assignment of the Counter_AD_O.

[0071] When the present embodiment performs the Ram read and write alternate timing, Ram1_A and Ram1_B appear alternately in reading and writing, and according to the size relationship between Counter_AD_I and 1023, it is further judged to use beat A or beat B to perform the read and write alternation, wherein Counter_AD_I is the address of writing Ram, and Counter_AD_O is the address of reading Ram.

[0072] Compared with the general electric signal transmission audio signal, the embodiment adopts an optical fiber sensor as a microphone, uses sound wave vibration to generate light interference to obtain an audio signal; the microphone is a passive device; and optical signal transmission is performed between the microphone and a storage device.

[0073] Therefore, the microphone of the embodiment scheme can obtain higher quality audio data; the microphone and the transmission optical fiber have insulation and explosion-proof characteristics; and the optical fiber has small long-distance transmission loss.

[0074] The embodiment scheme is suitable for dormitory monitoring, high-voltage transmission abnormal signal acquisition, and audio acquisition in high-risk scenes (coal mines or petrochemical industries).

[0075] Embodiment 2

[0076] In a specific implementation layer, the embodiment provides a method for sampling clock frequency, the sampling clock frequency of the embodiment is consistent with the audio file playing frequency, and the embodiment is preferably 24 KHz, that is, the sampling clock is obtained by dividing the 50 MHz signal 2083.

[0077] When the Ram read-write address timing is performed, taking audio channel one as an example, the read-write address timing of Ram1_A and Ram1_B is detailed as Step ①-④, in which Counter_AD_I is the address of the write Ram, and Counter_AD_O is the address of the read Ram.

[0078] ① The reset signal rising edge, the counter Counter_AD_I is assigned to 0, and the Counter_AD_O is assigned to 1024;

[0079] ② The sampling clock falling edge starts to judge whether Counter_AD_I≤2047, if yes, Counter_AD_I is incremented by one; if not, Counter_AD_I is assigned to 0 and Counter_AD_O is assigned to 1024;

[0080] ③ The Ram1 read clock falling edge drives Counter_AD_O to be incremented by one;

[0081] ④ Constraint condition I: the Raspberry Pi user program should avoid assigning values to Counter_AD_O at the same time in Step ② and ③.

[0082] The user program of the embodiment reads Ram1 after the SPI read start signal rising edge, which can meet the constraint condition.

[0083] When the Ram read-write alternating timing is performed, taking audio channel one as an example, Ram1_A and Ram1_B appear alternately in reading and writing, and the flow is as follows:

[0084]

[0085] Ram1_A interface is configured to write audio data:

[0086] Address <- Counter_AD_I;

[0087] Clock <- sampling clock;

[0088] Data <- audio input data 1;

[0089] Wren <- 1;

[0090] Q is suspended;

[0091] In this embodiment, Ram1_B interface is also configured to read audio data:

[0092] Address <- Counter_AD_O - 1024;

[0093] Clock <- Ram1 read clock;

[0094] Data is suspended;

[0095] Wren <- 0;

[0096] Q -> audio output data 1;

[0097] Wherein, the symbol "<-" and "->" represent the interface connection relationship and signal direction.

[0098] In this embodiment, it is judged whether Counter_AD_I≤1023, and if not, it is beat B

[0099] Ram1_A interface is configured to read audio data:

[0100] Address <- Counter_AD_O;

[0101] Clock <- Ram1 read clock;

[0102] Data is suspended;

[0103] Wren <- 0;

[0104] Q -> audio output data 1;

[0105] In this embodiment, Ram1_B interface is also configured to write audio data:

[0106] Address <- Counter_AD_I - 1024;

[0107] ​Clock <- sampling clock;

[0108] Data <- audio input data 1;

[0109] Wren <- 1;

[0110] Q is suspended;

[0111] 2. If 1≤Counter_AD_I≤500 or 1025≤Counter_AD_I≤1525, then the SPI read start is high, otherwise the SPI read start is low.

[0112] 3. Constraint II: In one beat (Beat A or B), the number of Ram1 read clocks must be 1024, and must be completed before the beat switches.

[0113] In this embodiment, the actual connection relationship of the storage module under Beats A and B is shown in Figure 2 and Figure 3 .

[0114] In this embodiment, the Counter_AD_I is incremented by one in the range [0, 2047] at the falling edge of the sampling clock.

[0115] When Counter_AD_I∈[0, 1023], it is Beat A, as shown in Figure 2 , Ram1_A, Ram2_A…Ram8_A are in write mode, and Ram1_B, Ram2_B…Ram8_B are in read mode.

[0116] When Counter_AD_I∈[1024, 2047], it is Beat B, as shown in Figure 3 , Ram1_A, Ram2_A…Ram8_A are in read mode, and Ram1_B, Ram2_B…Ram8_B are in write mode.

[0117] In this embodiment, the Counter_AD_I completes 1024 Ram1 write clocks in one beat, as shown in the Counter_AD_I curve in Figure 4 .

[0118] In this embodiment, audio channels 2 to 8 are considered. In Beat A, Ram1_A~Ram8_A write audio data of the respective channels in parallel, while Ram1_B~Ram8_B take the mode of reading in turn, and the specific reading time is determined by the user program, as shown in the Counter_AD_O curve in Figure 5 .

[0119] The embodiment is the same as the above. At the beat B, the Ram1_B~Ram8_B write the audio data of the respective channels in parallel, and the Ram1_A~Ram8_A take the mode of reading in sequence. The specific timing is shown in the following table. Figure 1 The chip select gating module determines.

[0120] Embodiment 3

[0121] The embodiment provides a multi-channel audio acquisition timing control device, as shown in the accompanying drawings, comprising a storage module, a chip select gating module and a Ram interface. Meanwhile, the device is installed with a Raspberry Pi and a user program, and the program reads the audio data according to the agreed timing. Figure 1

[0122] The storage module of the embodiment comprises

[0123] The main frequency clock is a 1bit input signal, and the embodiment preferably is 50MHz.

[0124] The reset signal is a 1bit input signal, and becomes 0 after generating a 100us positive pulse after power-on.

[0125] In the application of the embodiment, the storage module initializes the internal counter at the rising edge thereof.

[0126] The sampling clock is a 1bit output signal, which is obtained by dividing the main frequency clock. The sampling clock is generally 24KHz or 48KHz.

[0127] In the application of the embodiment, the audio input data is collected at the rising edge thereof, and the data is stored in the Ram at the falling edge thereof, which can effectively prevent the competition and risk of data.

[0128] The audio input data 1 is a 16bits input signal, which is the 1-channel audio data collected. Generally, the signal is generated by an analog-to-digital conversion (AD) chip.

[0129] The embodiment preferably uses a 16-bit AD chip. If the AD chip of the embodiment has less than 16 bits, the high bits can be filled with 0 to 16 bits.

[0130] The chip select gating module of the embodiment selects SPI_CS, SPI_SCLK and SPI_MISO as the standard SPI interface.

[0131] In the Ram interface of the embodiment, the storage depth of a single Ram block (Ram1_A, Ram2_A or Ram1_B, Ram2_B) is 1024, and the storage width is 16bits.

[0132] The external interface of the embodiment is

[0133] Address: 10bits input and output, read and write address;​

[0134] Clock: 1bit input, rising edge drive data input or output;

[0135] Data: 16bits input, write data;

[0136] Wren: 1bit input, control Ram read-write mode, 1 for writing, 0 for reading;

[0137] Q: 16bits output, read data.

[0138] When the embodiment works, the following is specifically as follows:

[0139] Audio input data 2-8: consistent with audio input data 1.

[0140] SPI read start: 1bit output signal, user program starts SPI interface reading at rising edge.

[0141] Ram1 read clock: 1bit input signal, used for external reading of audio data of Ram1_A and Ram1_B.

[0142] Audio output data 1: 16bits output signal, output to external module under the drive of Ram1 read clock.

[0143] Ram2-8 read clock: consistent with Ram1 read clock.

[0144] Audio output data 2-8: consistent with audio output data 1.

[0145] Embodiment 4

[0146] On other levels, on the basis of embodiment 3, the embodiment provides a multi-channel audio acquisition applied to a monitoring system. Since one optical fiber sensor outputs 3 AD signals, therefore, the 3 signals need to be demodulated by an embedded system at the data storage device end, so that the audio signal can be restored.

[0147] At the same time, in order to obtain higher audio sensitivity, 16 or 18 bit AD sampling is also used in the embedded system. However, the general multi-channel audio acquisition chip cannot meet the above demodulation algorithm and AD sampling accuracy, therefore, the sampling, demodulation, storage and network streaming of the audio signal in the embodiment all need to develop special embedded devices. The block diagram is as shown in Figure 6 .

[0148] In view of power consumption, volume and cost, the raspberry is selected as the embedded system, the FPGA is selected as the audio acquisition chip and 24 channels of AD are collected at a frequency of 24KHz in the embodiment. The biggest problem is how to send the demodulated 8 channels of audio (16 bits / 24KHz) to the raspberry.

[0149] Based on the above, the raspberry in the embodiment provides an SPI port (maximum frequency 64M), and the user program in the raspberry can read external data by using the port. However, the embedded system of the raspberry does not support interaction with the FPGA at a frequency of 24KHz, which will completely occupy the resources of the CPU.

[0150] Therefore, the FPGA in the embodiment stores the audio data into the RAM of itself and transmits the data to the raspberry at a lower frequency (such as 23Hz). The RAM of the FPGA is divided into Ram_A and Ram_B, and the storage and transmission of data are alternately performed (in beat A, Ram_A stores real-time audio and Ram_B waits and completes transmission; in beat B, Ram_B stores real-time audio and Ram_A waits and completes transmission).

[0151] The switching of beats A and B in the embodiment is completely controlled by the FPGA, and the user program in the raspberry only needs to read data according to the agreed byte number after receiving the "SPI read start" signal, so as to ensure the continuity of multi-channel audio data.

[0152] In summary, the application uses the interference of light generated by sound wave vibration to obtain audio signals, and the microphone is a passive device. The light signal is transmitted between the microphone and the storage device, so that the microphone of the application can obtain higher quality audio data. The microphone and the transmission optical fiber have the characteristics of insulation and explosion-proof. The loss of long-distance transmission of the optical fiber is small.

[0153] The above embodiments are only used to illustrate the technical solutions of the application, but not to limit it. Although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features. The modification or replacement does not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A method for timing control of multi-channel audio acquisition, characterized in that, The method uses a timing control algorithm and an SPI interface, and sets the sampling clock frequency to be consistent with the audio file playing frequency; When the Ram read / write address timing is performed, the Ram1 is read according to the assignment of the counter Counter_AD_I and the assignment of the counter Counter_AD_O, wherein the Ram1 includes two buffer zones Ram1_A and Ram1_B; When the Ram read / write alternate timing is performed, the Ram1_A and the Ram1_B are in read and write alternation, and the read / write alternation is performed using the beat A or the beat B according to the size relationship between the counter Counter_AD_I and 1023, wherein the beat A is used when the counter Counter_AD_I is less than or equal to 1023, and the beat B is used when the counter Counter_AD_I is greater than 1023, in the beat A, the Ram1_A writes audio data and the Ram1_B reads audio data, and in the beat B, the Ram1_A reads audio data and the Ram1_B writes audio data, wherein the counter Counter_AD_I is the address for writing the Ram, and the counter Counter_AD_O is the address for reading the Ram.

2. The method of claim 1, wherein, In the method, the rising edge of the reset signal is used to assign the counter Counter_AD_I as 0 and the counter Counter_AD_O as 1024.

3. The method of claim 1, wherein, In the method, the falling edge of the sampling clock is used to start judging whether the counter Counter_AD_I is less than or equal to 2047, if yes, the counter Counter_AD_I is incremented by 1, and if no, the counter Counter_AD_I is assigned as 0 and the counter Counter_AD_O is assigned as 1024. The falling edge of the Ram1 read clock is used to drive the counter Counter_AD_O to be incremented by 1.

4. The method of claim 3, wherein, In the method, the user program reads the Ram1 after the rising edge of the SPI read start signal, so as to prevent the user program of the Raspberry Pi from assigning the counter Counter_AD_O at the same time.

5. The method of claim 1, wherein, In the method, it is judged whether the counter Counter_AD_I is less than or equal to 1023, if yes, it is the beat A, and the Ram1_A interface is configured to write audio data: Address is an address input, connected to the counter Counter_AD_I; Clock is a clock input, connected to the sampling clock; Data is a data input, connected to audio input data 1, wherein the audio input data 1 is audio input data of the first channel; Wren is a write enable input, set as 1; Q is a data output, suspended; Meanwhile, the Ram1_B interface is configured to read audio data: Address is an address input, connected to the counter Counter_AD_O-1024; Clock is a clock input, connected to the Ram1 read clock; Data is suspended; Wren is set as 0; Q is connected to audio output data 1.

6. The method of claim 5, wherein, In the method, it is judged whether the counter Counter_AD_I is less than or equal to 1023, if no, it is the beat B, and the Ram1_A interface is configured to read audio data: Address <-Counter_AD_O; Clock <-Ram1 read clock; Data is suspended; Wren <-0; Q -> audio output data 1; Meanwhile, the Ram1_B interface is configured to write audio data: Address <- Counter_AD_I-1024; Clock <- sampling clock; Data <- audio input data 1; Wren <- 1; Q is suspended; Wherein, the symbols "<-" and "->" represent the interface connection relationship and signal direction.

7. The method of claim 1, wherein, In the method, if 1<=Counter_AD_I<=500 or 1025<=Counter_AD_I<=1525, the SPI read start is high, otherwise the SPI read start is low.

8. A multi-channel audio acquisition timing control apparatus for implementing the multi-channel audio acquisition timing control method according to any one of claims 1 to 7, characterized in that, The device comprises a storage module, a chip selection gating module and a Ram interface, and is installed with a Raspberry Pi and a user program, and the program reads audio data according to a time sequence.

9. A multi-channel audio acquisition timing control apparatus according to claim 8, wherein, The storage module comprises: a main frequency clock, a 1bit input signal, greater than 50MHz; a reset signal, a 1bit input signal, becoming 0 after generating a 100us positive pulse after power-on; a sampling clock, a 1bit output signal, obtained by frequency division of the main frequency clock, the sampling clock being 24KHz or 48KHz; audio input data N, a 16bits input signal, N-channel audio data collected, generated by an analog-digital conversion chip.

10. The multi-channel audio acquisition timing control device of claim 8, wherein, The Ram interface comprises a single Ram block, a storage depth of 1024, a storage width of 16bits; an external interface comprising Address, a 10bits input and output, a read-write address; Clock, a 1bit input, a rising edge driving data input or output; Data, a 16bits input, write data; Wren, a 1bit input, controlling Ram read-write mode, 1 for writing, 0 for reading; Q, a 16bits output, read data.

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