Method, device, equipment and storage medium for sorting components in power grid wiring diagram

Abstract

The present invention discloses a method, device, equipment and storage medium for sorting components in a power grid wiring diagram. The method comprises: using a pre-trained convolutional neural network to extract the semantic features and position labels of each component on each bus from the power grid wiring diagram, and for each bus, all the components on the bus form a bus component set; in each bus component set, for each component, according to the semantic features of the component, the dispatch label of the component is obtained, according to the dispatch label and the position label, Pareto non-dominated sorting is performed, and according to the Pareto non-dominated sorting, the Pareto level of each component in the bus component set is obtained; and the Pareto level of each component is saved in the ledger of the power grid wiring diagram.

Description

Technical Field

[0001] The present invention belongs to circuit diagram processing technology, and in particular to a method, device, equipment and storage medium for sorting components in a power grid wiring diagram. Background Art

[0002] In intelligent power grid mapping, it is necessary to arrange the components in the power grid wiring diagram blueprint in the correct logical order. However, in actual drawing, the components are often placed in disorder, difficult to sort in the correct logical order, and the dispatch number and position are confused.

[0003] Based on this, a solution is needed that can realize intelligent sorting of the components in the power grid wiring diagram in the required correct order in automatic drawing. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose a method, device, equipment and storage medium for sorting components in a power grid wiring diagram.

[0005] Based on the above purpose, the present application provides a method for sorting components in a power grid wiring diagram, including:

[0006] Using a pre-trained convolutional neural network to extract semantic features and position labels of each element on each bus from a power grid wiring diagram, and for each bus, forming a bus element set with all the elements on the bus;

[0007] In each of the busbar component sets, for each of the components, a scheduling label of the component is obtained according to the semantic feature of the component, a Pareto non-dominated sorting is performed according to the scheduling label and the position label, and a Pareto level of each of the components in the busbar component set is obtained according to the Pareto non-dominated sorting;

[0008] The Pareto level of each of the components is saved in a ledger of the power grid wiring diagram.

[0009] Further, extracting the location label of each tuple device on each bus bar includes:

[0010] Placing the power grid wiring diagram in a coordinate system;

[0011] Obtaining the horizontal coordinate and the vertical coordinate of each element in the grid connection diagram in the coordinate system as the position of the element;

[0012] Obtaining the location tag according to the location;

[0013] A position label matrix is ​​created for each of the elements using a Gaussian mask.

[0014] Furthermore, the semantic features and position labels of each of the components on each bus are extracted from the power grid wiring diagram using a pre-trained convolutional neural network, including:

[0015] Construct a convolutional neural network by connecting the feature extraction network and the feature fusion network in series;

[0016] The shape, color, component type, text label, component name, scheduling label, angle and equipment information of the icon in the power grid wiring diagram are used as dimensions of the semantic feature to extract the semantic feature.

[0017] Further, a Pareto non-dominated sort is performed according to the scheduling label and the position label, and a Pareto level of each component in the bus component set is obtained according to the Pareto non-dominated sort, including:

[0018] In each of the busbar element sets, extracting the position label of each of the elements;

[0019] Obtain the horizontal coordinate and the vertical coordinate in the position tag;

[0020] According to the Pareto dominance principle, each of the position labels is sorted according to the strategy of minimizing the horizontal coordinate and the vertical coordinate, and a position level is obtained;

[0021] A Pareto non-dominated sort is performed according to the scheduling label and the position level, and the Pareto level is obtained.

[0022] Furthermore, according to the Pareto dominance principle, each of the position labels is sorted according to the strategy of minimizing the horizontal coordinate and the vertical coordinate, and a position level is obtained, including:

[0023] In the same set of busbar elements, the horizontal coordinate and the vertical coordinate of the position tag of each element are used as two target components;

[0024] For any given two target components, the dominance relationship between the two components is determined according to the first formula shown below:

[0025] All have f i (p a )≤f i (p b )

[0026] All have f i (p a )≤f i (p b )

[0027] Among them, x represents the horizontal coordinate, y represents the vertical coordinate, and p a and p b represents two different said elements;

[0028] In response to the first formula being true, determine the element p a Dominant element p b ;

[0029] In response to any of the elements dominating all of the other elements, determining the element as a non-dominated solution in the busbar element set, and defining the position level of the non-dominated solution as level 1;

[0030] Using the formula again, a non-dominated solution is determined among all the remaining elements, and the position level of the element corresponding to the non-dominated solution is defined as level 2;

[0031] In response to all the elements in the busbar element set obtaining position ranks, the sorting is terminated.

[0032] Further, performing a Pareto non-dominated sort according to the scheduling label and the position level and obtaining the Pareto level includes:

[0033] In the same busbar element set, the dispatch label and the position level of each element are used as two target components;

[0034] For any two given elements of the same busbar element set, the dominance relationship between the two elements is determined according to the second formula shown below:

[0035] All have f j (q a )≤f j (q b )

[0036] All have f i (q a )≤f i (q b )

[0037] Among them, m represents the scheduling label, n represents the location level, and q a and q b represents two different said elements;

[0038] In response to the second formula being true, determine the element q a Dominant Component q b ;

[0039] In response to any of the elements dominating all of the other elements, determining the element as a non-dominated solution in the busbar element set, and defining the Pareto level of the non-dominated solution as level 1;

[0040] Using the formula again, a non-dominated solution is determined in all the remaining elements, and the Pareto level of the target component corresponding to the non-dominated solution is defined as level 2;

[0041] In response to all the elements in the busbar element set obtaining Pareto ranks, the sorting is terminated.

[0042] Based on the same inventive concept, the present application also provides a device for sorting components in a power grid wiring diagram, comprising:

[0043] The preprocessing module is configured to use a pre-trained convolutional neural network to extract the semantic features and position labels of each element on each bus from the power grid wiring diagram, and for each bus, all the elements on the bus are grouped into a bus element set.

[0044] The sorting module is configured to obtain, for each element in each busbar element set according to the semantic feature of the element, a scheduling label of the element, perform Pareto non-dominated sorting according to the scheduling label and the position label, and obtain the Pareto level of each element in the busbar element set according to the Pareto non-dominated sorting.

[0045] A saving module is configured to save the Pareto level of each of the components into a ledger of the power grid wiring diagram.

[0046] Based on the same inventive concept, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the component sorting method in the power grid wiring diagram as described in any one of the above items is implemented.

[0047] Based on the same inventive concept, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the component sorting method in the above-mentioned power grid wiring diagram.

[0048] From the above, it can be seen that the method, device, equipment and storage medium for sorting components in a power grid wiring diagram provided by the present application are based on the Pareto dominance principle, and comprehensively consider the position labels and scheduling labels of the components to perform sorting. The horizontal and vertical coordinates are used as two target components to increase the accuracy of the position label sorting, and the position and scheduling labels are combined as two evaluation criteria for sorting, thereby achieving effective sorting of the components in the power grid wiring diagram and improving the accuracy of the sorting. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1 A flowchart of a method for sorting components in a power grid wiring diagram according to an embodiment of the present application;

[0051] Figure 2 This is a schematic diagram of the structure of a component sorting device in a power grid wiring diagram in an embodiment of the present application;

[0052] Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0054] The following detailed description is an exemplary description, which is intended to provide further detailed description of the present invention. Unless otherwise specified, all technical terms used in the present invention have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used in the present invention are only for describing specific embodiments, and are not intended to limit exemplary embodiments according to the present invention.

[0055] As described in the background technology section, the method for sorting components in the related power grid wiring diagram is still difficult to meet the needs of actual drawing.

[0056] In the process of implementing the present application, the applicant discovered that the main problem with the method for sorting components in the relevant power grid wiring diagram is that the arrangement standard for components is single, while the hierarchical relationship between components needs to be sorted from multiple dimensions.

[0057] It can be understood that the method can be executed by any device, equipment, platform, or device cluster having computing and processing capabilities.

[0058] The technical method of the present application is described in detail below through specific embodiments.

[0059] refer to Figure 1 , a method for sorting components in a power grid wiring diagram according to an embodiment of the present application comprises the following steps:

[0060] Step S101, using a pre-trained convolutional neural network to extract the semantic features and position labels of each component on each bus from the power grid wiring diagram, and for each bus, all the components on the bus are grouped into a bus component set.

[0061] In an embodiment of the present application, a pre-trained convolutional neural network for feature extraction is first used to extract the semantic features of the element. The convolutional neural network can be a DLA (Deep Learning Accelerator)-34 convolutional neural network composed of a feature extraction network and a scale feature fusion network connected in series.

[0062] Furthermore, the dimensions of the semantic features extracted by the convolutional neural network may include: shape, color, component type, text label, component name, scheduling label, angle and equipment information of the component in the power grid wiring diagram.

[0063] The dispatch label is the dispatch number of the component; the angle is the direction in which the component is placed in the power grid wiring diagram.

[0064] Furthermore, the convolutional neural network will output a semantic feature matrix corresponding to each component.

[0065] In this embodiment, the extraction of component semantic features may be performed according to different buses, that is, all components under each bus are regarded as a bus component set.

[0066] Furthermore, for all the elements in each busbar set, the position label of each element is determined using the coordinate system.

[0067] Specifically, the power grid connection diagram may be placed in a coordinate system, and the coordinate position of each component in the coordinate system may be determined according to the coordinate system.

[0068] Furthermore, based on the coordinate position, the position label of each component is calculated using a Gaussian mask, and the position label matrix of all components is formed by splicing.

[0069] Specifically, the following formula is used for the position label of each component:

[0070]

[0071]

[0072] Wherein, d represents the location label of each component, x and y are the center coordinates of the component in the coordinate system, and w and h are the width and height of the component in the circuit wiring diagram.

[0073] Furthermore, the above-mentioned position label Gaussian masks of each component are spliced ​​together to obtain the position label matrix D of all components under the busbar.

[0074] Based on the extraction of the semantic features and the extraction of the position labels, all the components under the bus can be obtained in the bus component set, as well as the position label matrix and the semantic feature matrix of each component.

[0075] Step S102: In each of the busbar component sets, for each of the components, obtain a scheduling label of the component according to the semantic feature of the component, perform Pareto non-dominated sorting according to the scheduling label and the position label, and obtain the Pareto level of each of the components in the busbar component set according to the Pareto non-dominated sorting.

[0076] In an embodiment of the present application, for each bus element set, based on the semantic feature matrix obtained above, the scheduling label of each element is extracted from the semantic feature matrix of the bus element set.

[0077] Furthermore, the scheduling labels and the position labels are used to perform a Pareto non-dominated sorting within the busbar element set.

[0078] In this embodiment, the Pareto non-dominated sorting obtains a non-inferior solution in the busbar element set according to the position rank and scheduling label of each element, so it is necessary to determine the position rank of each element by sorting the position label of each element.

[0079] Specifically, within the same busbar element set, for each element, its horizontal coordinate and vertical coordinate are taken as the two target components of the element. In this implementation, the position labels are Pareto sorted on the principle of smaller is better, that is, the elements that reach Min(x, y) are taken as the non-dominated solutions with respect to the position label in the busbar element set. In practice, it can also be done on the principle of larger is better according to specific needs.

[0080] Furthermore, the Pareto ranking is determined based on the dominance relationship shown in the following first formula:

[0081] All have f i (p a )≤f i (p b )

[0082] All have f i (p a )≤f i (p b )

[0083] Among them, x represents the horizontal coordinate, y represents the vertical coordinate, and p a and p brepresents two different elements, and i represents any one of the two target components.

[0084] Furthermore, if there is an element whose horizontal coordinate and vertical coordinate are both minimized at the same time, that is, there is no other element whose horizontal coordinate is smaller than the horizontal coordinate of this element, and there is no other element whose vertical coordinate is smaller than the vertical coordinate of this element, then it can be considered that with respect to the position label, this element can dominate all other elements, and this element can be used as the only non-dominated solution among all elements in its busbar element set, that is, a non-inferior solution, and the position level of this element is defined as level 1.

[0085] Furthermore, within the above-mentioned busbar element set, for the remaining other elements, the above-mentioned Pareto dominance principle is used to perform Pareto sorting again, non-dominated solutions are determined among the remaining elements, and the elements corresponding to the non-dominated solutions determined by the second Pareto sorting are defined as position level 2.

[0086] Furthermore, the above-mentioned Pareto non-dominated sorting is performed multiple times on the remaining elements in the above-mentioned busbar element set to determine the position level of each element one by one.

[0087] In this embodiment, since the elements on each busbar will not overlap, and in most cases all the elements on the busbar will have the same horizontal coordinate and a monotonically increasing or monotonically decreasing vertical coordinate; or have the same vertical coordinate and a monotonically increasing or monotonically decreasing horizontal coordinate, multiple Pareto non-dominated sortings can be performed to obtain the position level of each element.

[0088] Furthermore, in the busbar element set, the scheduling label of each element is different, and the scheduling label of each element shows a regular increase or decrease. For example, multiple elements on a busbar are logically arranged in 301, 302, 303, and 304. Therefore, the value of the scheduling label can be used as one of the target components in the following Pareto non-dominated sorting.

[0089] Furthermore, within the same busbar component set, for each component, the value and position level of the above-mentioned scheduling label are used to perform Pareto non-dominated sorting according to the principle of smaller is better; in practice, it can also be performed according to the principle of larger is better according to specific needs.

[0090] Specifically, the Pareto ranking is determined based on the dominance relationship shown in the following second formula:

[0091] All have f j (q a )≤f j (q b )

[0092] All have f i (q a )≤f i (q b )

[0093] Among them, m represents the scheduling label, n represents the location level, and q a and q b represents two different elements, and j represents any one of the two target components.

[0094] Furthermore, if there is an element whose position rank and scheduling label value both reach the minimum at the same time, that is, there is no other element whose position rank is smaller than the position rank of this element, and there is no other element whose scheduling label value is smaller than the scheduling label value of this element, then it can be considered that this element can dominate all other elements, and this element is used as the only non-dominated solution among all elements in its busbar element set, and the Pareto rank of this element is defined as 1.

[0095] Furthermore, within the above-mentioned busbar element set, for the remaining other elements, the above-mentioned Pareto dominance principle is used to perform Pareto sorting again, non-dominated solutions are determined among the remaining elements, and the elements corresponding to the non-dominated solutions determined by the second Pareto sorting are defined as Pareto level 2.

[0096] Furthermore, the above-mentioned Pareto non-dominated sorting is performed multiple times on the remaining elements in the above-mentioned busbar element set to determine the Pareto level of each element one by one.

[0097] Step S103: Save the Pareto level of each of the components in the ledger of the power grid wiring diagram.

[0098] In an embodiment of the present application, a ledger is created for a power grid wiring diagram to be processed in a database, the ledger is used to record relevant information of each component in the power grid wiring diagram, and multiple feature categories including the component Pareto level are set for each component in the ledger.

[0099] Furthermore, the Pareto level of each component is saved in the ledger.

[0100] It can be seen that the method for sorting components in the power grid wiring diagram of the embodiment of the present application is based on the Pareto dominance principle, and comprehensively considers the position labels and scheduling labels of the components to perform sorting. The horizontal and vertical coordinates are used as two target components to increase the accuracy of the position label sorting, and the position is combined with the scheduling label as two evaluation criteria for sorting, thereby realizing effective sorting of the components in the power grid wiring diagram and improving the accuracy of the sorting.

[0101] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0102] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0103] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, an embodiment of the present application further provides a device for sorting components in a power grid wiring diagram.

[0104] refer to Figure 2 , the component sorting device in the power grid wiring diagram includes: a preprocessing module 201, a sorting module 202 and a storage module 203;

[0105] The preprocessing module 201 is configured to: use a pre-trained convolutional neural network to extract the semantic features and position labels of each element on each bus from the power grid wiring diagram, and for each bus, group all the elements on the bus into a bus element set.

[0106] The sorting module 202 is configured to: in each of the busbar element sets, for each of the elements, obtain a scheduling label of the element according to the semantic feature of the element, perform Pareto non-dominated sorting according to the scheduling label and the position label, and obtain the Pareto level of each of the elements in the busbar element set according to the Pareto non-dominated sorting.

[0107] The saving module 203 is configured to save the Pareto level of each of the components in the ledger of the power grid wiring diagram.

[0108] Furthermore, the above-mentioned device can also include a position acquisition module, which is configured to: place the power grid wiring diagram in a coordinate system, obtain the horizontal and vertical coordinates of each element in the power grid wiring diagram in the coordinate system as the position of the element, and obtain the position label based on the position.

[0109] For the convenience of description, the above devices are described in terms of functions and are divided into various modules. Of course, when implementing the embodiments of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0110] The device of the above embodiment is used to implement the component sorting method in the corresponding power grid wiring diagram in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0111] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, an embodiment of the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the component sorting method in the power grid wiring diagram as described in any of the above embodiments is implemented.

[0112] Figure 3 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0113] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0114] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solution provided in the embodiment of the present application is implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0115] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0116] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0117] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0118] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0119] The device of the above embodiment is used to implement the component sorting method in the corresponding power grid wiring diagram in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0120] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the component sorting method in the power grid wiring diagram as described in any of the above embodiments.

[0121] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0122] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the component sorting method in the power grid wiring diagram described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0123] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0124] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0125] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0126] It is known from common technical knowledge that the present invention can be implemented by other embodiments that do not deviate from its spirit or essential features. Therefore, the above disclosed embodiments are only illustrative in all respects and are not exclusive. All changes within the scope of the present invention or within the scope equivalent to the present invention are included in the present invention.

Claims

1. A method for sorting components in a power grid wiring diagram, characterized in that: include: Using a pre-trained convolutional neural network to extract semantic features and position labels of each element on each bus from a power grid wiring diagram, and for each bus, forming a bus element set with all the elements on the bus; In each of the busbar component sets, for each of the components, a scheduling label of the component is obtained according to the semantic feature of the component, a Pareto non-dominated sorting is performed according to the scheduling label and the position label, and a Pareto level of each of the components in the busbar component set is obtained according to the Pareto non-dominated sorting; Saving the Pareto level of each of the components in a ledger of the power grid wiring diagram; The step of extracting the position label of each tuple device on each bus bar comprises: Placing the power grid wiring diagram in a coordinate system; Obtaining the horizontal coordinate and the vertical coordinate of each element in the grid connection diagram in the coordinate system as the position of the element; Obtaining the location tag according to the location; Using a Gaussian mask to establish a position label matrix for each of the components; The step of performing a Pareto non-dominated sorting according to the scheduling label and the position label, and obtaining a Pareto level of each component in the bus component set according to the Pareto non-dominated sorting, comprises: In each of the busbar element sets, extracting the position label of each of the elements; Obtain the horizontal coordinate and the vertical coordinate in the position tag; According to the Pareto dominance principle, each of the position labels is sorted according to the strategy of minimizing the horizontal coordinate and the vertical coordinate, and a position level is obtained; Performing a Pareto non-dominated sorting according to the scheduling label and the position level, and obtaining the Pareto level; According to the Pareto dominance principle, each of the position labels is sorted according to the strategy of minimizing the horizontal coordinate and the vertical coordinate, and the position level is obtained, including: In the same set of busbar elements, the horizontal coordinate and the vertical coordinate of the position tag of each element are used as two target components; For any given two target components, the dominance relationship between the two components is determined according to the first formula shown below: All have f i (p a )≤f i (p b ) All have f i (p a )≤f i (p b ) Among them, x represents the horizontal coordinate, y represents the vertical coordinate, and p a and p b represents two different said elements; In response to the first formula being true, determine the element p a Dominant element p b ; In response to any of the elements dominating all of the other elements, determining the element as a non-dominated solution in the busbar element set, and defining the position level of the non-dominated solution as level 1; Using the formula again, a non-dominated solution is determined among all the remaining elements, and the position level of the element corresponding to the non-dominated solution is defined as level 2; In response to all the elements in the busbar element set obtaining position ranks, the sorting is terminated; The performing of Pareto non-dominated sorting according to the scheduling label and the position level and obtaining the Pareto level includes: In the same busbar element set, the dispatch label and the position level of each element are used as two target components; For any two given elements of the same busbar element set, the dominance relationship between the two elements is determined according to the second formula shown below: All have f j (q a )≤f j (q b ) All have f i (q a )≤f i (q b ) Among them, m represents the scheduling label, n represents the location level, and q a and q b represents two different said elements; In response to the second formula being true, determine the element q a Dominant Component q b ; In response to any of the elements dominating all of the other elements, determining the element as a non-dominated solution in the busbar element set, and defining the Pareto level of the non-dominated solution as level 1; Using the formula again, a non-dominated solution is determined in all the remaining elements, and the Pareto level of the target component corresponding to the non-dominated solution is defined as level 2; In response to all the elements in the busbar element set obtaining Pareto ranks, the sorting is terminated.

2. The method according to claim 1, characterized in that The method of using a pre-trained convolutional neural network to extract the semantic features and position labels of each component on each busbar from the power grid wiring diagram includes: Construct a convolutional neural network by connecting the feature extraction network and the feature fusion network in series; The shape, color, component type, text label, component name, scheduling label, angle and equipment information of the icon in the power grid wiring diagram are used as dimensions of the semantic feature to extract the semantic feature.

3. A device for sorting components in a power grid wiring diagram, used to implement the method for sorting components in a power grid wiring diagram according to claim 1 or 2, comprising: A preprocessing module is configured to extract semantic features and position labels of each element on each bus from the power grid wiring diagram using a pretrained convolutional neural network, and for each bus, group all the elements on the bus into a bus element set; A sorting module is configured to obtain, for each of the elements in each of the busbar element sets, a scheduling label of the element according to the semantic feature of the element, perform a Pareto non-dominated sorting according to the scheduling label and the position label, and obtain a Pareto rank of each of the elements in the busbar element set according to the Pareto non-dominated sorting; A saving module is configured to save the Pareto level of each of the components into a ledger of the power grid wiring diagram.

4. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, characterized in that: When the processor executes the computer program, the method according to claim 1 or 2 is implemented.

5. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the method according to claim 1 or 2.

Images