Random seed generation circuit for a memory system

Abstract

The present application relates to a random seed generation circuit of a memory system. The random seed generation circuit includes a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit generates an initial address based on target page information. The second address generation circuit generates a plurality of table addresses based on the target page information and a plurality of partial addresses divided from the initial address. The table circuit outputs a plurality of table values respectively corresponding to the plurality of table addresses from a plurality of tables. The seed generation circuit generates a random seed based on the plurality of table values.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean application No. 10-2020-0182543, filed on December 23, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure generally relate to a random seed generation circuit, and more particularly, to a random seed generation circuit for a memory system. Background Technology

[0004] The memory system can be configured to store data provided from the host device in response to a write request from the host device. Furthermore, the memory system can be configured to provide the stored data to the host device in response to a read request from the host device. The host device can be an electronic device capable of processing data and may include computers, digital cameras, mobile phones, etc. The memory system becomes operable when connected to the host device. The memory system can be manufactured to be embedded within the host device or removable from the host device.

[0005] When storing data in a specific pattern, memory systems may have a higher risk of errors. Therefore, memory systems can utilize randomization techniques, such as randomizing data using a randomizer, to store randomized data. The performance of the randomizer—the degree to which data can be randomized—can affect the reliability of the memory system. Furthermore, the complexity of the randomizer and memory usage can also influence the performance of the memory system. Summary of the Invention

[0006] According to embodiments of this disclosure, a random seed generation circuit for a memory system may include a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit can be configured to generate an initial address based on target page information. The second address generation circuit can be configured to generate multiple table addresses based on the target page information and multiple partial addresses divided from the initial address. The table circuit can be configured to output multiple table values ​​from the multiple tables, each corresponding to one of the multiple table addresses. The seed generation circuit can be configured to generate a random seed based on the multiple table values.

[0007] According to embodiments of this disclosure, a random seed generation circuit for a memory system may include a first address generation circuit, a second address generation circuit, a table circuit, and a seed generation circuit. The first address generation circuit can be configured to generate multiple partial addresses based on target page information. The second address generation circuit can be configured to select a predetermined first value from a predetermined first value group based on a page hierarchy index, and is configured to convert the multiple partial addresses into multiple table addresses based on the predetermined first value. The table circuit can be configured to output multiple table values ​​from multiple tables, each corresponding to one of the multiple table addresses. The seed generation circuit can be configured to generate a random seed based on the multiple table values.

[0008] According to embodiments of this disclosure, a random seed generation circuit for a memory system may include an address generation circuit, a table circuit, and a seed generation circuit. The address generation circuit can be configured to generate multiple table addresses based on target page information. The table circuit can be configured to output multiple table values ​​from multiple tables, each corresponding to one of the multiple table addresses. The seed generation circuit can be configured to perform an addition operation on the multiple table values ​​and to generate a random seed based on the result of the addition operation.

[0009] According to embodiments of this disclosure, a method for operating a controller may include: generating a plurality of first data bars based on information from a storage unit; generating a plurality of second data bars based on the first data bars and first values, wherein the first values ​​are selected from a set of first values ​​according to the information, and the set of first values ​​corresponds to the first data bars; selecting a plurality of second values ​​from a table based on the values ​​of the second data bars, each table having a second value entry corresponding to a value that the corresponding second data bar may have; generating a random seed based on the selected second values; randomizing the data to be stored in the storage unit using the random seed; and derandomizing the randomized data read from the storage unit using the random seed. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a random seed generation circuit for a memory system according to an embodiment of the present disclosure.

[0011] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the address generation unit shown.

[0012] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the table cell shown is provided.

[0013] Figure 4A and Figure 4B This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the seed generation unit shown.

[0014] Figure 5 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 6 This is a diagram illustrating a data processing system including a solid-state drive (SSD) according to an embodiment of the present disclosure.

[0016] Figure 7 This is a diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure.

[0017] Figure 8 This is a diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure.

[0018] Figure 9 This is a diagram illustrating a network system including a memory system according to an embodiment of the present disclosure.

[0019] Figure 10 This is a block diagram illustrating a non-volatile memory device included in a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0020] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0021] The accompanying drawings are not necessarily drawn to scale, and in some instances, the scale may have been enlarged to clearly show the features of the embodiments. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure.

[0022] As used herein, the term “and / or” includes at least one of the associated listed items. It will be understood that when an element is referred to as “connected to” or “linked to” another element, the element may be directly located on, directly connected to, or linked to the other element, or one or more intermediate elements may be present. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form, and vice versa. It will be further understood that when the terms “comprising,” “including,” “including,” and “comprise” are used in this specification, they specify the presence of the stated element and do not exclude the presence or addition of one or more other elements.

[0023] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0024] According to embodiments of the present disclosure, a random seed generation circuit for a memory system is provided, which has improved performance and a simple structure.

[0025] Figure 1 This is a block diagram illustrating a random seed generation circuit 100 of a memory system according to an embodiment of the present disclosure.

[0026] The random seed generation circuit 100 can be configured to generate a random seed RS to be provided to the randomizer in the memory system. The random seed RS can be used to generate a random pattern, which the randomizer uses to randomize the data.

[0027] The random seed generation circuit 100 can generate a random seed RS based on the target page information TPI. The target page information TPI can indicate the location within the storage medium of the memory system where the randomized data will be stored, i.e., it can indicate the target page. The target page information TPI can include the word line index WI, the page level index PLI, and the erase count EC. Specifically, when the target page is included in a target memory block within the storage medium and is to be accessed via a target word line among multiple word lines connected to the target memory block, the target page information TPI can be described as follows.

[0028] When multiple word lines connected to a target memory block can be identified by indices corresponding to those word lines, the word line index WI can be the index among those indices that corresponds to the target word line. For example, when 16384 word lines are connected to the target memory block and indices “0” to “16383” correspond to 16384 word lines respectively, the word line index WI can have a value between “0” and “16383” to indicate the target word line among the 16384 word lines.

[0029] A Page Rank Index (PLI) can indicate the target page among multiple pages when each of multiple pages can be accessed via a target word line, and the multiple pages can be identified by indices corresponding to each of those pages. For example, when each of four pages (e.g., the Least Significant Bit (LSB), Middle Significant Bit (CSB), Most Significant Bit (MSB), and Upper Significant Bit (USB) pages of a Quad-Level Cell (QLC) NAND flash memory block) can be accessed via a target word line, and indices "0" through "3" correspond to the four pages respectively, the PLI can have a value between "0" and "3" to indicate the target page among the four pages.

[0030] The erase count (EC) indicates the number of times a target page has been erased. When a storage medium performs an erase operation on a block-by-block basis, the erase count (EC) indicates the number of times a target block has been erased.

[0031] The controller of the memory system can be configured to determine the target page of the storage medium containing randomized data to be stored. Therefore, the controller can obtain the target page information (TPI). Consequently, the random seed generation circuit 100 included in the controller can generate a random seed (RS) based on the target page information (TPI).

[0032] According to embodiments of this disclosure, the random seed generation circuit 100 can further generate a random seed RS based on a slice index.

[0033] Specifically, the target page may include multiple slices, and randomized data may be stored in the target slice among the multiple slices. According to embodiments of this disclosure, a slice may be the smallest addressable storage unit within a storage medium. According to embodiments of this disclosure, a slice may have a storage capacity corresponding to the size of data that can be processed at one time by the error correction code (ECC) unit of the controller.

[0034] When multiple slices within a target page can be identified by indices corresponding to those slices, a slice index can indicate the target slice among those slices. For example, when a target page includes four slices corresponding to indices "0" to "3", the slice index can have a value between "0" and "3" to indicate the target slice among the four slices.

[0035] The random seed generation circuit 100 may include an address generation unit 110, a table unit 120, and a seed generation unit 130 (which may also be referred to as an address generation circuit, a table circuit, and a seed generation circuit, respectively).

[0036] Address generation unit 110 can be configured to generate multiple table addresses TAD1 to TADn based on target page information TPI. Specifically, address generation unit 110 can generate an initial address based on target page information TPI, divide the initial address to generate multiple partial addresses, and generate multiple table addresses TAD1 to TADn based on the multiple partial addresses and target page information TPI.

[0037] More specifically, the address generation unit 110 may include a first address generation unit and a second address generation unit. The first address generation unit may be configured to generate an initial address based on the target page information (TPI). The second address generation unit may be configured to select predetermined values ​​from a predetermined value group based on the target page information (TPI). The second address generation unit may be configured to convert multiple partial addresses divided by the initial address into multiple table addresses TAD1 to TADn based on the predetermined values.

[0038] Because the address generation unit 110 references the target page information TPI, the data can be randomized and derandomized using the same random seed RS when storing data to and reading data from the target page.

[0039] Furthermore, since the address generation unit 110 references the erase count EC, different seeds can be generated for the same target page whenever the erase count EC increases, thereby improving randomness.

[0040] Table unit 120 can be configured to output multiple table values ​​TV1 to TVn from multiple tables, each corresponding to a multiple table address TAD1 to TADn.

[0041] Seed generation unit 130 can be configured to generate a random seed RS based on a plurality of table values ​​TV1 to TVn. According to embodiments of this disclosure, seed generation unit 130 can perform addition operations on the plurality of table values ​​TV1 to TVn. Therefore, the randomness of the random seed RS can be improved by combining the plurality of table values ​​TV1 to TVn. Furthermore, because randomness is sufficiently ensured by combining the plurality of table values ​​TV1 to TVn, each of the plurality of tables in table unit 120 can maintain its performance even when configured to have a small size, and thus the memory size occupied by table unit 120 can be significantly reduced.

[0042] The following will describe each element within the random seed generation circuit 100 in detail. As described below, even though the random seed generation circuit 100 has a relatively simple structure, it can still provide a high degree of randomness.

[0043] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the address generation unit 110 shown.

[0044] Reference Figure 2The address generation unit 110 can be configured to generate multiple table addresses, such as the first to fourth table addresses TAD1[3:0] to TAD4[3:0], based on the word line index WI[13:0], the page level index PLI[1:0], and the erase count EC[15:0]. For example, the address generation unit 110 can generate four first to fourth table addresses TAD1[3:0] to TAD4[3:0], each configured with 4 bits, based on the word line index WI[13:0] configured with 14 bits, the page level index PLI[1:0] configured with 2 bits, and the erase count EC[15:0] configured with 16 bits. However, embodiments of this disclosure are not limited to a number of four.

[0045] Address generation unit 110 may include a first address generation unit ADG1 and a second address generation unit ADG2.

[0046] The first address generation unit ADG1 can be configured to generate the initial address IAD[15:0] based on the word line index WI[13:0], the page level index PLI[1:0], and the erase count EC[15:0].

[0047] The second address generation unit ADG2 can be configured to generate the first to fourth table addresses TAD1[3:0] to TAD4[3:0] based on the initial address IAD[15:0] and the page level index PLI[1:0]. As described below, the number of table addresses generated by the second address generation unit ADG2 can correspond to the number of lookup tables included in table unit 120. In the following example, table unit 120 includes four lookup tables, therefore the second address generation unit ADG2 generates four table addresses, namely the first to fourth table addresses TAD1[3:0] to TAD4[3:0].

[0048] The first address generation unit ADG1 may include the XOR operator XOR11. The first address generation unit ADG1 can be configured to combine the word line index WI[13:0] and the page level index PLI[1:0] to generate an index value IV[15:0] configured in 16 bits. For example, the first address generation unit ADG1 can configure 14 bits of the index value IV[15:0] using the word line index WI[13:0] and 2 bits of the index value IV[1:0] using the page level index PLI[1:0]. However, how to shuffle the word line index WI[13:0] and the page level index PLI[1:0] to configure the index value IV[15:0] is not limited to this example. For example, the even-numbered bits of the word line index WI[13:0] and the page level index PLI[1:0] can be changed to the higher 8 bits of the index value IV[15:0], and the odd-numbered bits of the word line index WI[13:0] and the page level index PLI[1:0] can be changed to the lower 8 bits of the index value IV[15:0].

[0049] The XOR operator XOR11 can be configured to perform an XOR operation on the index value IV[15:0] and the erase count EC[15:0], and output the result of the XOR operation as the initial address IAD[15:0].

[0050] The second address generation unit ADG2 may include the first to fourth table address generation units TADG1 to TADG4 (also referred to as table address generation circuits), and the first to fourth table address generation units TADG1 to TADG4 are configured to generate the first to fourth table addresses TAD1[3:0] to TAD4[3:0] in parallel respectively.

[0051] The first to fourth table address generation units TADG1 to TADG4 can respectively receive the first to fourth partial addresses IAD[3:0], IAD[7:4], IAD[11:8], and IAD[15:12] divided from the initial address IAD[15:0]. For example, the initial address IAD[15:0] can be evenly and sequentially divided into the first to fourth partial addresses IAD[3:0], IAD[7:4], IAD[11:8], and IAD[15:12] using 4 bits. However, embodiments of this disclosure are not limited to dividing the initial address IAD[15:0] into partial addresses using 4 bits. For example, the initial address IAD[15:0] may not be divided regularly, but rather randomly. According to embodiments of this disclosure, when the initial address IAD is configured with 'x' bits and there are 'y' table address generation units, the initial address IAD can be divided into 'y' partial addresses using 'x / y' bits. The first address generation unit ADG1 can be described as generating an initial address IAD, and can also be described as generating a portion of the address divided from the initial address IAD.

[0052] Each of the first to fourth table address generation units TADG1 to TADG4 can be configured to generate the corresponding table addresses in the first to fourth table addresses TAD1[3:0] to TAD4[3:0] based on the corresponding partial addresses in the first to fourth partial addresses IAD[3:0], IAD[7:4], IAD[11:8], and IAD[15:12] of the page hierarchy index PLI[1:0] and the initial address IAD[15:0]. The first to fourth table address generation units TADG1 to TADG4 can be configured and operated in a similar manner to each other. Therefore, the configuration and operation of the first table address generation unit TADG1 will be described below as an example.

[0053] The first table address generation unit TADG1 may include a selection unit MUX1 and an XOR operator XOR21.

[0054] The selection unit MUX1 (also known as the selection circuit) can be configured to output a predetermined value MO1 from a first predetermined value group PV1 that includes predetermined values ​​(e.g., 0x0, 0x4, 0x8, and 0xC) in response to the page level index PLI[1:0].

[0055] The first predetermined value group PV1 may include predetermined values, the number of which corresponds to the number of cases that can be represented by the page hierarchy index PLI[1:0] (e.g., 4 cases). According to an embodiment of the present invention, when the number of cases that can be represented by the page hierarchy index PLI is "a", the first predetermined value group PV1 may include "a" predetermined values.

[0056] The first predetermined value group PV1 can be stored in a register. The predetermined values ​​within the first predetermined value group PV1 can be determined regardless of the target page information TPI. The predetermined values ​​within the first predetermined value group PV1 may be immutable, i.e., fixed. However, according to embodiments of this disclosure, the controller of the memory system can change the predetermined values ​​within the first predetermined value group PV1.

[0057] The number of bits configured for each predetermined value within the first predetermined value group PV1 can be the number of bits configured for the first portion of the address IAD[3:0] (e.g., 4 bits). Figure 2 As shown, the predetermined values ​​within the first predetermined value group PV1 can be different from each other. Figure 2 As shown, according to an embodiment of the present disclosure, the predetermined values ​​in the first to fourth predetermined value groups PV1 to PV4 may be different from each other, wherein the first to fourth predetermined value groups PV1 to PV4 are respectively used by the first to fourth table address generation units TADG1 to TADG4.

[0058] According to embodiments of this disclosure, the selection unit MUX1 can be configured not to respond to the page hierarchy index PLI[1:0], but to respond to the selection unit MUX1 by means of the selection unit MUX1. Figure 1 The bit selected by performing a calculation on one or more of the word line index WI[13:0], page level index PLI[1:0], and erase count EC[15:0] included in the target page information TPI shown is used to output the predetermined value MO1 in the predetermined value in the first predetermined value group PV1.

[0059] The XOR operator XOR21 ​​can be configured to perform an XOR operation on a first partial address IAD[3:0] and a predetermined value MO1 to generate the result of the XOR operation as a first table address TAD1[3:0], wherein the predetermined value MO1 is selected from predetermined values ​​in a first predetermined value group PV1 in response to a page level index PLI[1:0]. The first partial address IAD[3:0] can be provided from the first address generation unit ADG1. The predetermined value MO1 can be output from the selection unit MUX1. The number of bits configuring the first table address TAD1[3:0] can be the same as the number of bits configuring the first partial address IAD[3:0].

[0060] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of table unit 120 shown.

[0061] Reference Figure 3 Table unit 120 can be configured to output the first to fourth table values ​​TV1[31:0] to TV4[31:0] based on the first to fourth table addresses TAD1[3:0] to TAD4[3:0].

[0062] Table unit 120 may include lookup tables T1 to T4. For example, each of lookup tables T1 to T4 may include 16 entries, each corresponding to one of 16 values ​​that a 4-bit corresponding table address (e.g., TAD1[3:0]) may have. Each of the 16 entries may have a value configured in 32 bits. However, the number of entries included in each of lookup tables T1 to T4 and the size of each entry are not limited to this example in the various embodiments of this disclosure.

[0063] According to embodiments of this disclosure, lookup tables T1 to T4 can be located in different memory devices. According to embodiments of this disclosure, lookup tables T1 to T4 can be located in the same memory device.

[0064] Table unit 120 can output entries corresponding to the first to fourth table addresses TAD1[3:0] to TAD4[3:0] from lookup tables T1 to T4 as the first to fourth table values ​​TV1[31:0] to TV4[31:0]. For example, table unit 120 can output entries corresponding to the first table address TAD1[3:0] from lookup table T1 as the first table value TV1[31:0].

[0065] Figure 4A and Figure 4B This illustrates an embodiment according to the present disclosure. Figure 1 A detailed diagram of the seed generation unit 130 shown.

[0066] Reference Figure 4A The seed generation unit 130A can be Figure 1 An embodiment of the seed generation unit 130 is shown. The seed generation unit 130A can be configured to generate a random seed RS[31:0] based on the first to fourth table values ​​TV1[31:0] to TV4[31:0]. The random seed RS[31:0] configured in 32-bit mode is merely an example, and embodiments of this disclosure are not limited to this example.

[0067] The seed generation unit 130A may include an adder 131 (also referred to as an adder circuit).

[0068] Adder 131 can be configured to perform addition operations on the first to fourth table values ​​TV1[31:0] to TV4[31:0] to generate a random seed RS[31:0] based on the result of the addition operation. For example, adder 131 can perform addition operations on each of the first to fourth table values ​​TV1[31:0] to TV4[31:0] configured in 32-bit order to generate a result of the addition operation configured in 34-bit order. Adder 131 can output bits at predetermined positions within the 34-bit result (e.g., the lower 32 bits) as the random seed RS[31:0]. However, embodiments of this disclosure are not limited to selecting the lower 32 bits from the 34-bit result of adder 131 as the random seed RS[31:0]. For example, adder 131 can output the higher 32 bits within the 34-bit result as the random seed RS[31:0].

[0069] Reference Figure 4B Seed generation unit 130B can be Figure 1 An embodiment of the seed generation unit 130 is shown. The seed generation unit 130B can be configured to generate a random seed RS[31:0] based on the first to fourth table values ​​TV1[31:0] to TV4[31:0] and the slice index SI[1:0].

[0070] Specifically, the seed generation unit 130B may include an adder 131 and a seed conversion unit 132 (also referred to as a seed conversion circuit).

[0071] Adder 131 can be configured to perform addition operations on the first to fourth table values ​​TV1[31:0] to TV4[31:0] to generate an initial random seed IRS[31:0] based on the result of the addition operation. The configuration and operation of adder 131 can be related to... Figure 4A The adder 131 shown is the same.

[0072] Seed conversion unit 132 can be configured to output random seed RS[31:0] based on slice index SI[1:0] and initial random seed IRS[31:0] provided from adder 131.

[0073] Specifically, the seed conversion unit 132 may include a selection unit MUX and an XOR operator XOR31.

[0074] The selection unit MUX can be configured to output a predetermined value MO from the predetermined value group PV in response to the slice index SI[1:0].

[0075] The number of predetermined values ​​in the predetermined value group PV can correspond to the number of cases that can be represented by the slice index SI[1:0] (e.g., 4 cases). According to an embodiment of the invention, when the number of cases that can be represented by the slice index SI is “b”, the predetermined value group PV can include “b” predetermined values.

[0076] A predetermined value set PV can be stored in a register. The predetermined values ​​within the predetermined value set PV may be immutable, i.e., fixed. However, according to embodiments of this disclosure, the controller of the memory system can change the predetermined values ​​within the predetermined value set PV.

[0077] The number of bits for each predetermined value within the configuration predetermined value group PV can be the number of bits for configuring the initial random seed IRS[31:0] (e.g., 32 bits). Figure 4B As shown, the predetermined values ​​within the predetermined value group PV can be different from each other.

[0078] The XOR operator XOR31 can be configured to perform an XOR operation on a predetermined value MO selected by the selection unit MUX from the predetermined value group PV and an initial random seed IRS[31:0] to generate the result of the XOR operation as a random seed RS[31:0]. The predetermined value MO can be output from the selection unit MUX. Because each of the predetermined value MO and the initial random seed IRS[31:0] is configured in 32-bit mode, the random seed RS[31:0] can also be configured in 32-bit mode.

[0079] Figure 5 This is a block diagram illustrating a memory system 200 according to an embodiment of the present disclosure.

[0080] Reference Figure 5 The memory system 200 can be configured to store data provided by an external host device in the memory system 200 in response to a write request from the external host device. The memory system 200 can also be configured to provide data stored in the memory system 200 to the host device in response to a read request from the external host device.

[0081] The memory system 200 may include PCMCIA cards, compact flash (CF) cards, smart media cards, memory sticks, various multimedia cards (e.g., MMC, eMMC, RS-MMC, and micro MMC), secure digital (SD) cards (e.g., SD, mini SD, and micro SD), universal flash (UFS), or solid-state drives (SSD).

[0082] The memory system 200 may include a controller 210 and a storage medium 220.

[0083] The controller 210 can control all operations of the memory system 200. The controller 210 can control the storage medium 220 to perform foreground operations in response to instructions from an external host device. Foreground operations may include writing data to the storage medium 220 and reading data from the storage medium 220 in response to instructions from the host device (i.e., write requests and read requests).

[0084] Furthermore, the controller 210 can control the storage medium 220 independently of an external host device to perform necessary internal background operations. Background operations may include at least one of the following: wear leveling, garbage collection, erasure, read / reclaim, and refresh operations for the storage medium 220. Similar to foreground operations, background operations may include writing data to and reading data from the storage medium 220.

[0085] The controller 210 may include a random seed generation unit 211, a randomizer 212, and a derandomizer 213.

[0086] The random seed generation unit 211 can be used with Figure 1 The random seed generation unit 100 shown is configured and operated in the same manner.

[0087] Randomizer 212 can be configured to randomize data DT based on random seed RS generated by random seed generation unit 211. Controller 210 can store the randomized data RDT into target page TP, which is associated with target page information TPI and included in storage medium 220.

[0088] The derandomizer 213 can be configured to derandomize data (i.e., randomized data RDT) read from the target page TP of the storage medium 220 based on the random seed RS generated by the random seed generation unit 211. Because the random seed generation unit 211 provides the random seed RS to the derandomizer 213, and the randomizer 212 randomizes the data DT based on the random seed RS, the derandomizer 213 can recover the original data DT from the randomized data RDT using the random seed RS.

[0089] Under the control of the controller 210, the storage medium 220 can store the randomized data RDT provided by the controller 210 into the target page TP, and can read the randomized data RDT from the target page TP to provide the read data to the controller 210.

[0090] Storage medium 220 may include a plurality of non-volatile memory devices. Each of the non-volatile memory devices may include flash memory devices (e.g., NAND flash or NOR flash), ferroelectric random access memory (FeRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), etc.

[0091] Figure 6 This is a diagram illustrating a data processing system 1000 including a solid-state drive (SSD) 1200 according to an embodiment of the present disclosure. (Refer to...) Figure 6 The data processing system 1000 may include a host device 1100 and an SSD 1200.

[0092] SSD 1200 may include controller 1210, buffer memory device 1220, multiple non-volatile memory devices 1231 to 123n, power supply 1240, signal connector 1250 and power connector 1260.

[0093] The controller 1210 can control the general operation of the SSD 1200. The controller 1210 may include a host interface unit 1211, a control unit 1212, a random access memory 1213, a randomization unit 1214, an error correction code (ECC) unit 1215, and a memory interface unit 1216.

[0094] The host interface unit 1211 can exchange signals SGL with the host device 1100 via signal connector 1250. Signal SGL may include commands, addresses, data, etc. According to the protocol of the host device 1100, the host interface unit 1211 can interface with the host device 1100 and the SSD 1200. For example, the host interface unit 1211 can communicate with the host device 1100 via any of the following standard communication interfaces or protocols: Secure Digital, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial SCSI (SAS), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), and Universal Flash Memory (UFS).

[0095] Control unit 1212 can analyze and process the signal SGL received from host device 1100. Based on the firmware or software used to drive SSD 1200, control unit 1212 can control the operation of internal functional blocks. Random access memory 1213 can be used as working memory for driving such firmware or software.

[0096] Randomization unit 1214 can randomize data to be stored in non-volatile memory devices 1231 to 123n. Randomization unit 1214 can derandomize data read from non-volatile memory devices 1231 to 123n and corrected by ECC unit 1215. Randomization unit 1214 may include random seed generation unit 211, randomizer 212, and derandomizer 213.

[0097] ECC unit 1215 can generate parity data for the data randomized by randomization unit 1214. The generated parity data can be stored together with the randomized data in non-volatile memory devices 1231 to 123n. ECC unit 1215 can detect errors in data read from at least one of the non-volatile memory devices 1231 to 123n based on the parity data. If the detected error is within a correctable range, ECC unit 1215 can correct the detected error.

[0098] Under the control of the control unit 1212, the memory interface unit 1216 can provide control signals, such as commands and addresses, to at least one of the non-volatile memory devices 1231 to 123n. Furthermore, under the control of the control unit 1212, the memory interface unit 1216 can exchange data with at least one of the non-volatile memory devices 1231 to 123n. For example, the memory interface unit 1216 can provide data stored in the buffer memory device 1220 to at least one of the non-volatile memory devices 1231 to 123n, or provide data read from at least one of the non-volatile memory devices 1231 to 123n to the buffer memory device 1220.

[0099] The buffer memory device 1220 can temporarily store data to be stored in at least one of the non-volatile memory devices 1231 to 123n. Further, the buffer memory device 1220 can temporarily store data read from at least one of the non-volatile memory devices 1231 to 123n. Under the control of the controller 1210, the data temporarily stored in the buffer memory device 1220 can be transferred to the host device 1100 or at least one of the non-volatile memory devices 1231 to 123n.

[0100] Non-volatile memory devices 1231 to 123n can be used as storage media for the SSD 1200. Non-volatile memory devices 1231 to 123n can be connected to the controller 1210 via multiple channels CH1 to CHn, respectively. One or more non-volatile memory devices can be connected to a single channel. Non-volatile memory devices connected to each channel can be connected to the same signal bus and data bus.

[0101] Power supply 1240 can provide power PWR input through power connector 1260 to the internals of SSD 1200. Power supply 1240 may include auxiliary power supply 1241. Auxiliary power supply 1241 can supply power to allow SSD 1200 to terminate normally in the event of a sudden power outage. Auxiliary power supply 1241 may include a large-capacity capacitor.

[0102] Depending on the interface scheme between the host device 1100 and the SSD 1200, the signal connector 1250 can be configured with various types of connectors.

[0103] Depending on the power supply scheme of the host device 1100, the power connector 1260 can be configured with various types of connectors.

[0104] Figure 7 This is a diagram illustrating a data processing system 2000 including a memory system 2200 according to an embodiment of the present disclosure. (Refer to...) Figure 7 The data processing system 2000 may include a host device 2100 and a memory system 2200.

[0105] The host device 2100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 2100 may include internal function blocks for performing the functions of the host device.

[0106] The host device 2100 may include connection terminals 2110 such as sockets, slots, or connectors. The memory system 2200 may be mounted to the connection terminals 2110.

[0107] The memory system 2200 can be configured in the form of a board, such as a printed circuit board. The memory system 2200 can be referred to as a memory module or a memory card. The memory system 2200 may include a controller 2210, a buffer memory device 2220, non-volatile memory devices 2231 and 2232, a power management integrated circuit (PMIC) 2240, and a connection terminal 2250.

[0108] The controller 2210 can control the general operation of the memory system 2200. The controller 2210 can be connected to... Figure 6 The controller 1210 shown is configured in the same way.

[0109] Buffer memory device 2220 can temporarily store data to be stored in non-volatile memory devices 2231 and 2232. Furthermore, buffer memory device 2220 can temporarily store data read from non-volatile memory devices 2231 and 2232. Under the control of controller 2210, data temporarily stored in buffer memory device 2220 can be transferred to host device 2100 or non-volatile memory devices 2231 and 2232.

[0110] Non-volatile memory devices 2231 and 2232 can be used as storage media in memory system 2200.

[0111] PMIC 2240 can supply power to the memory system 2200 via connection terminal 2250. PMIC 2240 can manage the power of the memory system 2200 under the control of controller 2210.

[0112] Connection terminal 2250 can be connected to connection terminal 2110 of host device 2100. Through connection terminal 2250, signals such as commands, addresses, and data, as well as power, can be transmitted between host device 2100 and memory system 2200. Depending on the interface scheme between host device 2100 and memory system 2200, connection terminal 2250 can be configured in various ways. Connection terminal 2250 can be located on either side of memory system 2200.

[0113] Figure 8 This is a diagram illustrating a data processing system 3000 including a memory system 3200 according to an embodiment of the present disclosure. (Refer to...) Figure 8 The data processing system 3000 may include a host device 3100 and a memory system 3200.

[0114] The host device 3100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0115] The memory system 3200 can be configured in a surface-mount package. The memory system 3200 can be mounted to the host device 3100 via solder balls 3250. The memory system 3200 may include a controller 3210, a buffer memory device 3220, and a non-volatile memory device 3230.

[0116] The controller 3210 can control the general operation of the memory system 3200. The controller 3210 can be connected to... Figure 6 The controller 1210 shown is configured in the same way.

[0117] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memory device 3230. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memory device 3230. Under the control of the controller 3210, the data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memory device 3230.

[0118] The non-volatile memory device 3230 can be used as the storage medium of the memory system 3200.

[0119] Figure 9 This is a diagram illustrating a network system 4000 including a memory system 4200 according to an embodiment of the present disclosure. (Refer to...) Figure 9 The network system 4000 may include a server system 4300 and multiple client systems 4410 to 4430 connected via a network 4500.

[0120] Server system 4300 can serve data in response to requests from multiple client systems 4410 to 4430. For example, server system 4300 can store data provided by multiple client systems 4410 to 4430. As another example, server system 4300 can provide data to multiple client systems 4410 to 4430.

[0121] Server system 4300 may include host device 4100 and memory system 4200. Memory system 4200 may be composed of… Figure 5 The memory system 200 shown Figure 6 The SSD 1200 shown Figure 7 The memory system 2200 shown or Figure 8 The memory system 3200 shown is configured as shown.

[0122] Figure 10 This is a block diagram illustrating a non-volatile memory device 300 included in a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 10 The non-volatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

[0123] The memory cell array 310 may include memory cells MC arranged in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect.

[0124] The row decoder 320 can be connected to the memory cell array 310 via word lines WL1 to WLm. The row decoder 320 can operate under the control of control logic 360. The row decoder 320 can decode addresses provided from external devices (not shown). The row decoder 320 can select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 can provide word line voltages from voltage generator 350 to word lines WL1 to WLm.

[0125] The data read / write block 330 can be connected to the memory cell array 310 via bit lines BL1 to BLn. The data read / write block 330 may include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read / write block 330 can be operated according to the control of the control logic 360. Depending on the operating mode, the data read / write block 330 can operate as a write driver or a sense amplifier. For example, in a write operation, the data read / write block 330 can operate as a write driver to store data provided from an external device into the memory cell array 310. As another example, in a read operation, the data read / write block 330 can operate as a sense amplifier to read data from the memory cell array 310.

[0126] The column decoder 340 can operate under the control of the control logic 360. The column decoder 340 can decode addresses provided from external devices. Based on the decoding result, the column decoder 340 can connect the read / write circuits RW1 to RWn of the data read / write block 330, which correspond to the bit lines BL1 to BLn respectively, to the data input / output lines or data input / output buffers.

[0127] Voltage generator 350 can generate voltages to be used in the internal operation of non-volatile memory device 300. The voltage generated by voltage generator 350 can be applied to the memory cells of memory cell array 310. For example, a programming voltage generated during a programming operation can be applied to the word line of the memory cell to which the programming operation is to be performed. In another example, an erase voltage generated during an erase operation can be applied to the well area of ​​the memory cell to which the erase operation is to be performed. In yet another example, a read voltage generated during a read operation can be applied to the word line of the memory cell to which the read operation is to be performed.

[0128] Control logic 360 can control the general operation of non-volatile memory device 300 based on control signals provided from an external device. For example, control logic 360 can control the operation of non-volatile memory device 300, such as read operations, write operations and erase operations of non-volatile memory device 300.

[0129] According to embodiments of the present disclosure, a random seed generation circuit for a memory system is provided, which has improved performance and a simple structure.

[0130] While specific embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Embodiments can be combined to form other embodiments. Therefore, the random seed generation circuitry for the memory system should not be limited to the described embodiments. Rather, when taken in conjunction with the foregoing description and drawings, the random seed generation circuitry for the memory system described herein should be limited only by the appended claims.

Claims

1. A random seed generation circuit for a memory system, the random seed generation circuit comprising: The first address generation circuit generates an initial address based on the target page information of the target page. The second address generation circuit generates multiple table addresses based on the target page information and multiple partial addresses divided from the initial address; The table circuit outputs multiple table values ​​corresponding to the addresses of the multiple tables from multiple tables; as well as A seed generation circuit generates a random seed corresponding to the target page based on the multiple table values.

2. The random seed generation circuit according to claim 1, wherein the target page information includes a word line index, a page level index, and an erase count corresponding to the target page.

3. The random seed generation circuit according to claim 2, wherein the first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate the initial address.

4. The random seed generation circuit according to claim 1, The second address generation circuit includes multiple table address generation circuits, and Each of the plurality of table address generation circuits generates a corresponding table address among the plurality of table addresses based on the target page information and a corresponding partial address among the plurality of partial addresses.

5. The random seed generation circuit according to claim 4, wherein each of the plurality of table address generation circuits comprises: The selection circuit, in response to the target page information, outputs a predetermined value from a plurality of predetermined values; as well as The XOR operator performs an XOR operation on the predetermined value and the corresponding partial address to generate the corresponding table address.

6. The random seed generation circuit according to claim 5, wherein the plurality of predetermined values ​​are different from each other.

7. The random seed generation circuit according to claim 1, wherein the seed generation circuit performs an addition operation on the plurality of table values, and selects a plurality of bits at a plurality of predetermined positions within the result of the addition operation as the random seed.

8. The random seed generation circuit according to claim 1, wherein the seed generation circuit comprises: An adder circuit performs an addition operation on the plurality of table values ​​and selects a plurality of bits at a plurality of predetermined positions within the result of the addition operation as an initial random seed; as well as The seed conversion circuit generates the random seed based on the initial random seed and the slice index.

9. The random seed generation circuit according to claim 8, wherein the seed conversion circuit comprises: The selection circuit, in response to the slice index, outputs a predetermined value from a plurality of predetermined values; as well as The XOR operator performs an XOR operation on the predetermined value and the initial random seed to generate the random seed.

10. A random seed generation circuit for a memory system, the random seed generation circuit comprising: The first address generation circuit generates multiple partial addresses based on the target page information of the target page; The second address generation circuit selects multiple predetermined first values ​​from multiple predetermined first value groups based on the page level index, and converts the multiple partial addresses into multiple table addresses based on the multiple predetermined first values. The table circuit outputs multiple table values ​​corresponding to the addresses of the multiple tables from multiple tables; as well as A seed generation circuit generates a random seed corresponding to the target page based on the multiple table values.

11. The random seed generation circuit according to claim 10, The target page information includes the word line index corresponding to the target page, the page hierarchy index, and the erase count. The first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate an initial address, which will be divided into the multiple partial addresses.

12. The random seed generation circuit according to claim 10, The second address generation circuit includes multiple table address generation circuits, each of which receives the multiple partial addresses and outputs the multiple table addresses. Each of the plurality of table address generation circuits includes: The selection circuit receives a corresponding predetermined first value group from the plurality of predetermined first value groups, and outputs a predetermined first value from the corresponding predetermined first value group in response to the page level index. as well as The XOR operator performs an XOR operation on the predetermined first value and the corresponding partial address to generate the corresponding table address.

13. The random seed generation circuit according to claim 10, wherein the seed generation circuit comprises: An adder circuit performs an addition operation on the plurality of table values ​​and selects a plurality of bits at a plurality of predetermined positions within the result of the addition operation as an initial random seed; as well as The seed conversion circuit generates the random seed based on the initial random seed and the slice index.

14. The random seed generation circuit according to claim 13, wherein the seed conversion circuit comprises: The selection circuit, in response to the slice index, outputs a predetermined second value from a plurality of predetermined second values; as well as The XOR operator performs an XOR operation on the predetermined second value and the initial random seed to generate the random seed.

15. A random seed generation circuit for a memory system, the random seed generation circuit comprising: The address generation circuit generates multiple table addresses based on the target page information of the target page. The table circuit outputs multiple table values ​​corresponding to the addresses of the multiple tables from multiple tables; as well as The seed generation circuit performs an addition operation on the plurality of table values ​​and generates a random seed corresponding to the target page based on the result of the addition operation.

16. The random seed generation circuit according to claim 15, wherein the address generation circuit comprises: The first address generation circuit generates an initial address based on the target page information; as well as The second address generation circuit generates the multiple table addresses based on the target page information and multiple partial addresses divided from the initial address.

17. The random seed generation circuit according to claim 16, The target page information includes the word line index, page hierarchy index, and erase count corresponding to the target page, and The first address generation circuit combines the word line index and the page level index to generate an index value, and performs an XOR operation on the index value and the erase count to generate the initial address.

18. The random seed generation circuit according to claim 16, The second address generation circuit includes multiple table address generation circuits, and Each of the plurality of table address generation circuits generates a corresponding table address among the plurality of table addresses based on the target page information and a corresponding partial address among the plurality of partial addresses.

19. The random seed generation circuit of claim 18, wherein each of the plurality of table address generation circuits comprises: The selection circuit, in response to the target page information, outputs a predetermined value from a plurality of predetermined values; as well as The XOR operator performs an XOR operation on the predetermined value and the corresponding partial address to generate the corresponding table address.

20. The random seed generation circuit according to claim 15, wherein the seed generation circuit comprises: An adder circuit performs the addition operation and selects multiple bits at multiple predetermined positions within the result of the addition operation as an initial random seed; as well as The seed conversion circuit generates the random seed based on the initial random seed and the slice index.

21. The random seed generation circuit according to claim 20, wherein the seed conversion circuit comprises: The selection circuit, in response to the slice index, outputs a predetermined value from a plurality of predetermined values; as well as The XOR operator performs an XOR operation on the predetermined value and the initial random seed to generate the random seed.

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