Protection Circuit for Preventing Accidental Erasure of Flash Memory

Abstract

The present invention provides a protection circuit for preventing accidental erasure of a Flash memory, including an enable signal gate for receiving an enable signal, a high-voltage enable signal, and a high-voltage configuration signal, and generating an internal enable signal and an internal high-voltage configuration signal; a status controller for receiving the internal enable signal and then generating first and second status signals; a status verifier for receiving the internal enable signal and the first and second status signals, and determining whether the levels of the first and second signals are consistent, and if consistent, issuing a high-voltage status signal; a control signal decoder for receiving the enable signal, the second status signal, and the high-voltage status signal. After the control decoder receives the high-voltage status signal, it sends a high-voltage control signal enabling the status to the internal module of the Flash memory. The enable signal gate of the present invention reduces the degree of interference when the chip is not reset or is interfered, and avoids accidental erasure operations inside the Flash.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a protection circuit for preventing accidental erasure of Flash memory. Background Art

[0002] With the development of the integrated circuit industry, various types of system-on-chip (SOC) chips based on embedded systems have been applied in various fields, such as industrial control, video and other fields, mainly relying on the design of embedded software to ensure that the chip completes specific functions such as control, monitoring, and identification. In the application of products of the MCU (microcontroller unit) and SOC types, it is necessary to save pre-written software code during the application process. In the context of an increasingly complex industry background, non-volatile memories, especially Flash (flash memory), are commonly used in these architectures, and their characteristic is that new software code can be rewritten, and new functions can be provided through software updates. The correctness of the data stored in the non-volatile memory determines whether the product is usable and is very important for the product life cycle.

[0003] With the popularization of the application scope of such chips, especially in the scenario of extremely low power supply voltage, the working environment of such chips is very harsh, and they are easily affected by power / ground fluctuations, resulting in internal logic anomalies. In fields such as small household appliances and motor control, factors such as power fluctuations are particularly obvious. Usually, the embedded flash control system is independent of software control. After being interfered, it is easily triggered to malfunction. Especially after accidental erasure and other actions occur, it will cause partial data anomalies or loss, which will directly affect the product function. Since such malfunctions usually occur in the actual application environment and often affect partial data, they are hidden and do not directly show anomalies, forming potential safety hazards in product operation and even possibly causing irreparable losses.

[0004] In current embedded flash memories, the prohibition of abnormal data operations is generally achieved by adding a logic lock in the controller. In existing research, 1) A data protection technology for preventing accidental erasure proposed in Patent 200810227986 writes a string of specific command words before the FLASH erasure operation. Only when all the command words are correct, the erasure command is started, which can prevent accidental erasure from occurring. 2) Patent 201710168401 proposes using two control signals to perform a logical "AND" operation with the Flash control signal to achieve the protection of the logical signal of Flash by the peripheral control signal.

[0005] In the prior art, when the chip is in a normal logic state, existing inventions can reduce or avoid the possibility of accidental Flash operation at the application level. However, when the chip is in a strong interference condition or the state before power-on reset, the abnormal situation of the internal logic register's accidental operation on Flash cannot be solved by existing inventions.

[0006] Therefore, a protection circuit is required for the control circuit of an embedded flash memory, which can avoid the internal Flash memory from being misoperated under abnormal conditions and protect the data security and reliability under interference conditions. SUMMARY OF THE INVENTION

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a protection circuit for preventing mis-erasing of Flash memory, which is used to solve the problem of misoperation of Flash caused by abnormal conditions of internal logic registers when the chip is under strong interference conditions or before power-on reset in the prior art.

[0008] To achieve the above object and other related objects, the present invention provides a protection circuit for preventing mis-erasing of Flash memory, including:

[0009] An enable signal gate for receiving an enable signal, a high-voltage enable signal, and a high-voltage configuration signal, and generating an internal enable signal and an internal high-voltage configuration signal;

[0010] A state controller for receiving the internal enable signal and then generating first and second state signals,

[0011] A state validator for receiving the internal enable signal and the first and second state signals, and judging whether the levels of the first and second signals are consistent. If they are consistent, a high-voltage state signal is sent out;

[0012] A control signal decoder for receiving the enable signal, the second state signal, and the high-voltage state signal. After receiving the high-voltage state signal, the control decoder sends a high-voltage control signal of the enable state to the internal module of the Flash memory.

[0013] Preferably, the enable signal gate uses a first AND gate to integrate the enable signal and the high-voltage enable signal to generate the internal enable signal.

[0014] Preferably, the output terminal of the first AND gate is electrically connected to the input terminals of a first D flip-flop and an inverter respectively. The output terminal of the inverter is electrically connected to the input terminal of a second D flip-flop. The positive output terminal of the first D flip-flop and the negative output terminal of the second D flip-flop are electrically connected to the input terminals of a second AND gate respectively. The output terminal of the second AND gate is used to provide the high-voltage enable signal.

[0015] Preferably, the set values of the first and second D flip-flops are 0 and 1 respectively, corresponding to the enable-off state of the high-voltage enable signal.

[0016] Preferably, the high-voltage enable signal and the high-voltage enable signal output the internal high-voltage configuration signal through a third AND gate.

[0017] Preferably, the state controller includes first and second state control modules and first and second counters. The first state control module and the second state control module are used to switch to the high-voltage state according to the high-voltage state signal and respectively generate the first and second state signals. The first and second counters are respectively started to count according to the start signals provided by the first and second state control modules, and respectively feedback the start count to the first and second state control modules.

[0018] Preferably, both the first and second signals define the all-0 value as the starting state, and the starting state is that the internal high-voltage configuration signal is in the off state.

[0019] Preferably, the control signal decoder is used to convert the second state signal into a conversion signal applicable to the internal module.

[0020] Preferably, the control signal decoder includes a fourth AND gate and a flash signal decoding module. The second state signal and the high-voltage state signal are output through the fourth AND gate to obtain the conversion signal, and the flash signal decoding module is used to convert the conversion signal into the high-voltage control signal.

[0021] Preferably, if the first and second state signals are the same, the output high-voltage state signal is at a high level; if they are different, the output high-voltage state signal is at a low level.

[0022] Preferably, if the high-voltage enable signal is at a low level, the high-voltage enable signal is at a low level.

[0023] Preferably, if the high-voltage enable signal is at a low level, the control signal decoder does not generate the high-voltage control signal.

[0024] As described above, the protection circuit for preventing mis-erasing of the Flash memory according to the present invention has the following beneficial effects:

[0025] The enabling signal gate (HV_EN_Gating) of the present invention is used for primary protection of the memory. Its structure contains two D flip-flop structures with the same structure. Under normal circumstances, the values stored inside these two D flip-flops are ensured to be different through control logic. However, when the chip is not reset or is interfered with, these two D flip-flops are in adjacent positions, and the degree of interference they receive is relatively close. After being interfered with, the values stored in them are more likely to be the same. If such a situation occurs, for the corresponding high-voltage enabling signal, the internal high-voltage control signal is kept in a non-enabled state; on the basis of primary protection, the present invention uses a combination of a state controller and a state verifier for secondary protection of the memory. Inside the state controller, there are two sets of state control circuits with the same structure, namely, a combination of a state control module and a counter, which are used to control state monitoring. The two sets of state control circuits operate independently and generate a first state signal and a second state signal. Under normal conditions, the state signals, the first state signal and the second state signal, should be in the same state. When the state signals are different, it indicates that an abnormality has occurred in the internal register, and the state verifier immediately closes the Flash signal control signal to avoid accidental erasure operations inside the Flash. Brief Description of the Drawings

[0026] Figure 1 It shows a schematic diagram of the protection circuit of the present invention;

[0027] Figure 2 It shows a schematic diagram of the structure of the enabling signal gate module of the present invention;

[0028] Figure 3 It shows a schematic diagram of the structure of the state controller of the present invention;

[0029] Figure 4 It shows a schematic diagram of the structure of the control signal decoder of the present invention. Detailed Embodiment

[0030] The following uses specific specific examples to illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please refer to Figure 1 , the present invention provides a protection circuit for preventing accidental erasure of a Flash memory, including:

[0032] Enable signal gate 10 (HV_EN_Gating) is used to receive an enable signal (ME), a high-voltage enable signal (HVEN), and a high-voltage configuration signal (HV_CFG), and generate an internal enable signal and an internal high-voltage configuration signal (HV_CFG_I);

[0033] In an alternative embodiment, the enable signal gate 10 integrates the enable signal and the high-voltage enable signal using a first AND gate 101 to generate an internal enable signal.

[0034] In an alternative embodiment, refer to Figure 2 , the output terminal of the first AND gate 101 is electrically connected to the input terminals of a first D flip-flop 104 (DFF1) and an inverter 106 respectively. The output terminal of the inverter 106 is electrically connected to the input terminal of a second D flip-flop 105 (DFF2). The positive output terminal of the first D flip-flop 104 and the negative output terminal of the second D flip-flop 105 are electrically connected to the input terminals of a second AND gate 102 respectively. The output terminal of the second AND gate 102 is used to provide the high-voltage enable signal. The enable signal gate 10 is used for the first-level protection of the memory. Its structure has two D flip-flop structures with the same structure. Under normal circumstances, the values stored inside these two D flip-flops are ensured to be different through control logic. However, when the chip is not reset or is interfered with, these two D flip-flops are in adjacent positions, and the degree of interference they receive is relatively close. After being interfered with, the values stored in them are more likely to be the same. If such a situation occurs, for the corresponding high-voltage enable signal, the internal high-voltage control signal is kept in a non-enabled state.

[0035] In an alternative embodiment, the values set after setting the first and second D flip-flops are 0 and 1 respectively, corresponding to the enabled and disabled states of the high-voltage enable signal.

[0036] In an alternative embodiment, the high-voltage enable signal and the high-voltage enable signal perform an AND operation on each bit through a third AND gate 103 respectively, and then output the internal high-voltage configuration signal.

[0037] The state controller 20 is used to receive the internal enable signal and then generate first and second state signals.

[0038] In an alternative embodiment, refer to Figure 3, the status controller 20 includes first and second status control modules (Stage_Ctrl_1, Stage_Ctrl_2) and first and second counters 203, 204 (CNT1, CNT2). The first status control module 201 and the second status control module 202 are used to switch to the high-voltage state according to the high-voltage status signal and respectively generate first and second status signals (HV_STAGE_A and HV_STAGE_B). The first and second counters 203, 204 are respectively started to count according to the start signals provided by the first and second status control modules, and respectively feedback the start count to the first and second status control modules. The first and second status control modules are relatively easy to implement for those skilled in the art. The first and second counters 203, 204 are relatively common counter modules and can be relatively easily implemented by those skilled in the art.

[0039] In an alternative embodiment, both the first and second signals define the all-0 value as the starting state, and the starting state is that the internal high-voltage configuration signal is in the off state.

[0040] In an alternative embodiment, the control signal decoder 40 is used to convert the second status signal into a conversion signal applicable to the internal module.

[0041] In an alternative embodiment, please refer to Figure 4 , the control signal decoder 40 includes a fourth AND gate 401 and a flash signal decoding module 402. After the second status signal and the high-voltage status signal perform an AND operation on each bit through the fourth AND gate 401 respectively, a conversion signal is output. The flash signal decoding module 402 is used to convert the conversion signal into a high-voltage control signal, and the flash signal decoding module 402 is a module existing in the prior art.

[0042] The status validator 30 is used to receive the internal enable signal and the first and second status signals, and determine whether the levels of the first and second signals are consistent. If they are consistent, a high-voltage status signal (HV_VALID) is issued;

[0043] On the basis of primary protection, the present invention uses the combination of the status controller 20 and the status validator 30 for secondary protection of the memory. There are 2 sets of status control circuits with the same structure inside the status controller 20, that is, the combination of the status control module and the counter, which is used to control status monitoring. The two sets of status control circuits operate independently and generate the first status signal and the second status signal. Under normal conditions, the first status signal and the second status signal should be in the same state. When the status signals are different, it indicates that an abnormality has occurred in the internal register. The status validator 30 immediately closes the Flash signal control signal to avoid incorrect erasing operations on the inside of the Flash.

[0044] The control signal decoder 40 is configured to receive an enable signal, a second status signal, and a high-voltage status signal. When the control decoder receives the high-voltage status signal, it sends a high-voltage control signal with an enabled status to the internal module of the Flash memory.

[0045] In an alternative embodiment, if the first and second status signals are the same, the output high-voltage status signal is at a high level; if they are different, the output high-voltage status signal is at a low level.

[0046] In an alternative embodiment, if the high-voltage enable signal is at a low level, the high-voltage enable signal remains at a low level.

[0047] In an alternative embodiment, if the high-voltage enable signal is at a low level, the control signal decoder 40 does not generate a high-voltage control signal. That is, the Flash Signal Decoder module receives all signals in a closed state, preventing misoperation of the internal Flash.

[0048] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the actual number, shape, and size of the components during actual implementation. The type, quantity, and ratio of each component during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0049] In summary, the enable signal gate (HV_EN_Gating) of the present invention is used for primary protection of the memory. Its structure has two D flip-flop structures with the same structure. Under normal circumstances, the values stored inside these two D flip-flops are ensured to be different through control logic. However, when the chip is not reset or is interfered with, these two D flip-flops are in adjacent positions, and the degree of interference they receive is relatively close. After being interfered with, the stored values have a high probability of being the same. In such a case, for the corresponding high-voltage enable signal, the internal high-voltage control signal is kept in a non-enabled state. On the basis of primary protection, the present invention uses a combination of a state controller and a state verifier for secondary protection of the memory. The state controller internally has two sets of state control circuits with the same structure, that is, a combination of a state control module and a counter, which is used to control state monitoring. The two sets of state control circuits operate independently to generate a first status signal and a second status signal. Under normal conditions, the first status signal and the second status signal of the status signals should be in the same state. When the status signals are different, it indicates that an abnormality has occurred in the internal register. The state verifier immediately closes the Flash signal control signal to prevent mis-erasure operations on the inside of the Flash. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0050] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A protection circuit for preventing accidental erasure of Flash memory, characterized in that, Comprising: An enable signal gate for receiving an enable signal, a high-voltage enable signal, and a high-voltage configuration signal, and generating an internal enable signal and an internal high-voltage configuration signal; A state controller for receiving the internal enable signal and then generating first and second state signals; A state validator for receiving the internal enable signal and the first and second state signals, and determining whether the levels of the first and second signals are consistent. If they are consistent, a high-voltage state signal is issued; A control signal decoder for receiving the enable signal, the second state signal, and the high-voltage state signal. After receiving the high-voltage state signal, the control signal decoder sends a high-voltage control signal with an enabled state to the internal module of the Flash memory.

2. The protection circuit for preventing accidental erasure of Flash memory according to claim 1, wherein: The enable signal gate uses a first AND gate to integrate the enable signal and the high-voltage enable signal to generate the internal enable signal.

3. The protection circuit for preventing accidental erasure of Flash memory according to claim 2, wherein: The output end of the first AND gate is electrically connected to the input ends of a first D flip-flop and an inverter respectively. The output end of the inverter is electrically connected to the input end of a second D flip-flop. The positive output end of the first D flip-flop and the negative output end of the second D flip-flop are electrically connected to the input ends of a second AND gate respectively. The output end of the second AND gate is used to provide the high-voltage enable signal.

4. The protection circuit for preventing accidental erasure of a Flash memory according to claim 3, characterized in that: The set values of the first and second D flip-flops are set to 0 and 1 respectively, corresponding to the disabled state of the high-voltage enable signal.

5. The protection circuit for preventing accidental erasure of Flash memory according to claim 1, characterized in that: The high-voltage enable signal and the high-voltage configuration signal output the internal high-voltage configuration signal through a third AND gate.

6. The protection circuit for preventing accidental erasure of a Flash memory according to claim 1, characterized in that: The state controller includes first and second state control modules and first and second counters. The first state control module and the second state control module are used to switch to the high-voltage state according to the high-voltage state signal and generate the first and second state signals respectively. The first and second counters are started to count respectively according to the start signals provided by the first and second state control modules, and feedback the start counts to the first and second state control modules respectively.

7. The protection circuit for preventing accidental erasure of a Flash memory according to claim 6, wherein: Both the first and second signals define the all-0 value as the starting state, and the starting state is that the internal high-voltage configuration signal is in the off state.

8. The protection circuit for preventing accidental erasure of Flash memory according to claim 1, characterized in that: The control signal decoder is used to convert the second state signal into a conversion signal applicable to the internal module.

9. The protection circuit for preventing accidental erasure of Flash memory according to claim 8, wherein: The control signal decoder includes a fourth AND gate and a flash memory signal decoding module. The second state signal and the high-voltage state signal output the conversion signal through the fourth AND gate, and the flash memory signal decoding module is used to convert the conversion signal into the high-voltage control signal.

10. The protection circuit for preventing accidental erasure of a Flash memory according to claim 1, characterized in that: If the first and second state signals are consistent, the output high-voltage state signal is at a high level. If they are inconsistent, the output high-voltage state signal is at a low level.

11. The protection circuit for preventing accidental erasure of a Flash memory according to claim 1, characterized in that: If the high-voltage enable signal is at a low level, the high-voltage state signal is at a low level.

12. The protection circuit for preventing accidental erasure of a Flash memory according to claim 10 or 11, characterized in that: If the high-voltage enable signal is at a low level, the control signal decoder does not generate the high-voltage control signal.

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