Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist on a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a fluoride-containing gas, wherein after removal of the patterned photoresist, fluoride residue from the gas remains on the top surface of the substrate. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor structure. Background Technology

[0002] Semiconductor structures are used in a wide variety of electronic devices, such as mobile phones, laptops, desktop computers, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronic components. A semiconductor structure generally consists of a semiconductor portion and wiring formed within the semiconductor portion. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor structure. The method includes forming a patterned photoresist on a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a fluoride-containing gas, wherein after removal of the patterned photoresist, fluoride residue from the gas remains on the top surface of the substrate. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.

[0004] This disclosure provides a method for forming a semiconductor structure. The method includes removing patterned photoresist from a top surface of a substrate. The method includes transferring the substrate to a wafer memory device. The method includes transferring the substrate from the wafer memory device to a first chamber. The method includes forming a first dielectric layer over the top surface of the substrate in the first chamber. The method includes transferring the substrate from the first chamber to the wafer memory device.

[0005] This disclosure provides a method for forming a semiconductor structure. The method includes removing patterned photoresist from a top surface of a substrate using a fluoride-containing gas, wherein after removal of the patterned photoresist, polymer residues from the patterned photoresist remain on the top surface of the substrate, and after removal of the patterned photoresist, fluoride residues from the gas remain on the top surface of the substrate. The method includes transferring the substrate to a cleaning tank. The method includes cleaning the top surface of the substrate in the cleaning tank to remove the polymer residues. The method includes transferring the substrate to a chamber. The method includes treating the substrate in the chamber using nitrous oxide to remove the fluoride residues. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best convey aspects of this disclosure. Note that, in accordance with standard practice in the art, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figures 1 to 18 Cross-sectional views of semiconductor structures at different stages of fabrication according to some embodiments are shown.

[0008] Figures 19 to 22 The diagram illustrates the movement of a semiconductor structure during fabrication according to some embodiments.

[0009] Figure 23 The diagram illustrates the processing of a semiconductor fabrication within a chamber according to some embodiments.

[0010] Figure 24 A cross-sectional view of a semiconductor structure during fabrication, according to some embodiments, is shown.

[0011] Figure 25 The diagram illustrates the movement of a semiconductor structure during fabrication according to some embodiments.

[0012] Figures 26 to 34 Cross-sectional views of semiconductor structures at different stages of fabrication according to some embodiments are shown.

[0013] Figure 35 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments.

[0014] Figure 36 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments.

[0015] Figure 37 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments.

[0016] Figure 38 Exemplary computer-readable media according to some embodiments are shown, which may include processor-executable instructions configured to implement one or more of the provisions set forth herein.

[0017] [Explanation of Symbols]

[0018] 100, 3400: Semiconductor Structure

[0019] 102: Substrate

[0020] 202: First photoresist

[0021] 302: First patterned photoresist

[0022] 304: First Opening

[0023] 402: Trench

[0024] 602: Isolation Structure

[0025] 602A: First isolation structure

[0026] 602B: Second isolation structure

[0027] 702: Second photoresist

[0028] 802: Second patterned photoresist

[0029] 804: Second opening

[0030] 806, 3002: Part One

[0031] 902: First doped region

[0032] 1102: Third photoresist

[0033] 1202: Third patterned photoresist

[0034] 1204: Third opening

[0035] 1206, 3004: Part Two

[0036] 1302: Second doped region

[0037] 1302A, 1302B, 1702A, 1702B: Doped regions

[0038] 1502: Fourth photoresist

[0039] 1602: Fourth Patterned Photoresist

[0040] 1604: The Fourth Opening

[0041] 1606: Part Three

[0042] 1702: Third doped region

[0043] 1802: First Chamber

[0044] 1902: Chip memory device

[0045] 2002: Cleaning tank

[0046] 2202: Second Chamber

[0047] 2302: Processing Materials

[0048] 2304: Emission pipe

[0049] 2306: Fluoride contents

[0050] 2308: Baffle

[0051] 2310: Sprayer Head

[0052] 2312: Heater

[0053] 2402: First dielectric layer

[0054] 2602: Fifth photoresist

[0055] 2702: Fifth Patterned Photoresist

[0056] 2704: The Fifth Opening

[0057] 2802: The Sixth Opening

[0058] 2902: Second Component

[0059] 2904: First Component

[0060] 3202: Second dielectric layer

[0061] 3302: Second conductive structure

[0062] 3304: First conductive structure

[0063] 3306: Direction

[0064] 3308: Partial

[0065] 3310: Central Area

[0066] 3312: Side area

[0067] 3402: Third dielectric layer

[0068] 3500, 3600, 3700, 3802: Methods

[0069] 3502, 3504, 3506, 3508, 3602, 3604, 3606, 3608, 3610, 3702, 3704, 3706, 3708, 3710: Steps

[0070] 3800: Example

[0071] 3804: Processor-executable computer instructions

[0072] 3806: Computer-readable data

[0073] 3808: Computer-readable media Detailed Implementation

[0074] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and constructions are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals or letters may be reused in various instances of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself imply a relationship between the various embodiments or configurations discussed.

[0075] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and other elements or features. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0076] Some embodiments relate to a method of forming a semiconductor structure. According to some embodiments, patterned photoresist is removed from the top surface of a substrate using a fluoride-containing gas. After removal of the patterned photoresist, fluoride residue from the gas remains on the top surface of the substrate. The substrate is treated with a processing material (e.g., nitrous oxide or at least one of other suitable materials) to remove the fluoride residue. After treating the substrate with the processing material, a first dielectric layer is formed on the substrate. Compared to some semiconductor structures formed without treating the substrate before forming the first dielectric layer, treating the substrate with a processing material before forming the first dielectric layer reduces the number of fluoride ions at the interface between the first dielectric layer and the substrate. Compared to some semiconductor structures formed without treating the substrate before forming the first dielectric layer, treating the substrate with a processing material before forming the first dielectric layer increases the amount of radiation obtained by the semiconductor structure during at least one operation of sensing, detecting, or converting into electrons. In some embodiments, the semiconductor structure includes optical elements. In some embodiments, the semiconductor structure operates as a sensor, such as at least one of the following: an optical sensor, an image sensor, a proximity sensor, or other types of sensor. Due to the increased amount of radiation received during at least one of the operations of sensing, detecting, or converting into electrons, the semiconductor structure operates more efficiently than other optical elements and / or sensors, for example, requiring less power, being more effective in relatively low light conditions, and providing higher resolution.

[0077] Figures 1 to 18 This is a cross-sectional view of a semiconductor fabrication 100 according to some embodiments. In some embodiments, at least one of an optical element, a sensor, or a photodiode is implemented via the semiconductor fabrication 100. The sensor includes at least one of the following: an optical sensor, an image sensor, a proximity sensor, a time-of-flight (ToF) sensor, an indirect ToF (iToF) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, or other types of sensors. Other structures and configurations of the semiconductor fabrication 100 and the sensors are within the scope of this disclosure.

[0078] Figure 1A semiconductor structure 100 according to some embodiments is illustrated. The semiconductor structure 100 includes a substrate 102. The substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. The substrate 102 comprises at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. According to some embodiments, the substrate 102 comprises single-crystal silicon, having… <100> Crystalline silicon with crystallographic orientation <110> Crystallographically oriented crystalline silicon or other suitable materials. In some embodiments, substrate 102 is a p-type semiconductor substrate (P-substrate). In some embodiments, substrate 102 is an n-type semiconductor substrate (N-substrate). Other structures and configurations of substrate 102 are within the scope of this disclosure.

[0079] Figure 2 A first photoresist 202 formed on a substrate 102 according to some embodiments is shown. The first photoresist 202 is present in at least one of the following situations: overlying the substrate 102; in direct contact with the top surface of the substrate 102; or in indirect contact with the top surface of the substrate 102. The first photoresist 202 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques.

[0080] The first photoresist 202 comprises a light-sensitive material, wherein the properties of the first photoresist 202 (e.g., solubility) are affected by light. The first photoresist 202 is either a negative photoresist or a positive photoresist. For a negative photoresist, when irradiated by a light source, the areas of the negative photoresist become insoluble, such that applying a solvent to the negative photoresist during a subsequent development stage removes the unirradiated areas of the negative photoresist. Therefore, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque areas of the template (e.g., a mask) between the light source and the negative photoresist. In a positive photoresist, the irradiated areas of the positive photoresist become soluble and are removed during development by applying a solvent. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque areas of the template (e.g., a mask) between the light source and the positive photoresist.

[0081] Figure 3 A first patterned photoresist 302 formed from a first photoresist 202 is shown according to some embodiments. The first patterned photoresist 302 defines a first opening 304 that exposes a portion of the substrate 102. Although two openings of the first opening 304 of the first patterned photoresist 302 are shown, any number of openings in the first opening 304 are expected.

[0082] Figure 4 The diagram illustrates the formation of trenches 402 in a substrate 102 using a first patterned photoresist 302 according to some embodiments. Although two trenches 402 in the substrate 102 are illustrated, any number of trenches 402 are contemplated. In some embodiments, an etching process is performed to form the trenches 402, wherein a first opening 304 in the first patterned photoresist 302 allows for the removal of portions of the substrate 102 by one or more etchants applied during the etching process, while the first patterned photoresist 302 protects or shields portions of the substrate 102 covered by the first patterned photoresist 302. The etching process is at least one of a dry etching process, a wet etching process, anisotropic etching process, isotropic etching process, or other suitable processes. The etching process uses at least one of hydrogen fluoride (HF), diluted HF, chlorinated compounds such as hydrogen chloride (HCl2), hydrogen sulfide (H2S), tetrafluoromethane (CF4), or other suitable materials. Other processes and techniques for forming trenches 402 are within the scope of this disclosure.

[0083] Figure 5The removal of a first patterned photoresist 302 according to some embodiments is illustrated. The first patterned photoresist 302 is removed after the trench 402 is formed. The first patterned photoresist 302 is removed by at least one of chemical mechanical planarization (CMP), a cleaning process, or other suitable techniques. In some embodiments, the first patterned photoresist 302 is removed using a fluoride-containing gas (e.g., HF, diluted HF, CF4, or at least one of other fluoride-containing gases). In some embodiments, after the removal of the first patterned photoresist 302, a first fluoride residue from the gas (e.g., ammonium fluoride silicate ((NH4)2SF6) or other fluoride-containing residual material) remains on the top surface of the substrate 102. In some embodiments, after the removal of the first patterned photoresist 302, a first polymer residue from at least one of the first photoresist 202 or the first patterned photoresist 302 remains on the top surface of the substrate 102.

[0084] Figure 6 An isolation structure 602 formed in a trench 402 according to some embodiments is shown. Although two isolation structures 602 are illustrated, any number of isolation structures 602 are contemplated. In some embodiments, the isolation structure 602 includes at least one of a first isolation structure 602A or a second isolation structure 602B. In some embodiments, the isolation structure 602 is a shallow trench isolation (STI) region. The isolation structure 602 comprises a dielectric material or other suitable material. In some embodiments, the isolation structure 602 comprises at least one of silicon, oxide, nitride such as silicon nitride, or other suitable materials. The isolation structure 602 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0085] An isolation structure 602 is at least partially formed within the substrate 102. In some embodiments, the top surface of the isolation structure 602 is located above the top surface of the substrate 102. In some embodiments, the top surface of the isolation structure 602 is substantially coplanar with the top surface of the substrate 102. In some embodiments, the top surface of the substrate 102 is located above the top surface of the isolation structure 602. The sidewalls of the isolation structure 602 are in at least one of the following situations: directly contacting the sidewalls of the defining trench 402 of the substrate 102 or indirectly contacting the sidewalls of the defining trench 402 of the substrate 102.

[0086] Figure 7A second photoresist 702 is shown formed on at least one of a substrate 102 or an isolation structure 602 according to some embodiments. The second photoresist 702 is present in at least one of the following states: overlying the substrate 102; in direct contact with the top surface of the substrate 102; or indirect contact with the top surface of the substrate 102. The second photoresist 702 is also present in at least one of the following states: overlying the isolation structure 602; in direct contact with the top surface of the isolation structure 602; or indirect contact with the top surface of the isolation structure 602. The second photoresist 702 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0087] Figure 8 A second patterned photoresist 802 formed by a second photoresist 702 is shown according to some embodiments. The second patterned photoresist 802 defines a second opening 804 that exposes a portion of the substrate 102. In some embodiments, the second opening 804 is located between isolation structures 602 such that the second opening 804 does not overlap the isolation structure 602 or is laterally offset relative to the isolation structure 602. In some embodiments, the second opening 804 overlaps at least some of the isolation structures of the isolation structure 602.

[0088] Figure 9 The first portion 806 of the substrate 102 (shown in some embodiments) is illustrated using a second patterned photoresist 802. Figure 8The substrate 102 is doped to form a first doped region 902. In some embodiments, at least some of the first doped regions 902 are located between isolation structures 602. In some embodiments, a portion of the first doped region 902 is located below the isolation structure 602. In some embodiments, a portion of the first doped region 902 is located below the isolation structure 602. A first portion 806 of the substrate 102 is doped to form the first doped region 902 by at least one of ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, the depth of the dopant in the substrate 102 is controlled by increasing or decreasing the voltage used to introduce the dopant into the substrate 102. Other processes and techniques for doping the first portion 806 of the substrate 102 or forming at least one of the first doped regions 902 are within the scope of this disclosure. In some embodiments, the first doped region 902 has a gradient, such that as the first doped region 902 extends into the substrate 102, the concentration of the dopant changes, for example, increases or decreases. In some embodiments, the first doped region 902 contains an n-type dopant. In some embodiments, the first doped region 902 is an n-well. In some embodiments, the first doped region 902 contains a p-type dopant. In some embodiments, the first doped region 902 is a p-well. Other configurations of the first doped region 902 are within the scope of this disclosure.

[0089] Figure 10 The removal of a second patterned photoresist 802 according to some embodiments is illustrated. The second patterned photoresist 802 is removed after a first portion 806 of the substrate 102 is doped to form a first doped region 902. The second patterned photoresist 802 is removed by at least one of CMP, a cleaning process, or other suitable techniques. In some embodiments, the second patterned photoresist 802 is removed using a fluoride-containing gas (e.g., HF, diluted HF, CF4, or at least one of other fluoride-containing gases). In some embodiments, after removal of the second patterned photoresist 802, a second fluoride residue from the gas (e.g., (NH4)2SF6 or other fluoride-containing residual material) remains on the top surface of the substrate 102. In some embodiments, after removal of the second patterned photoresist 802, a second polymer residue from at least one of the second photoresist 702 or the second patterned photoresist 802 remains on the top surface of the substrate 102.

[0090] Figure 11A third photoresist 1102 is shown formed on at least one of a substrate 102 or an isolation structure 602 according to some embodiments. The third photoresist 1102 is present in at least one of the following states: coated on the substrate 102; in direct contact with the top surface of the substrate 102; or indirect contact with the top surface of the substrate 102. The third photoresist 1102 is also present in at least one of the following states: coated on the isolation structure 602; in direct contact with the top surface of the isolation structure 602; or indirect contact with the top surface of the isolation structure 602. The third photoresist 1102 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0091] Figure 12 A third patterned photoresist 1202 formed from a third photoresist 1102 is shown according to some embodiments. The third patterned photoresist 1202 defines a third opening 1204 that exposes a portion of the substrate 102. Although two openings of the third opening 1204 of the third patterned photoresist 1202 are shown, any number of openings of the third opening 1204 are contemplated. In some embodiments, the third opening 1204 is located between isolation structures 602 such that the third opening 1204 does not overlap the isolation structure 602 or is laterally offset relative to the isolation structure 602. In some embodiments, the third opening 1204 overlaps at least some of the isolation structures 602.

[0092] Figure 13 This illustrates the use of a third patterned photoresist 1202 to pattern one or more second portions 1206 of a substrate 102 (shown in...) according to some embodiments. Figure 12The substrate 102 is doped to form one or more second doped regions 1302. In some embodiments, the one or more second doped regions 1302 include at least one of doped region 1302A or doped region 1302B. In some embodiments, at least some of the doped regions of the one or more second doped regions 1302 are located between isolation structures 602. The one or more second portions 1206 of the substrate 102 are doped to form the one or more second doped regions 1302 by at least one of ion implantation, molecular diffusion or other suitable techniques. In some embodiments, the depth of the dopant in the substrate 102 is controlled by increasing or decreasing the voltage used to introduce the dopant into the substrate 102. Other processes and techniques for doping the one or more second portions 1206 of the substrate 102 or forming at least one of the one or more second doped regions 1302 are within the scope of this disclosure. In some embodiments, the one or more second doped regions 1302 have a gradient, such that the concentration of the dopant changes, for example, increases or decreases, as the one or more second doped regions 1302 extend into the substrate 102. In some embodiments, the one or more second doped regions 1302 comprise an n-type dopant. In some embodiments, the one or more second doped regions 1302 comprise a p-type dopant. Other configurations of the one or more second doped regions 1302 are within the scope of this disclosure.

[0093] Figure 14 The removal of a third patterned photoresist 1202 according to some embodiments is illustrated. The third patterned photoresist 1202 is removed after the substrate 102 has been doped with one or more second portions 1206 to form one or more second doped regions 1302. The third patterned photoresist 1202 is removed by at least one of CMP, a cleaning process, or other suitable techniques. In some embodiments, the third patterned photoresist 1202 is removed using a fluoride-containing gas (e.g., HF, diluted HF, CF4, or at least one of other fluoride-containing gases). In some embodiments, after the removal of the third patterned photoresist 1202, a third fluoride residue (e.g., (NH4)2SF6 or other fluoride-containing residual material) from the gas remains on the top surface of the substrate 102. In some embodiments, after the removal of the third patterned photoresist 1202, a third polymer residue from at least one of the third photoresist 1102 or the third patterned photoresist 1202 remains on the top surface of the substrate 102.

[0094] Figure 15A fourth photoresist 1502 is shown formed on at least one of a substrate 102 or an isolation structure 602 according to some embodiments. The fourth photoresist 1502 is present in at least one of the following states: coated on the substrate 102; in direct contact with the top surface of the substrate 102; or indirect contact with the top surface of the substrate 102. The fourth photoresist 1502 is also present in at least one of the following states: coated on the isolation structure 602; in direct contact with the top surface of the isolation structure 602; or indirect contact with the top surface of the isolation structure 602. The fourth photoresist 1502 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0095] Figure 16 A fourth patterned photoresist 1602 formed from a fourth photoresist 1502 is shown according to some embodiments. The fourth patterned photoresist 1602 defines a fourth opening 1604 that exposes a portion of the substrate 102. Although two openings of the fourth opening 1604 of the fourth patterned photoresist 1602 are shown, any number of openings of the fourth opening 1604 are contemplated. In some embodiments, the fourth opening 1604 does not overlap the isolation structure 602 or is laterally offset relative to the isolation structure 602. In some embodiments, the fourth opening 1604 overlaps at least some of the isolation structures 602.

[0096] Figure 17 This illustrates the use of a fourth patterned photoresist 1602 to pattern one or more third portions 1606 of a substrate 102 according to some embodiments (shown in...). Figure 16The substrate 102 is doped to form one or more third doped regions 1702. In some embodiments, the one or more third doped regions 1702 include at least one of doped region 1702A or doped region 1702B. In some embodiments, a first isolation structure 602A is located between doped region 1702A and doped region 1702B of the one or more third doped regions 1702. In some embodiments, a first isolation structure 602A of the isolation structure 602 is located between doped region 1702A and second isolation structure 602B of the isolation structure 602. Other configurations of the one or more third doped regions 1702 are within the scope of this disclosure. The one or more third portions 1606 of the substrate 102 are doped to form the one or more third doped regions 1702 by at least one of ion implantation, molecular diffusion or other suitable techniques. In some embodiments, the depth of the dopant in the substrate 102 is controlled by increasing or decreasing the voltage used to introduce the dopant into the substrate 102. Other processes and techniques for forming at least one of the one or more third portions 1606 of the substrate 102 or forming the one or more third doped regions 1702 are within the scope of this disclosure. In some embodiments, the one or more third doped regions 1702 have a gradient, such that the concentration of the dopant changes, for example, increases or decreases, as the one or more third doped regions 1702 extend into the substrate 102. In some embodiments, the one or more third doped regions 1702 contain n-type dopant. In some embodiments, the one or more third doped regions 1702 contain p-type dopant. Other configurations of the one or more third doped regions 1702 are within the scope of this disclosure.

[0097] Figure 18The removal of a fourth patterned photoresist 1602 according to some embodiments is illustrated. The fourth patterned photoresist 1602 is removed after the substrate 102 has been doped with the one or more third portions 1606 to form the one or more third doped regions 1702. The fourth patterned photoresist 1602 is removed by at least one of CMP, a cleaning process, or other suitable techniques. In some embodiments, the fourth patterned photoresist 1602 is removed using a fluoride-containing gas (e.g., HF, diluted HF, CF4, or at least one of other fluoride-containing gases). In some embodiments, after the removal of the fourth patterned photoresist 1602, a fourth fluoride residue (e.g., (NH4)2SF6 or other fluoride-containing residual material) from the gas remains on the top surface of the substrate 102. In some embodiments, after the removal of the fourth patterned photoresist 1602, a fourth polymer residue from at least one of the fourth photoresist 1502 or the fourth patterned photoresist 1602 remains on the top surface of the substrate 102.

[0098] In some embodiments, the fourth patterned photoresist 1602 is removed in the first chamber 1802. In some embodiments, at least one of the following operations is performed in the first chamber 1802: forming a first photoresist 202, forming a first patterned photoresist 302, forming a trench 402, removing the first patterned photoresist 302, forming an isolation structure 602, forming a second photoresist 702, forming a second patterned photoresist 802, doping a first portion 806 of the substrate 102 to form a first doped region 902, removing the second patterned photoresist 802, forming a third photoresist 1102, forming a third patterned photoresist 1202, doping the one or more second portions 1206 of the substrate 102 to form the one or more second doped regions 1302, removing the third patterned photoresist 1202, forming a fourth photoresist 1502, forming a fourth patterned photoresist 1602, or doping the one or more third portions 1606 of the substrate 102 to form the one or more third doped regions 1702.

[0099] Figure 19A semiconductor structure 100 is shown being transferred to a wafer storage device 1902. In some embodiments, the semiconductor structure 100 is transferred from a first chamber 1802 to the wafer storage device 1902 after the fourth patterned photoresist 1602 is removed. The wafer storage device 1902 is at least one of a wafer storage pod (e.g., a front-opening unified pod, FOUP) or other suitable storage device. In some embodiments, one or more wafers (e.g., a batch of wafers) are temporarily stored in the wafer storage device 1902 or other wafer storage device during intervals between different processes (e.g., at least one of etching, ashing, stripping, metallization, CMP, deposition, etc.). The semiconductor structure 100 is located within the wafer of the one or more wafers. In some embodiments, the one or more wafers are vertically stacked in the wafer storage device 1902 and supported by a support frame having multiple individual wafer racks or slots within the wafer storage device 1902. In some embodiments, at least one of humidity or contamination within the wafer storage device 1902 is controlled to maintain the integrity of the wafers within the wafer storage device 1902.

[0100] Figure 20 A semiconductor structure 100 is shown being transferred to a cleaning tank 2002 according to some embodiments. In some embodiments, the semiconductor structure 100 is transferred from a wafer storage device 1902 to the cleaning tank 2002. At least some of the substrates 102 (e.g., the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate 102) are cleaned in the cleaning tank 2002. In some embodiments, the substrates 102 are cleaned using a liquid (e.g., deionized water or other suitable material). Cleaning the substrates 102 achieves the effect of removing or reducing at least one of the polymer contents on the substrates 102 (e.g., on the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate). The polymer contents include at least one of the following: a first polymer residue from at least one of the first photoresist 202 or the first patterned photoresist 302, a second polymer residue from at least one of the second photoresist 702 or the second patterned photoresist 802, a third polymer residue from at least one of the third photoresist 1102 or the third patterned photoresist 1202, or a fourth polymer residue from at least one of the fourth photoresist 1502 or the fourth patterned photoresist 1602.

[0101] Figure 21The illustration shows a semiconductor structure 100 transferred to a wafer storage device 1902 according to some embodiments. In some embodiments, the semiconductor structure 100 is transferred from the cleaning tank 2002 to the wafer storage device 1902 after at least some of the substrates 102 have been cleaned in the cleaning tank 2002.

[0102] In some embodiments, at least some of the substrates 102 (e.g., the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate 102) are etched using an etching process. The etching process is at least one of dry etching, wet etching, anisotropic etching, isotropic etching, or other suitable processes. The etching process uses at least one of HF, diluted HF, chlorine compounds such as HCl2, H2S, CF4, or other suitable materials. The etching process is performed to achieve the effect of removing or reducing at least one of negative oxides on the substrate 102 (e.g., on the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate). In some embodiments, the etching process is performed after cleaning the semiconductor fabrication 100 or after transferring the semiconductor fabrication 100 to at least one of the wafer storage devices 1902. In some embodiments, the semiconductor structure 100 is transferred from the wafer storage device 1902 to a chamber (e.g., a first chamber 1802 or at least one of other chambers), and an etching process is performed in the chamber. After the etching process is performed, the semiconductor structure 100 is transferred from the chamber to the wafer storage device 1902.

[0103] Figure 22 A semiconductor structure 100 is shown being transferred to a second chamber 2202 according to some embodiments. In some embodiments, the second chamber 2202 is different from the first chamber 1802. In some embodiments, the second chamber 2202 is the same as the first chamber 1802. The semiconductor structure 100 is transferred from a wafer storage device 1902 to the second chamber 2202, for example, after performing an etching process to achieve at least one effect of removing or reducing negative oxides on the substrate 102.

[0104] Figure 23A semiconductor fabrication 100 is illustrated being processed in a second chamber 2202 using a processing material 2302 according to some embodiments. In some embodiments, the semiconductor fabrication 100 is processed using the processing material 2302 to achieve at least one effect of removing or reducing fluoride contents 2306 on a substrate 102 (e.g., on the top surface of the substrate 102 or on at least one of one or more other surfaces of the substrate 102). The fluoride contents 2306 include at least one of: a first fluoride residue from a gas used to remove a first patterned photoresist 302, a second fluoride residue from a gas used to remove a second patterned photoresist 802, a third fluoride residue from a gas used to remove a third patterned photoresist 1202, or a fourth fluoride residue from a gas used to remove a fourth patterned photoresist 1602. In some embodiments, the fluoride contents 2306 include fluoride ions. In some embodiments, while processing the semiconductor structure 100 with the processing material 2302, the semiconductor structure 100 is heated with the heater 2312.

[0105] The treatment material 2302 includes at least one of nitrous oxide or other suitable materials. Figure 23 In the diagram, arrows with solid lines indicate the movement of the processing material 2302, and arrows with dashed lines indicate the movement of the fluoride contents 2306. In some embodiments, the processing material 2302 is pumped into a second chamber 2202. In some embodiments, the processing material 2302 is delivered to the semiconductor fabrication 100 via at least one of a baffle plate 2308 or a spray head 2310. In some embodiments, the baffle plate 2308 provides uniform deposition or flow of the processing material 2302 through the spray head 2310 to deliver it to the semiconductor fabrication 100. In some embodiments, the processing material 2302 flows through at least one of the baffle plate 2308 or the spray head 2310 and impacts the semiconductor fabrication 100.

[0106] In some embodiments, the impact of the processing material 2302 on the semiconductor fabrication 100 removes fluoride contents 2306 from at least some of the substrates 102 (e.g., the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate). The processing material 2302 impacts the fluoride contents 2306 to remove the fluoride contents 2306 from at least some of the substrates 102 (e.g., the top surface of the substrate 102 or at least one of one or more other surfaces of the substrate). In some embodiments, one or more discharge pipes 2304 are used to remove the fluoride contents 2306 from the second chamber 2202. In some embodiments, the one or more discharge pipes 2304 conduct the fluoride contents 2306 from the second chamber 2202 to the outside of the second chamber 2202.

[0107] In some embodiments, the concentration of the fluoride contents 2306 is greater on the side regions of the top surface of the substrate 102 than at the center of the top surface of the substrate 102. In some embodiments, more processing material 2302 is directed toward the side regions of the top surface of the substrate 102, for example, by a configuration such as an opening in at least one of the baffle plate 2308 or a spray head 2310, so that the degree of interaction between the processing material 2302 and the fluoride contents 2306 is greater on the side regions of the top surface of the substrate 102 than at the center of the top surface of the substrate 102.

[0108] In some embodiments, the impact of the processing material 2302 on the semiconductor structure 100 causes a thin film to form on the top surface of the substrate 102. In some embodiments, the thin film contains dangling bonds of the atoms of the processing material 2302. In some embodiments where the processing material 2302 comprises at least one of nitrous oxide or the substrate comprises silicon, the thin film contains dangling bonds of at least one of nitrogen, oxygen, or silicon. In some embodiments, the thin film comprises SiO. x N y The thin film has a thickness between about 1 nanometer and about 3 nanometers. Other thickness values ​​are within the range of this disclosure. The thin film inhibits the accumulation of contaminants (such as fluoride ions or at least one of other contaminants) on the top surface of substrate 102.

[0109] Figure 24 A first dielectric layer 2402 is shown formed on at least one of a substrate 102 or an isolation structure 602 according to some embodiments. The first dielectric layer 2402 is in at least one of the following states: overlying the substrate 102; in direct contact with the top surface of the substrate 102; or indirectly contacting the top surface of the substrate 102. In some embodiments, a thin film is located between the first dielectric layer 2402 and the substrate 102. The first dielectric layer 2402 is in at least one of the following states: overlying the isolation structure 602; in direct contact with the top surface of the isolation structure 602; or indirectly contacting the top surface of the isolation structure 602. The first dielectric layer 2402 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the first dielectric layer 2402 is a resist protective oxide (RPO) layer. In some embodiments, the first dielectric layer 2402 comprises at least one of oxides or other suitable materials.

[0110] In some embodiments, a first dielectric layer 2402 is formed in a second chamber 2202. The first dielectric layer 2402 is formed in the second chamber 2202 after the substrate 102 has been treated with a processing material 2302. In some embodiments, the first dielectric layer 2402 is formed in a chamber other than the second chamber 2202 (e.g., a first chamber 1802 or other chambers).

[0111] Figure 25 The illustration shows a semiconductor fabrication 100 transferred to a wafer memory device 1902 according to some embodiments. In some embodiments in which a first dielectric layer 2402 is formed in a second chamber 2202, the semiconductor fabrication 100 is transferred from the second chamber 2202 to the wafer memory device 1902 after the formation of the first dielectric layer 2402. In some embodiments in which the first dielectric layer 2402 is formed in a chamber different from the second chamber 2202, the semiconductor fabrication 100 is transferred from the chamber to the wafer memory device 1902 after the formation of the first dielectric layer 2402.

[0112] Figure 26 A fifth photoresist 2602 is shown formed on a first dielectric layer 2402 according to some embodiments. The fifth photoresist 2602 is present in at least one of the following situations: overlying the first dielectric layer 2402; in direct contact with the top surface of the first dielectric layer 2402; or indirect contact with the top surface of the first dielectric layer 2402. The fifth photoresist 2602 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0113] Figure 27 A fifth patterned photoresist 2702 formed from a fifth photoresist 2602 is shown according to some embodiments. The fifth patterned photoresist 2702 defines a fifth opening 2704 that exposes a portion of the first dielectric layer 2402. Although four openings of the fifth opening 2704 of the fifth patterned photoresist 2702 are shown, any number of openings of the fifth opening 2704 are contemplated. In some embodiments, the fifth opening 2704 covers a doped region of at least one of the one or more second doped regions 1302 or the one or more third doped regions 1702.

[0114] Figure 28This illustration shows the formation of one or more sixth openings 2802 in a first dielectric layer 2402 using a fifth patterned photoresist 2702 according to some embodiments. In some embodiments, the one or more sixth openings 2802 expose the top surface of the substrate 102. A portion of the first dielectric layer 2402 is removed to form the openings of the one or more sixth openings 2802. The one or more sixth openings 2802 are overlaid on a doped region of at least one of the one or more second doped regions 1302 or the one or more third doped regions 1702. In some embodiments, the one or more sixth openings 2802 expose the doped region of at least one of the one or more second doped regions 1302 or the one or more third doped regions 1702. Other processes and techniques for forming the one or more sixth openings 2802 are within the scope of this disclosure.

[0115] Figure 29 One or more first components 2904 and one or more second components 2902 formed on a substrate 102 according to some embodiments are shown. In some embodiments, the one or more first components 2904 are overlaid on the one or more second doped regions 1302. Components of the one or more first components 2904 are located on or within doped regions of the one or more second doped regions 1302. In some embodiments, the one or more first components 2904 comprise at least one of silicide components, self-aligned silicide components, or other suitable materials. Other configurations and structures of the one or more first components 2904 are within the scope of this disclosure.

[0116] In some embodiments, the one or more first components 2904 are formed by forming metal at least over the one or more second doped regions 1302 and then heating the semiconductor structure 100 after metal formation. Other processes and techniques for forming the one or more first components 2904 are within the scope of this disclosure.

[0117] In some embodiments, the one or more second components 2902 are overlaid on the one or more third doped regions 1702. The components of the one or more second components 2902 are located on or within the doped regions of the one or more third doped regions 1702. In some embodiments, the one or more second components 2902 comprise at least one of silicide components, self-aligned silicide components, or other suitable materials. Other configurations and structures of the one or more second components 2902 are within the scope of this disclosure.

[0118] In some embodiments, the one or more second components 2902 are formed by forming metal over the one or more third doped regions 1702 and then heating the semiconductor structure 100 after metal formation. Other processes and techniques for forming the one or more second components 2902 are within the scope of this disclosure.

[0119] Figure 30 The removal of a fifth patterned photoresist 2702 is illustrated according to some embodiments. In some embodiments, the fifth patterned photoresist 2702 is removed after the formation of the one or more first components 2904 and the one or more second components 2902. The fifth patterned photoresist 2702 is removed by at least one of CMP, a cleaning process, or other suitable techniques.

[0120] Figure 31 A first portion 3002 of the first dielectric layer 2402 according to some embodiments is shown (shown in...) Figure 30 (in the middle) or the second portion 3004 of the first dielectric layer 2402 (shown in Figure 30 Removal of at least one of the first portion 3002 or the second portion 3004 of the first dielectric layer 2402. In some embodiments, at least one of the first portion 3002 or the second portion 3004 of the first dielectric layer 2402 is removed by at least one of CMP, etching or other suitable techniques.

[0121] Figure 32A second dielectric layer 3202 formed on a substrate 102 according to some embodiments is shown. In some embodiments, the second dielectric layer 3202 is in at least one of the following states: covering the substrate 102; directly contacting the top surface of the substrate 102; or indirectly contacting the top surface of the substrate 102. In some embodiments, the second dielectric layer 3202 is in at least one of the following states: covering the isolation structure 602; directly contacting the top surface of the isolation structure 602; or indirectly contacting the top surface of the isolation structure 602. In some embodiments, the second dielectric layer 3202 is in at least one of the following states: covering the one or more first components 2904; directly contacting the top surface of the components of the one or more first components 2904; or indirectly contacting the top surface of the components of the one or more first components 2904. In some embodiments, the second dielectric layer 3202 is in at least one of the following states: covering the one or more second components 2902; directly contacting the top surface of the components of the one or more second components 2902; or indirectly contacting the top surface of the components of the one or more second components 2902. In some embodiments, a first dielectric layer 2402 is located between a first portion and a second portion of a second dielectric layer 3202. The second dielectric layer 3202 comprises at least one of silicon, nitride, oxide (e.g., SiO2), or other suitable materials. The second dielectric layer 3202 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the second dielectric layer 3202 is an interlevel dielectric (ILD).

[0122] Figure 33 This illustration shows one or more first conductive structures 3304 and one or more second conductive structures 3302 formed in a second dielectric layer 3202 according to some embodiments. In some embodiments, the one or more first conductive structures 3304 are formed by forming one or more openings (not shown) in the second dielectric layer 3202 and forming the one or more first conductive structures 3304 in the one or more openings. The one or more first conductive structures 3304 are formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. Other processes and techniques for forming the one or more first conductive structures 3304 are within the scope of this disclosure.

[0123] In some embodiments, the conductive structure of the one or more first conductive structures 3304 is in at least one of the following situations: covering the components of the one or more first components 2904; directly contacting the top surface of the components of the one or more first components 2904; or indirectly contacting the top surface of the components of the one or more first components 2904. The one or more first conductive structures 3304 comprise a conductive material, such as a metallic material or other suitable material. Although two conductive structures of the one or more first conductive structures 3304 are illustrated, any number of conductive structures of the one or more first conductive structures 3304 are contemplated. In some embodiments, the one or more first conductive structures 3304 are at least one of one or more metal contacts, one or more metal pads, one or more through-holes, or one or more metal terminals. In some embodiments, the one or more first conductive structures 3304 are connected to at least one of various doping features, circuit systems, inputs / outputs, etc., of the semiconductor fabric 100. Other structures and configurations of the one or more first conductive structures 3304 are within the scope of this disclosure.

[0124] In some embodiments, the one or more second conductive structures 3302 are formed by forming one or more openings (not shown) in the second dielectric layer 3202 and forming the one or more second conductive structures 3302 in the one or more openings. The one or more second conductive structures 3302 are formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. Other processes and techniques for forming the one or more second conductive structures 3302 are within the scope of this disclosure.

[0125] In some embodiments, the conductive structure of the one or more second conductive structures 3302 is in at least one of the following situations: covering the components of the one or more second components 2902; directly contacting the top surface of the components of the one or more second components 2902; or indirectly contacting the top surface of the components of the one or more second components 2902. The one or more second conductive structures 3302 contain a conductive material, such as a metallic material or other suitable material. Even though two conductive structures of the one or more second conductive structures 3302 are illustrated, any number of conductive structures of the one or more second conductive structures 3302 are contemplated. In some embodiments, the one or more second conductive structures 3302 are at least one of one or more metal contacts, one or more metal pads, one or more vias, or one or more metal terminals. In some embodiments, the second conductive structure 3302 is connected to at least one of various doping features, circuit systems, inputs / outputs, etc., of the semiconductor fabrication 100. Other structures and configurations of the one or more second conductive structures 3302 are within the scope of this disclosure.

[0126] In some embodiments, the semiconductor structure 100 is configured to perform at least one of sensing radiation, detecting radiation, or converting radiation into electrons. In some embodiments, at least some of the radiation travels toward the semiconductor structure 100 (e.g., in direction 3306). In some embodiments, at least some of the radiation passes through at least some of the first dielectric layers 2402 or at least some of the substrates 102. In some embodiments, at least some of the radiation passing through the substrate 102 (e.g., passing through the first doped region 902) is converted into electrons through the substrate 102. In some embodiments, at least some of the radiation is converted into electrons at a junction between the first doped region 902 and a portion 3308 of the substrate 102 adjacent to the first doped region 902. In some embodiments, a portion 3308 of the substrate 102 is spaced apart from either the first doped region 902 or an undoped region of the substrate 102. In some embodiments, a measure of radiation, such as the amplitude of ambient light, is determined by determining the electrical properties (e.g., at least one of current or voltage) of one or more of the first conductive structures 3304 or one or more of the second conductive structures 3302 or at least one of the first conductive structures 3304 or one or more of the second conductive structures 3302.

[0127] Contaminants between substrate 102 and the first dielectric layer 2402 (e.g., fluoride ions at the interface defined between substrate 102 and the first dielectric layer 2402) can affect the performance of semiconductor fabrication 100. In some embodiments, a higher amount of fluoride ions at the interface can result in lower levels of radiation obtained by the semiconductor fabrication 100 during at least one of sensing, detection, or conversion into electrons. In some embodiments, fluoride ions introduce a charge, such as a negative charge, into the interface. In some embodiments, the charge can lead to at least one of the following: reduced sensitivity of the junction between the first doped region 902 and a portion 3308 of substrate 102; or lower levels of radiation obtained during at least one of sensing, detection, or conversion into electrons at the junction.

[0128] Compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer, treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402 provides a reduction in contaminants at the interface between the substrate 102 and the first dielectric layer 2402. In some embodiments, treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402 provides a reduction, for example, a reduction of about 24%, in at least one of the fluoride ion strength or the amount of fluoride ions at the interface between the substrate 102 and the first dielectric layer 2402, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer on the substrate 102, treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402 provides a reduction, for example, a reduction of about 63%, in the difference between the amount of fluoride ions in the central region 3310 of the interface and the amount of fluoride ions in the side region 3312 of the interface. In some embodiments, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer on the substrate, treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402 provides an increase in the amount of radiation obtained by the semiconductor structure 100 performing at least one operation of sensing, detecting, or converting. In some embodiments, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer on the substrate 102, treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402 provides an increased amount of nitrogen at the interface between the substrate 102 and the first dielectric layer 2402. In some embodiments, treating the substrate 102 with a processing material 2302 before forming the first dielectric layer 2402 provides an increased nitrogen intensity to fluoride intensity ratio at the interface between the substrate 102 and the first dielectric layer 2402, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, by treating the substrate 102 with the processing material 2302 before forming the first dielectric layer 2402, the nitrogen intensity to fluoride intensity ratio at the interface between the substrate 102 and the first dielectric layer 2402 is between about 10 and about 11. Some semiconductor structures formed without treating the substrate before forming the dielectric layer have a nitrogen intensity to fluoride intensity ratio between about 3 and about 4 at the interface between the dielectric layer and the substrate.

[0129] In some embodiments, treating the substrate 102 with a processing material 2302 prior to the formation of the first dielectric layer 2402 provides improved optical properties of the semiconductor structure 100, such as at least one of improved quantum efficiency or improved photosensitivity, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. Treating the substrate 102 with the processing material 2302 prior to the formation of the first dielectric layer 2402 reduces contaminants (e.g., fluoride ions) at the interface between the substrate 102 and the first dielectric layer 2402, and thus increases the sensitivity of the junction between the first doped region 902 and a portion 3308 of the substrate 102, and improves the quantum efficiency of the semiconductor structure 100 (e.g., by reducing contaminants at the interface between the substrate 102 and the first dielectric layer 2402, resulting in a greater amount of radiation at the junction for at least one of sensing, detection, or conversion into electrons).

[0130] In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides improved photosensitivity of the semiconductor structure 100 compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 3.6% in photosensitivity of the semiconductor structure 100 to blue light (e.g., having wavelengths between approximately 430 nm and approximately 510 nm) compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 7% in photosensitivity of the semiconductor structure 100 to red light (e.g., having wavelengths between approximately 620 nm and approximately 720 nm) compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 7.9% in the photosensitivity of the semiconductor structure 100 to infrared radiation (e.g., wavelengths greater than about 750 nanometers) compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 3.6% in the amount of blue light (e.g., wavelengths between about 430 nanometers and about 510 nanometers) obtained by the semiconductor structure 100 in at least one of sensing, detection, or conversion operations. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 7% in the amount of red light (e.g., having a wavelength between approximately 620 nm and approximately 720 nm) obtained by at least one operation of sensing, detection, or conversion performed by the semiconductor structure 100, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer 2402. In some embodiments, treating the substrate 102 with processing material 2302 before forming the first dielectric layer 2402 provides an increase of approximately 7.9% in the amount of infrared radiation (e.g., having a wavelength greater than approximately 750 nm) obtained by at least one operation of sensing, detection, or conversion performed by the semiconductor structure 100, compared to some semiconductor structures formed without treating the substrate before forming the dielectric layer 2402.

[0131] In some processes used to form semiconductor structures, the substrate is not treated with processing materials before forming a dielectric layer on it. Different processes are performed on the substrate to form doped regions, such as at least one of a first doped region 902, one or more second doped regions 1302, or one or more third doped regions 1702. During the intervals between different processes, the substrate is stored in a wafer storage device. After performing different processes, fluoride residues from those processes remain on the surface of the substrate. After performing different processes, the substrate is transferred to the wafer storage device. While storing the substrate in the wafer storage device, chemicals such as fluoride ions are degassed from the substrate and adhered to the inner surface of the wafer storage device. The substrate is transferred from the wafer storage device to a cleaning tank. The substrate is cleaned in the cleaning tank. Instead of transferring the substrate back to the wafer storage device, the substrate is transferred to a cleaned wafer storage device different from the original wafer storage device. Before transferring the substrate to the cleaned wafer storage device, the cleaned wafer storage device is cleaned to reduce the amount of fluoride contents in the cleaned wafer storage device. The substrate is transferred from the cleaned wafer storage device to a chamber and an etching process is performed to remove negative oxides from one or more surfaces of the substrate. After the etching process, the substrate is transferred from the chamber to the cleaned wafer storage device. The cleaned wafer storage device contains fluoride ions after cleaning, and fluoride ions from the cleaned wafer storage device accumulate on one or more surfaces of the substrate while the substrate is stored in the cleaned wafer storage device. Therefore, the longer the substrate is stored in the cleaned wafer storage device, the more fluoride contents accumulate on one or more surfaces of the substrate. The substrate is transferred to the chamber, and a dielectric layer, such as a first dielectric layer 2402, is formed on the substrate. The wafer, including the substrate and the dielectric layer, is transferred to a different wafer storage device than the cleaned wafer storage device. After different substrates undergo different processes and are cleaned in a cleaning tank, the cleaned wafer storage device is cleaned again and used to store different substrates.

[0132] In some embodiments, the substrate 102 is stored in the wafer storage device 1902 before being transferred to the second chamber 2202. In some embodiments, after cleaning the substrate 102 in the cleaning tank 2002, the substrate 102 is not transferred to a different wafer storage device, such as a cleaned storage device. In some embodiments, since the substrate 102 is treated with processing material 2302 before forming the first dielectric layer 2402, the duration of storing the substrate 102 in the wafer storage device 1902 before transferring it to the second chamber 2202 has little effect on the amount of fluoride ions at the interface between the substrate 102 and the first dielectric layer 2402.

[0133] Figure 34 A cross-sectional view of a semiconductor fabrication 3400 according to some embodiments is shown. Semiconductor fabrication 3400 includes at least some elements, structures, layers, features, etc., of semiconductor fabrication 100. Semiconductor fabrication 3400 includes a third dielectric layer 3402. The third dielectric layer 3402 is in at least one of the following states: overlying the first dielectric layer 2402; in direct contact with the first dielectric layer 2402; or indirectly in contact with the first dielectric layer 2402. The third dielectric layer 3402 is in at least one of the following states: located below the second dielectric layer 3202; in direct contact with the second dielectric layer 3202; or indirectly in contact with the second dielectric layer 3202. The third dielectric layer 3402 comprises at least one of silicon, oxide, nitrides such as silicon nitride, or other suitable materials. In some embodiments, the third dielectric layer 3402 is a contact etch stop layer (CESL).

[0134] According to some embodiments, in Figure 35 The diagram illustrates a method 3500 for forming a semiconductor structure (e.g., semiconductor structure 100, semiconductor structure 3400, or at least one of other suitable semiconductor structures). At 3502, a patterned photoresist is formed over the top surface of a substrate. The patterned photoresist is at least one of a second patterned photoresist 802, a third patterned photoresist 1202, a fourth patterned photoresist 1602, or other suitable patterned photoresist. The substrate is at least one of a substrate 102 or other suitable substrate. At 3504, a portion of the substrate is doped using the patterned photoresist. The portion is at least one of a first portion 806, a portion of one or more second portions 1206, a portion of one or more third portions 1606, or other suitable portions. At 3506, the patterned photoresist is removed using a fluoride-containing gas. After the patterned photoresist is removed, fluoride residue from the gas remains on the top surface of the substrate. Fluoride residues include at least one of fluoride contents 2306 or other fluoride residues. At 3508, the substrate is treated with nitrous oxide to remove the fluoride residues.

[0135] According to some embodiments, in Figure 36The diagram illustrates a method 3600 for forming a semiconductor structure (e.g., semiconductor structure 100, semiconductor structure 3400, or at least one of other suitable semiconductor structures). At 3602, patterned photoresist is removed from the top surface of a substrate. The patterned photoresist is at least one of a first patterned photoresist 302, a second patterned photoresist 802, a third patterned photoresist 1202, a fourth patterned photoresist 1602, or other suitable patterned photoresist. The substrate is at least one of a substrate 102 or other suitable substrate. At 3604, the substrate is transferred to a wafer storage device, such as a wafer storage device 1902 or at least one of other suitable wafer storage devices. At 3606, the substrate is transferred from the wafer storage device to a cavity, such as a second cavity 2202 or at least one of other suitable cavities. At 3608, a first dielectric layer is formed in the cavity over the top surface of the substrate. The first dielectric layer is at least one of a first dielectric layer 2402 or other suitable dielectric layers. At 3610, the substrate is transferred from the chamber to the wafer storage device.

[0136] According to some embodiments, in Figure 37 The diagram illustrates a method 3700 for forming a semiconductor structure (e.g., semiconductor structure 100, semiconductor structure 3400, or at least one of other suitable semiconductor structures). At 3702, a patterned photoresist is removed from the top surface of a substrate using a fluoride-containing gas. The patterned photoresist is at least one of a first patterned photoresist 302, a second patterned photoresist 802, a third patterned photoresist 1202, a fourth patterned photoresist 1602, or other suitable patterned photoresist. The substrate is at least one of a substrate 102 or other suitable substrate. After the patterned photoresist is removed, polymer residues from the patterned photoresist remain on the top surface of the substrate. After the patterned photoresist is removed, fluoride residues from the gas remain on the top surface of the substrate. The fluoride residues include at least one of fluoride contents 2306 or other fluoride residues. At 3704, the substrate is transferred to a cleaning tank, such as cleaning tank 2002 or at least one of other suitable cleaning tanks. At 3706, the top surface of the substrate is cleaned in a cleaning tank to remove polymer residues. At 3708, the substrate is transferred to a chamber, such as a second chamber 2202 or at least one of other suitable chambers. At 3710, the substrate is treated in the chamber with nitrous oxide to remove fluoride residues.

[0137] One or more embodiments relate to a computer-readable medium containing processor-executable instructions configured to implement one or more of the techniques presented herein. Figure 38An exemplary computer-readable medium is illustrated, wherein embodiment 3800 includes a computer-readable medium 3808 (e.g., a Compact Disc Recordable (CD-R), a Digital Versatile Disc Recordable (DVD-R), a flash drive, a hard disk platter, etc.) encoded thereon with computer-readable data 3806. This computer-readable data 3806 then includes a set of processor-executable computer instructions 3804 configured to operate according to one or more of the principles set forth herein. In some embodiments 3800, the processor-executable computer instructions 3804 are configured to implement method 3802, such as at least some of the foregoing methods. In some embodiments, the processor-executable computer instructions 3804 are configured to implement a system, such as at least some of the one or more foregoing systems. Many such computer-readable media configured to operate according to the techniques presented herein can be designed by those skilled in the art.

[0138] According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein is in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein. According to some embodiments, at least one of the one or more layers, features, structures, elements, etc. disclosed herein is not in direct contact with another of the one or more layers, features, structures, elements, etc. disclosed herein, for example, where one or more intervening, spaced, etc., are present.

[0139] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a patterned photoresist on a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a fluoride-containing gas, wherein after removal of the patterned photoresist, fluoride residue from the gas remains on the top surface of the substrate. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.

[0140] In some embodiments, the method includes forming a first isolation structure and a second isolation structure in the substrate prior to treating the substrate with the nitrous oxide. In some embodiments, a first portion of the substrate is located between the first isolation structure and the second isolation structure. In some embodiments, the first isolation structure is located between the first portion of the substrate and the second isolation structure. In some embodiments, treating the substrate with the nitrous oxide includes pumping the nitrous oxide into a chamber including the substrate. In some embodiments, treating the substrate with the nitrous oxide includes removing the fluoride residue from the chamber using a discharge pipe.

[0141] In some embodiments, a method of forming a semiconductor structure is provided. The method includes removing patterned photoresist from a top surface of a substrate. The method includes transferring the substrate to a wafer memory device. The method includes transferring the substrate from the wafer memory device to a first chamber. The method includes forming a first dielectric layer over the top surface of the substrate in the first chamber. The method includes transferring the substrate from the first chamber to the wafer memory device.

[0142] In some embodiments, the method includes doping a first portion of the substrate using the patterned photoresist. In some embodiments, removal of the patterned photoresist is performed in a second chamber; and transferring the substrate to the wafer storage device includes transferring the substrate from the second chamber to the wafer storage device.

[0143] In some embodiments, a method of forming a semiconductor structure is provided. The method includes removing patterned photoresist from a top surface of a substrate using a fluoride-containing gas, wherein after removal of the patterned photoresist, polymer residues from the patterned photoresist remain on the top surface of the substrate, and after removal of the patterned photoresist, fluoride residues from the gas remain on the top surface of the substrate. The method includes transferring the substrate to a cleaning tank. The method includes cleaning the top surface of the substrate in the cleaning tank to remove the polymer residues. The method includes transferring the substrate to a chamber. The method includes treating the substrate in the chamber using nitrous oxide to remove the fluoride residues.

[0144] In some embodiments, the method includes transferring the substrate from the cleaning tank to the wafer storage device after cleaning the top surface of the substrate and before transferring the substrate to the chamber. In some embodiments, transferring the substrate to the chamber includes transferring the substrate from the wafer storage device to the chamber. In some embodiments, the method includes transferring the substrate from the chamber to the wafer storage device after treating the substrate with the nitrous oxide.

[0145] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0146] Although the subject matter has been described using language specific to structural features or methodological actions, it is understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing at least some of the claims.

[0147] Various operations are provided in the embodiments herein. The order in which some or all of the operations are described should not be construed as implying that these operations must be performed in that order. It will be understood that alternative orders also have the beneficial effects of this description. Furthermore, it will be understood that not all operations must exist in every embodiment provided herein. In addition, it will be understood that in some embodiments, not all operations are necessary.

[0148] It will be understood that in some embodiments, such as for the purposes of simplicity and ease of understanding, the layers, features, elements, etc. illustrated herein are illustrated with respect to specific dimensions (e.g., structural dimensions or orientations) relative to each other, and the actual dimensions of the layers, features, elements, etc. are substantially different from those illustrated herein. Furthermore, various techniques exist, such as at least one of the following, to form the layers, regions, features, elements, etc. mentioned herein: etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques (e.g., chemical vapor deposition (CVD)).

[0149] Furthermore, the term "exemplary" is used herein to refer to something serving as an instance, example, or illustration, and not necessarily to something advantageous. The word "or" as used in this application is intended to refer to an inclusive "or" rather than an exclusive "or." Additionally, unless otherwise specified or clearly indicated from the context, "a" (and "an") as used in this application and the appended claims is generally considered to mean "one or more." Furthermore, "at least one of A and B" and / or similar expressions generally refer to A or B, or both A and B. Moreover, with regard to the extent to which "includes," "having," "has," "with," or variations thereof are used, such terms are intended to indicate inclusion in a manner similar to the term "comprising." Additionally, unless otherwise specified, "first," "second," etc., are not intended to imply temporal, spatial, or sequential aspects. Specifically, such terms are used only as identifiers, names, etc., for features, elements, items, etc. For example, the first element and the second element generally correspond to element A and element B, or two different elements, or two identical elements, or the same element.

[0150] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and modifications and is limited only by the scope of the preceding claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), the terminology used to describe such components is intended to correspond to any component (unless otherwise stated) that performs the specified function of said component (e.g., functionally equivalent), even if said component is not structurally equivalent to the disclosed structure. Additionally, although specific features of this disclosure may be disclosed only with respect to one embodiment of several embodiments, such features may be combined with one or more other features of other embodiments where they may be desirable and advantageous for any given or particular application.

Claims

1. A method of forming a semiconductor construction, comprising: forming a patterned photoresist over a top surface of a substrate; doping a first portion of the substrate using the patterned photoresist; removing the patterned photoresist using a gas comprising a fluoride, wherein after removing the patterned photoresist, a fluoride residue from the gas remains on the top surface of the substrate; cleaning the top surface of the substrate; after cleaning the top surface of the substrate, etching the top surface of the substrate to remove a negative oxide; and after etching the top surface of the substrate to remove the negative oxide, treating the substrate using nitrous oxide to remove the fluoride residue.

2. The method of claim 1, comprising: after treating the substrate using the nitrous oxide, forming a first dielectric layer over the top surface of the substrate.

3. The method of claim 1, wherein: cleaning the top surface of the substrate comprises utilizing deionized water.

4. The method of claim 1, comprising: prior to treating the substrate using the nitrous oxide, forming a first isolation structure and a second isolation structure in the substrate.

5. The method of claim 4, wherein: the first portion of the substrate is between the first isolation structure and the second isolation structure.

6. The method of claim 4, wherein: the first isolation structure is between the first portion of the substrate and the second isolation structure.

7. The method of claim 1, wherein: treating the substrate using the nitrous oxide comprises pumping the nitrous oxide into a chamber comprising the substrate.

8. The method of claim 7, wherein: treating the substrate using the nitrous oxide comprises removing the fluoride residue from the chamber using a drain.

9. A method of forming a semiconductor construction, comprising: removing a patterned photoresist from a top surface of a substrate, wherein after removing the patterned photoresist, a fluoride residue remains on the top surface of the substrate; etching the top surface of the substrate to remove a negative oxide; after removing the negative oxide, treating the substrate to remove the fluoride residue from the top surface of the substrate; transferring the substrate to a wafer storage device; transferring the substrate from the wafer storage device to a first chamber; in the first chamber, forming a first dielectric layer over the top surface of the substrate; and transferring the substrate from the first chamber to the wafer storage device.

10. The method of claim 9, wherein: treating the substrate comprises treating the substrate using nitrous oxide to remove the fluoride residue.

11. The method of claim 9, comprising: doping a first portion of the substrate using the patterned photoresist.

12. The method of claim 9, wherein: ​ ​ removing the patterned photoresist is performed in a second chamber; and transferring the substrate to the wafer storage device includes transferring the substrate from the second chamber to the wafer storage device.

13. A method of forming a semiconductor construction, comprising: removing a patterned photoresist from a top surface of a substrate using a gas including a fluoride, wherein: after removing the patterned photoresist, a polymer residue from the patterned photoresist remains on the top surface of the substrate; and after removing the patterned photoresist, a fluoride residue from the gas remains on the top surface of the substrate; transferring the substrate to a cleaning tank; cleaning the top surface of the substrate in the cleaning tank to remove the polymer residue; etching the top surface of the substrate to remove a negative oxide; transferring the substrate to a chamber; and treating the substrate in the chamber using nitrous oxide to remove the fluoride residue.

14. The method of claim 13, comprising: forming a first dielectric layer over the top surface of the substrate after treating the substrate with the nitrous oxide.

15. The method of claim 13, comprising: after cleaning the top surface of the substrate and before transferring the substrate to the chamber, transferring the substrate from the cleaning tank to a wafer storage device.

16. The method of claim 15, wherein: transferring the substrate to the chamber includes transferring the substrate from the wafer storage device to the chamber.

17. The method of claim 16, comprising: after treating the substrate with the nitrous oxide, transferring the substrate from the chamber to the wafer storage device.

Images