A wire and a method for forming the same

Abstract

The present invention provides a wire and a method for forming the same. The forming method includes the following steps: providing a semiconductor substrate in which a dielectric layer is formed, and a trench is formed in the dielectric layer for forming a metal interconnect; forming a barrier layer on the bottom wall and side walls of the trench; physically bombarding the bottom wall of the trench to deepen the depth of the trench; and filling the trench with a metal material to form a metal interconnect, thereby forming a wire. By adding a physical bombardment process to the barrier layer on the bottom wall of the trench, the present invention can change the shape of the trench, and at the same time increase the filling longitudinal section of the metal material, which can effectively reduce the resistance value of the wire. Specifically, the resistance value of the wire can be reduced by about 5%, the occurrence of the RC delay phenomenon is reduced, and the response speed of the wire is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing processes, and particularly to a wire and a method for forming the same. Background Art

[0002] Currently, in the back-end-of-line (BEOL) process of semiconductor devices, when fabricating semiconductor integrated circuits, after the formation of the semiconductor device layer, a metal interconnect layer needs to be formed on the semiconductor device layer. Each metal interconnect layer includes metal interconnect lines and an insulating material layer.

[0003] The line width of the metal interconnect lines formed by the prior art is getting smaller and smaller. As the line width continues to shrink, the resistance value of the metal interconnect lines continuously increases, resulting in a more serious RC delay phenomenon, thereby reducing the response speed of semiconductor devices. Therefore, how to reduce the resistance value and improve the response speed of semiconductor devices is an important issue. Summary of the Invention

[0004] The purpose of the present invention is to provide a wire and a method for forming the same, which can reduce the resistance value and improve the response speed of semiconductor devices.

[0005] To achieve the above purpose, the present invention provides a method for forming a wire, including the following steps:

[0006] Provide a semiconductor substrate, in which a dielectric layer is formed, and a trench is formed in the dielectric layer, and the trench is used to form a metal interconnect line;

[0007] Form a barrier layer on the bottom wall and side walls of the trench;

[0008] Physically bombard the bottom wall of the trench to deepen the depth of the trench; and

[0009] Fill the trench with a metal material to form a metal interconnect line, and further form a wire.

[0010] Optionally, physically bombarding the bottom wall of the trench to deepen the depth of the trench includes:

[0011] Physically bombard the bottom wall of the trench in the reaction chamber for forming the barrier layer to deepen the depth of the trench, and also change the shape of the trench. Among them, when performing the physical bombardment, the gas introduced into the reaction chamber for the barrier layer includes an inert gas.

[0012] Further, when performing the physical bombardment, the gas introduced into the reaction chamber for the barrier layer includes argon.

[0013] Further, during physical bombardment, the flow rate of the argon gas introduced is 5 sccm to 30 sccm, and the AC power in the reaction chamber of the barrier layer is 200 W to 1500 W.

[0014] Further, the edge of the bottom wall of the trench is stepped.

[0015] Optionally, the method for forming the barrier layer includes:

[0016] Successively forming a tantalum nitride layer and a tantalum layer on the outer side of the trench and the inner wall of the trench through a deposition process.

[0017] Further, after filling the trench with a metal material, it further includes:

[0018] Successively removing the metal material outside the trench and the barrier layer through a chemical mechanical polishing process.

[0019] On the other hand, the present invention provides a wire including at least one metal interconnect prepared by the above method.

[0020] Compared with the prior art, the present invention has at least the following beneficial effects:

[0021] The present invention provides a wire and a method for forming the same. The forming method includes the following steps: providing a semiconductor substrate in which a dielectric layer is formed, a trench is formed in the dielectric layer, and the trench is used to form a metal interconnect; forming a barrier layer on the bottom wall and side wall of the trench; performing physical bombardment on the bottom wall of the trench to deepen the depth of the trench; and filling the trench with a metal material to form a metal interconnect, thereby forming a wire. By adding a physical bombardment process to the barrier layer on the bottom wall of the trench, the present invention can change the shape of the trench, and at the same time increase the filling longitudinal section of the metal material, effectively reducing the resistance value of the wire. Specifically, the resistance value of the wire can be reduced by about 5%, reducing the occurrence of RC delay phenomenon and improving the wire response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic flow chart of a method for forming a wire according to an embodiment of the present invention;

[0023] Figures 2a - 2e It is a schematic structural diagram of each step during the formation of a wire according to an embodiment of the present invention;

[0024] Figure 3 It is a relationship diagram between the resistance value of a copper wire and the wire width according to an embodiment of the present invention.

[0025] Description of the reference numerals:

[0026] 10 - dielectric layer; 20 - trench; 30 - barrier layer; 40 - metal material. Detailed implementation manners

[0027] A wire and a method for forming the same according to the present invention will be further described in detail below. The present invention will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the advantageous effects of the present invention. Therefore, the following description should be understood as a broad knowledge for those skilled in the art and not as a limitation to the present invention.

[0028] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary details. It should be considered that in the development of any actual embodiment, numerous implementation details must be made to achieve the specific goals of the developer, such as changes from one embodiment to another in accordance with the relevant system or business limitations. Additionally, it should be considered that such development work may be complex and time-consuming, but it is only routine work for those skilled in the art.

[0029] To make the objectives and features of the present invention more obvious and understandable, the specific implementation manners of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0030] Figure 1 is a flowchart of a method for forming a wire according to this embodiment. As Figure 1 shown, this embodiment provides a method for forming a wire, including the following steps:

[0031] S10: Provide a semiconductor substrate, in which a dielectric layer is formed, and a trench is formed in the dielectric layer, and the trench is used to form a metal interconnect;

[0032] S20: Form a barrier layer on the bottom wall and side walls of the trench;

[0033] S30: Physically bombard the bottom wall of the trench to deepen the depth of the trench; and

[0034] S40: Fill the trench with a metal material to form a metal interconnect, and then form a wire.

[0035] The following will be combined with Figures 1 - 3 to describe in detail the method for forming a wire provided in this embodiment.

[0036] Figure 2aSchematic structural diagram of the semiconductor substrate provided in this embodiment. As Figure 2a shown, first, step S10 is performed to provide a semiconductor substrate. A dielectric layer 10 is formed in the semiconductor substrate, and a trench 20 is formed in the dielectric layer 10. The trench 20 is used to form metal interconnects, and the depth of the trench 20 is H1.

[0037] Specifically, the semiconductor substrate is, for example, a silicon substrate. The dielectric layer 10 is located on the silicon substrate, and a trench 20 is formed in the dielectric layer 10. In order to effectively reduce the RC delay phenomenon, suppress crosstalk, and reduce power consumption, the dielectric layer 10 is usually a low-k dielectric layer. In this embodiment, the structure of the low-k dielectric layer is a porous structure. The size of the opening of the trench 20 is the largest, so that the longitudinal cross-section of the trench 20 is an inverted trapezoid. The trench 20 is used to form metal interconnects. Further, the trench 20 can be used to form any layer from the bottom metal interconnect to the top metal interconnect (i.e., Metal1~Metaln, where n is the total number of metal layers).

[0038] Please continue to refer to Figure 2a , and then step S20 is performed to form a barrier layer 30 on the bottom wall and side walls of the trench 20. The barrier layer 30 is used to prevent the metal material filled in the trench 20 later from diffusing into the dielectric layer 10. In this embodiment, the barrier layer 30 includes a tantalum nitride layer and a tantalum layer. In other embodiments, the barrier layer may also include other commonly used barrier materials, such as titanium nitride and titanium layers.

[0039] This step specifically includes: sequentially forming a tantalum nitride layer and a tantalum layer on the outside of the trench 20 and the inner wall (i.e., the bottom wall and side walls) of the trench 20 through a deposition process. The deposition process includes a physical vapor deposition (PVD) process and an ALD (atomic layer deposition) process.

[0040] In this step, the thickness of the barrier layer 30 deposited on the dielectric layer 10 outside the trench 20 is greater than the thickness of the barrier layer 30 on the bottom wall of the trench 20, and the thickness of the barrier layer 30 on the bottom wall of the trench 20 is greater than the thickness of the barrier layer 30 on the side walls of the trench 20.

[0041] Figure 2b Schematic structural diagram during the physical bombardment process of this embodiment. Figure 2c Schematic structural diagram after the physical bombardment of this embodiment. As Figures 2b - 2c shown, then step S30 is performed to physically bombard the bottom wall of the trench 20 to deepen the depth of the trench 20.

[0042] In this embodiment, the bombarding ions used in physical bombardment are inert ions (such as argon ions), that is, the gas introduced into the barrier layer reaction chamber is an inert gas (such as argon). The flow rate of the inert gas used in physical bombardment is 5 sccm to 30 sccm (standard gas volume unit / minute), and the AC power is 200 W to 1500 W. The incident angle of the bombarding ions used in physical bombardment is perpendicular to the semiconductor substrate, that is, the incident angle of the bombarding ions used in physical bombardment is parallel to the thickness direction of the semiconductor substrate. The size of the projection of the side wall of the trench 20 in the direction perpendicular to the thickness direction of the semiconductor substrate is very small. This makes it so that when physically bombarding the trench 20, fewer bombarding ions act on the side wall of the trench 20, making the influence of physical bombardment on the side wall of the trench 20 very small and basically negligible. The physical bombardment of the bombarding ions splashes some of the barrier layer material on the bottom wall of the trench 20 to the side wall of the trench 20 and the edge of the bottom wall of the trench 20, thickening the thickness of the side wall of the trench 20 near the bottom wall and the thickness at the edge of the bottom wall of the trench 20, and also thinning the thickness of the barrier layer 30 in most areas of the bottom wall of the trench 20; at the same time, due to the greater hardness of the barrier layer 30 than that of the dielectric layer and the porous structure characteristics of the dielectric layer 10, the physical bombardment of the bombarding ions can push the barrier layer 30 on the bottom wall of the trench 20 into the lower dielectric layer 10, deepening the depth of the trench 20. At this time, the depth of the trench 20 ≥ H1, and the depth of the deepest part of the trench 20 is H2, and H2 > H1. The depth of the metal material that can be filled later is deepened, increasing the cross-sectional area of the longitudinal section of the trench 20, so that the cross-sectional area through which the current can pass becomes larger, reducing the resistance value of the metal interconnect formed later and reducing the total resistance value of the wire formed later, achieving the purpose of reducing the wire resistance. In this step, during physical bombardment, since some of the barrier layer material splashes to the side wall of the trench 20 and the edge of the bottom wall of the trench 20, less of the edge of the bottom wall of the trench 20 is pushed downward, while most areas of the bottom wall of the trench 20 are significantly pushed downward, resulting in a stepped structure at the edge of the bottom wall of the trench 20.

[0043] In other embodiments, the bombarding ions can also be any other ions. The bombarding ions can include ions that react chemically with the barrier layer. These ions also play a role in physical bombardment when bombarding the bottom wall of the trench, forming a stepped bottom wall of the trench and deepening the depth of the trench.

[0044] Figure 3 This is the relationship diagram between the resistance value of the copper wire and the line width in this embodiment. As Figure 3 shown, h1, h2, and h3 in the figure are different trench depths respectively, and the value of h1 is the smallest and the value of h3 is the largest. Figure 3The x-axis in [description] is the width of the wire, which is the width of the trench, and the y-axis is the resistivity of the copper wire. It can be seen from Figure 3 that when the wire width is fixed, the resistivity of the copper wire with a deeper trench depth is lower, that is, the resistance value of the wire is the smallest. That is to say, the copper wire with a trench depth of h3 has the lowest resistivity and the smallest resistance value, while the copper wire with a trench depth of h1 has the highest resistivity and the largest resistance value. Therefore, after physically bombarding the barrier layer in the trench in this embodiment, the depth of the trench is increased, and the influence of the trench width in this process is very small and can be ignored. Therefore, the longitudinal section of the trench becomes larger and the resistance value of the copper wire becomes smaller. It should be noted that the width of the trench is Figure 2a the length of the trench from left to right in [description].

[0045] Figure 2d is a schematic structural diagram after filling the metal layer in this embodiment. Figure 2e is a schematic structural diagram after forming the metal layer in this embodiment. As Figures 2d - 2e shown, then step S40 is executed, and a metal material is filled in the trench 20 to form a metal interconnection line, and then a wire is formed.

[0046] This step specifically includes:

[0047] As Figure 2d shown, first, an electrochemical plating (ECP) process is used to fill the trench 20 with a metal material 40, and the metal material 40 is also formed on the dielectric layer 10 outside the trench 20. The metal material 40 can be copper.

[0048] As Figure 2e shown, then, through a chemical mechanical polishing process, the metal material 40 and the barrier layer 30 on the dielectric layer 10 outside the trench 20 are sequentially removed to form a metal interconnection line, thereby forming a wire. The metal interconnection line can be a metal interconnection line of any layer from the bottom metal interconnection layer to the top metal interconnection layer. By using the method of this embodiment to form each layer of metal interconnection line, the resistance value of the wire can be greatly reduced, and the response speed of the semiconductor device can be improved.

[0049] This embodiment also provides a wire, which includes at least one metal interconnection line prepared by the above method.

[0050] In summary, the present invention provides a wire and a method for forming the same. By adding a physical bombardment process to the barrier layer on the bottom wall of the trench between the two processes of forming the barrier layer in the trench and filling the trench with the metal material, the shape of the trench can be changed, and at the same time, the filling longitudinal section of the metal material can be increased, which can effectively reduce the resistance value of the wire. Specifically, the resistance value of the wire can be reduced by about 5%, the occurrence of the RC delay phenomenon is reduced, and the response speed of the wire is improved.

[0051] In addition, it should be noted that unless otherwise specified or indicated, the descriptions of terms such as "first", "second", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.

[0052] It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a wire, characterized in that, Including the following steps: Providing a semiconductor substrate, in which a dielectric layer is formed, and in which a trench is formed for forming a metal interconnect line; Forming a barrier layer on the bottom wall and side walls of the trench, the thickness of the barrier layer on the bottom wall of the trench being greater than the thickness of the barrier layer on the side walls of the trench; Physically bombarding the bottom wall of the trench to thin the thickness of the barrier layer in most areas at the bottom of the trench and deepen the depth of the trench, such that the edge of the bottom wall of the trench is stepped; And Filling the trench with a metal material to form a metal interconnect line, and further forming a wire; Wherein, during the physical bombardment, the gas introduced into the reaction chamber of the barrier layer includes argon, the flow rate of the introduced argon is 5 sccm to 30 sccm, and the AC power in the reaction chamber of the barrier layer is 200 W to 1500 W.

2. The method for forming a wire according to claim 1, characterized in that, Physically bombarding the bottom wall of the trench to deepen the depth of the trench includes: Physically bombarding the bottom wall of the trench in the reaction chamber for forming the barrier layer to deepen the depth of the trench, and also changing the shape of the trench.

3. The method for forming a wire according to claim 1, characterized in that, The method for forming the barrier layer includes: Sequentially forming a tantalum nitride layer and a tantalum layer on the outer side of the trench and on the inner wall of the trench through a deposition process.

4. The method for forming a wire according to claim 1, characterized in that, After filling the trench with the metal material, it further includes: Removing the metal material outside the trench and the barrier layer in sequence through a chemical mechanical polishing process.

5. The method for forming a wire according to claim 1, wherein The dielectric layer is a low-k dielectric layer.

6. The method for forming a wire according to claim 5, wherein The low-k dielectric layer is a porous structure.

7. A wire, characterized in that, Including at least one metal interconnect line prepared by the method for forming a wire according to any one of claims 1 to 6.

Images