Semiconductor memory device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device comprises: a semiconductor substrate; a word line structure located in the semiconductor substrate and extending in a first direction; a bit line structure located above the word line structure and extending in a second direction across the word line structure; a spacer structure located directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half and a lower half, the width of the upper half is greater than that of the lower half, and there is a gap inside the spacer structure; and a contact structure located in a space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate.

Description

[0001] This application is a divisional application of the original application number 202010368174.9, the application date April 30, 2020, and the invention name “Semiconductor memory device and its manufacturing method”. Technical Field

[0002] The embodiments disclosed in the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a spacer structure between memory cells and a method for manufacturing the same. Background Art

[0003] Semiconductor devices have been widely used in the electronics industry due to their small size, multi-functions and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logic data, semiconductor logic devices that process operations on logic data, and hybrid devices that have the functions of both memory devices and logic devices.

[0004] Some semiconductor devices may include vertically stacked layer structure patterns and contact plugs or interconnect structures that electrically connect the stacked patterns to each other. As semiconductor devices continue to shrink and increase in integration, the spacing between such patterns and / or the spacing between the patterns and the contact plugs is also continuously reduced. As a result, the parasitic capacitance between the patterns and / or between the patterns and the contact plugs increases, and the contact resistance between the patterns and the interconnect structures also increases, resulting in performance degradation of the semiconductor device, such as reduced operating speed. Summary of the invention

[0005] In view of the conventional problems encountered by the above-mentioned semiconductor devices, the present invention proposes a novel semiconductor memory device and a method for manufacturing the same, characterized in that the spacer structure between the memory cells has a special shape, which can increase the contact area between the memory cells and the active area to reduce the contact resistance, and the spacer structure has a cavity to reduce the parasitic capacitance.

[0006] One aspect of the present invention is to provide a semiconductor memory device, comprising a semiconductor substrate, a word line structure, which is located in the semiconductor substrate and extends in a first direction, a bit line structure, which is located above the word line structure and extends in a second direction across the word line structure, and a spacer structure, which is located directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half and a lower half, the width of the upper half is greater than that of the lower half, and the spacer structure has a gap inside, and a contact structure, which is located in the space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate.

[0007] Another aspect of the present invention is to provide a method for manufacturing a semiconductor memory device, comprising providing a semiconductor substrate, forming a word line structure extending in a first direction in the semiconductor substrate, forming a bit line structure extending in a second direction across the word line structure on the word line structure, forming a spacer structure directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half and a lower half, the upper half is wider than the lower half, and the spacer structure has a cavity inside, and forming a contact structure connected to the semiconductor substrate in the space defined by the bit line structure and the spacer structure.

[0008] These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is described in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This specification contains drawings and constitutes a part of this specification, so that the reader can further understand the embodiments of the present invention. These drawings depict some embodiments of the present invention and illustrate their principles together with the description herein. In these drawings:

[0010] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A as well as Fig. 6A depicts a plan view of a method of manufacturing a semiconductor memory device according to an example embodiment;

[0011] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B as well as Figure 6B Along Figures 1A to 6A A cross-sectional view taken along line Ⅰ-Ⅰ';

[0012] Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C as well as Figure 6C Along Figures 1A to 6A A cross-sectional view taken along line II-II';

[0013] Figures 7 to 11 A flowchart showing steps for making a spacer structure having a special cross-sectional shape according to an exemplary embodiment is depicted; and

[0014] Figures 12 to 16 Cross-sectional views of spacer structures having particular cross-sectional shapes according to other example embodiments are depicted.

[0015] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0016] The reference numerals are described as follows:

[0017] 1a, first doping region; 1b, second doping region; 100, semiconductor substrate; 101, device isolation layer; 103, gate insulating layer; 105, gate hard mask pattern; 107, insulating interlayer; 109, recessed region; 111, polysilicon pattern; 113, silicide pattern; 115, metal pattern; 117, hard mask pattern; 119, bit line contact pattern; 121, bit line contact spacer; 123, spacer wall; 125, insulating layer; 127, spacer pattern; 127a, upper half part; 127b, lower half part; 127c, third part; 129, sacrificial layer; 131, composite mask; 133, sacrificial pattern; 133a, upper half sacrificial pattern; 133b, lower half sacrificial pattern; 135, cavity; 137, organic dielectric layer; 139, sacrificial layer; 141, contact hole; 143, storage node contact; 145, outer layer; 147, inner layer; ACT, active area; D1, first direction; D2, second direction; D3, third direction; W1, W2, width; WL, word line. DETAILED DESCRIPTION

[0018] Now, the exemplary embodiments of the present invention will be described in detail below, and the features described will be indicated with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. The reader will understand that the description in the text is only carried out by way of example, and is not intended to limit the present case. The various embodiments of the present case and the various features that do not conflict with each other in the embodiments can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present case are understandable to those skilled in the art and are intended to be included in the scope of the present case.

[0019] Readers should be able to easily understand that the meanings of “on,” “over,” and “above” in this case should be interpreted in a broad manner, so that “on” not only means “directly on” something, but also includes the meaning of being “on” something with intervening features or layers, and “on” or “above” not only means “on” or “above” something, but also includes the meaning of being “on” or “above” something with no intervening features or layers (i.e., directly on something).

[0020] In addition, spatially related terms such as "under," "beneath," "lower," "over," "upper," and the like may be used herein for descriptive convenience to describe the relationship of one component or feature to another or more components or features, as shown in the accompanying drawings.

[0021] As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc.

[0022] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above, and / or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0023] In the illustrations in this manual, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A as well as Fig. 6A A plan view illustrating a method of manufacturing a semiconductor memory device according to an example embodiment of the present invention is shown. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B as well as Figure 6B Along the Figures 1A to 6A The cross-sectional view is taken along the line Ⅰ-Ⅰ', which cuts through the long axis of the entire active region. Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C as well as Figure 6C Along the Figures 1A to 6A The cross-sectional view is taken along line II-II', which cuts through a plurality of word lines and predetermined positions of memory cells. Figures 7 to 11 A flow chart showing steps for making a spacer structure with a special cross-sectional shape according to an example embodiment is shown. Figure 12 to Figure 14FIG. 4 is a cross-sectional view of a spacer structure having a special cross-sectional shape according to other example embodiments.

[0024] Please refer to Figure 1A , Figure 1B and Figure 1C . First, a semiconductor substrate 100 is provided, and a device isolation layer 101 defining an active area ACT is formed in the semiconductor substrate 100. The semiconductor substrate 100 may include a silicon substrate, a germanium substrate and / or a silicon germanium substrate. The device isolation layer 101 may be formed by performing a photolithography process on the semiconductor substrate 100 to form individually separated active areas ACT, and filling the grooves between the active areas ACT with isolation materials, such as silicon oxide and the like. In the example, the active area ACT has a strip shape in a plan view and has a long axis extending in a third direction D3. Multiple active areas ACT are uniformly arranged in a staggered manner on the plane.

[0025] Next, a plurality of word lines WL are formed in the semiconductor substrate 100, which extend in the first direction D1. The angle between the first direction D1 and the third direction D3 is preferably between 45 degrees and 90 degrees. In one example, the active area ACT and the device isolation layer 101 can be patterned by a photolithography process to form a gate recessed area 102 extending in the first direction D1, and a gate insulating layer 103 is formed in the gate recessed area 102. Afterwards, word lines WL located on the gate insulating layer 103 can be formed in the corresponding gate recessed areas 102. The material of the word line WL can be a metal, such as tungsten, aluminum, titanium and / or tantalum. The bottom surface of the gate recessed area 102 can be set to be higher than the bottom surface of the device isolation layer 101. The top surface of the word line WL can be set to be lower than the top surface of the device isolation layer 101. After the word lines WL are formed, a gate hard mask pattern 105 , such as a silicon nitride layer, is then formed in the remaining gate recess region 102 on the word lines WL.

[0026] After the gate hard mask pattern 105 is formed, a first doped region 1a and a second doped region 1b may be formed in the active region ACT on both sides of the word line WL, respectively, which may be formed by an ion implantation process and may include a dopant of a conductivity type opposite to that of the active region ACT. The bottom surfaces of the first doped region 1a and the second doped region 1b may be positioned at a predetermined depth below the top surface of the active region ACT. The first doped region 1a is located in the middle of the active region ACT, which will then be electrically connected to the bit line. The second doped region 1b is located at both ends of the active region ACT, which will then be electrically connected to the storage node contact. In addition, an insulating interlayer 107 may be formed on the surface of the semiconductor substrate 100 to isolate the active region ACT below from the components above. The insulating interlayer 107 may be formed by a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, a silicon nitride layer and / or a silicon nitride oxide layer.

[0027] According to one example, the semiconductor substrate 100 and the insulating interlayer 107 can be patterned via a photolithography process to form a recessed region 109 that exposes the first doped region 1a. In one example, the shape of the recessed region 109 can be elliptical. In addition, the recessed regions 109 can be uniformly arranged in a staggered manner on a plane. In some embodiments, the recessed regions 109 can be formed by an anisotropic etching process. In this case, a portion of the device isolation layer 101 and a portion of the gate hard mask pattern 105 adjacent to the first doped region 1a are etched together. The bottom surface of the recessed region 109 can be higher than the bottom surface of the first doped region 1a (as shown by the dotted line), and a portion of the device isolation layer 101 and a portion of the gate hard mask pattern 105 can be exposed from the recessed region 109.

[0028] Please refer to Figure 2A , 2B and 2C. After defining the active area ACT and forming structures such as the word line WL and the insulating interlayer 107, a bit line structure BLS extending in the second direction D2 is then formed on the semiconductor substrate 100. The angle between the second direction D2 and the third direction D3 is preferably between 0 and 45 degrees, and the second direction D2 is preferably orthogonal to the first direction D1. The steps of forming the bit line structure BLS may include: sequentially forming a polysilicon layer, a silicide layer, a metal layer, and a hard mask layer on the semiconductor substrate 100, wherein the polysilicon layer fills the recessed area 109, and then using the bit line mask pattern as an etching mask to sequentially etch the hard mask layer, the metal layer, the silicide layer, and the polysilicon layer, thereby forming a structure such as Figure 2B The bit line structure BLS shown in the figure. The bit line mask pattern can be removed after the etching process. In the example, the polysilicon layer can be a doped polysilicon layer, and the metal layer can be a tungsten layer, an aluminum layer, a titanium layer or a tantalum layer, etc. In this way, each bit line structure BLS includes a stacked polysilicon pattern 111, a silicide pattern 113, a metal pattern 115 and a hard mask pattern 117 in sequence from bottom to top. Among them, a portion of the polysilicon pattern 111 will be formed in the recessed area 109 as a bit line contact pattern 119 that directly contacts the first impurity region 1a. In addition, the minimum width of the recessed area 109 can be greater than the width of each bit line structure BLS. The sidewalls of the polysilicon pattern 111 of the bit line structure BLS can be separated from the sidewalls of the corresponding recessed area 109.

[0029] Please refer to Figure 3A , 3Band 3C. After the bit line structure BLS is formed, an insulating structure is then formed on the sidewall of each bit line structure BLS to prevent the bit line structure BLS from being electrically connected to surrounding components. Among them, the insulating structure may include two parts, namely, a lower half formed in the recessed area 109 and an upper half covering the sidewall of the bit line structure BLS. More specifically, in one example, the step of forming the insulating structure may include depositing an insulating stack that fills the recessed area 109 and conformally covers the bit line structure BLS. The insulating stack may include a first nitride layer, an oxide layer, and a second nitride layer stacked in sequence. When the insulating stack is anisotropically etched, the middle oxide layer may serve as an etch stop layer, so that the oxide layer and the second nitride layer may be partially retained in the recessed area 109 to form a bit line contact spacer 121. The bit line contact spacer 121 may be formed of an insulating material having an etching selectivity relative to the insulating interlayer 107. For example, the bit line contact spacer 121 may include a silicon oxide layer, a silicon nitride layer and / or a silicon oxynitride layer. For the upper portion of the insulating structure, a spacer 123 may be formed on the sidewall of the bit line structure BLS, and an insulating layer 125 may be conformally formed on the spacer 123 and the insulating interlayer 107. The spacer 123 may be formed by depositing a spacer layer and performing anisotropic etching, and similarly, its material has an etching selectivity relative to the insulating structure located in the recessed area 109, such as silicon oxide. The material of the insulating layer 125 has an etching selectivity relative to both the spacer 123 and the insulating interlayer 107, such as a silicon nitride layer and / or a silicon oxynitride layer.

[0030] Please refer to Figure 4A , 4B After the insulating layer 125 and the bit line contact spacer 121 are formed, a spacer structure is then fabricated to define a memory cell region between the bit line BLS and the word line WL. Figure 4AAs shown, a plurality of spacer structures 127 are formed in the space between the bit lines BLS and the bit lines BLS. In the example, the spacer structure 127 is located directly above the word line WL and also extends in the first direction D1, and the spacer structure 127 contacts the insulating layer 125 on the sidewall of the bit line BLS, so that the spacer structure 127 and the bit line BLS are spaced together and define a plurality of spaces located on the insulating layer 125, each of which corresponds to a memory cell region and is located above the second doped region 1b of the active region ACT, and a storage node contact is predetermined to be formed in the space. In one example, more particularly, the spacer structure 127 has a special cross-sectional shape. As shown in the figure, in the present invention, the spacer structure 127 has a distinctive upper half 127a and a lower half 127b, and its characteristic is that the width of the upper half 127a of the spacer structure 127 is greater than the width of the lower half 127b, and its width is gradually reduced from the surface of the sacrificial layer 129 to the insulating layer 125. Furthermore, the cross-sectional curves of the upper half 127 a and the lower half 127 b of the spacer structure 127 are not smooth curves, but are discontinuous at the intersection of the two halves, so that the upper and lower halves can be clearly distinguished.

[0031] The special cross-sectional shape of the spacer structure 127 can be achieved by adjusting the parameters of the etching process. Figures 7 to 11 As shown, the steps of making the spacer structure 127 are shown: (1) First, as Figure 7 As shown, a sacrificial layer 129 is formed on the insulating layer 125, and a composite mask 131 having a spacer structure pattern is formed on the sacrificial layer 129, wherein the sacrificial layer 129 may be formed using a spin-on hard mask (SOH) material, such as SOH silicon oxide, and the composite mask 131 may include an organic dielectric layer (ODL), an anti-reflective layer (ARC), and a photoresist layer (PR) in order from bottom to top, wherein the spacer structure pattern has been defined in the photoresist layer;

[0032] (2) Then, Figure 8 As shown, with the composite mask 131 and the bit line structure BLS ( Figure 4B ) is an etching mask to perform a first etching process to etch the sacrificial layer 129 to form an upper sacrificial pattern 133a in the sacrificial layer 129, wherein the upper sacrificial pattern 133a is the pattern of the upper half portion 127a of the aforementioned spacer structure;

[0033] (3) Then, Fig. 9As shown, the etching parameters are adjusted, for example, the etching gas and / or parameters are adjusted to have a stronger anisotropic property, and then a second etching process is performed to form a lower sacrificial pattern 133b in the sacrificial layer 129. The lower sacrificial pattern 133b is the pattern of the lower half portion 127b of the aforementioned spacer structure, and the upper sacrificial pattern 133a and the lower sacrificial pattern 133b together constitute the sacrificial pattern 133. Since the lower sacrificial pattern 133b is formed by etching with a stronger anisotropic etching process after the upper sacrificial pattern 133a is formed, the width of the lower sacrificial pattern 133b formed in this way will be smaller than that of the upper sacrificial pattern 133a, and the intersection of the two will have a discontinuous state;

[0034] (4) Then, Fig.10 As shown, the composite mask 131 is removed, and a spacer material is filled into the sacrificial pattern 133, thereby forming a spacer structure 127. At this time, a void 135 may be formed inside the spacer structure 127, especially in the lower half 127b of the spacer structure 127. The presence of this void 135 can increase the insulation of the spacer structure 127, thereby reducing the overall parasitic capacitance of the device. The void 135 can be achieved by using a spacer material with poor hole filling properties. For example, the spacer structure 127 can be formed of an insulating material having an etching selectivity relative to the sacrificial layer 129. For example, the spacer structure 127 can be formed of silicon nitride, and the sacrificial layer 129 can be formed of silicon oxide or silicon oxynitride. Afterwards, another organic dielectric layer 137 is formed on the spacer material to provide a flat surface for the subsequent back etching process;

[0035] (5) Finally, Fig.11 As shown, an etching process is performed to remove the organic dielectric layer 137 and the spacer material on the surface of the sacrificial layer 129 , so that the individual spacer structures 127 can be separated, and the manufacturing of the spacer structure 127 is completed.

[0036] The spacer structure with a special cross-sectional shape in this case can also have other variations. Fig.12 As shown, another sacrificial layer 139 may be formed on the surface of the sacrificial layer 129, and the third portion 127c of the top of the spacer structure 127 may be formed therein, wherein the width of the third portion 127c is smaller than the width of the lower upper portion 127a. The lateral etching rate of the sacrificial layer 139 material is preferably lower than the lateral etching rate of the sacrificial layer 129 material, so that during the process of forming the sacrificial pattern by the etching process, the sacrificial layer 139 has a lower lateral etching rate, so its width will be smaller than the width of the lower upper portion 127a formed.

[0037] In addition, if Fig.13As shown, without forming an additional sacrificial layer, the spacer structure 127 can be formed with different widths by adjusting the etching gas and / or parameters in different stages of the same etching process. For example, at the beginning of the process, a stronger anisotropic etching gas and / or parameter setting is used to form the third portion 127c, and then the etching gas and / or parameter is adjusted to have a stronger isotropic property to form the upper portion 127a, so that the portion has a larger width, and finally the etching gas and / or parameter is adjusted back to the original stronger anisotropic setting to form the lower portion 127b.

[0038] In other examples, such as Fig.14 As shown, the spacer structure 127 can also be made to have a cavity 135 in both the upper part 127a and the lower part 127b, and the method is also through using a spacer material with poor hole filling efficiency. In this way, almost the entire spacer structure 127 has a cavity, which can further reduce parasitic capacitance.

[0039] In other examples, such as Fig.15 As shown, the spacer structure 127 can also be made into a double-layer structure, such as an outer layer 145 located on the sidewall of the spacer structure 127 and an inner layer 147 filling the inside. In one example, the outer layer structure can be Fig. 9 The sacrificial pattern 133 is formed by removing the composite mask 131 and then forming a conformal layer on the pattern surface and etching back. Fig.16 As shown, the outer layer 145 may also be selected in Figure 5B The step is formed after the contact hole 141 is formed and before the storage node contact 143 is formed. The method is to form a conformal outer layer 145 on the surface of the contact hole 141, and then etch back the bottom surface of the outer layer 145 to expose the active region (the second doped region 1b), so that the outer layer 145 is only formed on the sidewall of the spacer structure 127. The material of the outer layer 145 and the inner layer 147 of the spacer structure 127 can be formed of an insulating material having an etching selectivity relative to the sacrificial layer 129. For example, the material of the outer layer of the spacer structure 127 can be formed of silicon oxynitride, the material of the inner layer 147 can be formed of silicon nitride, and the sacrificial layer 129 can be formed of silicon oxide.

[0040] Please refer to the following Figure 5A , 5Band 5C. After the spacer structure 127 is formed, the sacrificial layer 129 can be removed by using an etching recipe with etching selectivity relative to the spacer structure 127 and the insulating layer 125, so that a contact area for the storage node to land between the bit line structure BLS and the spacer structure 127 can be defined. However, since the active area (the second doped region 1b) below the contact area is still covered with the insulating interlayer 107 and the insulating layer 125, the insulating interlayer 107 and the insulating layer 125 must be removed to expose the active area. Therefore, the spacer structure 127 and the bit line structure BLS can be used as an etching mask to perform anisotropic etching to remove the exposed insulating interlayer 107 and the insulating layer 125, so as to form a contact hole 141. This anisotropic etching will also remove part of the second impurity region 1b, the gate hard mask pattern 105 and the device isolation layer 101, so that the bottom surface of the contact hole 141 can be lower than the top surface of the semiconductor substrate 100.

[0041] from Figure 5B and Figure 5C As can be seen in the figure, since in the present invention, the spacer structure 127 has a cross-sectional shape that is wide at the top and narrow at the bottom, the contact hole 141 separated by it will have a corresponding cross-sectional shape that is narrow at the top and wide at the bottom, as shown in the figure, where W1 is larger than W2. The advantage of this feature is that the width of the contact member subsequently formed in the contact hole 141 will be larger than that of the contact member generally formed by the known technology, which can effectively reduce the contact resistance between the storage node and the connected active area, thereby improving the performance of the device. Similarly, in Fig.12 and Fig.13 In the variant embodiment, the feature of the spacer structure 127 having a narrower third portion 127c can also increase the contact area with the upper component, such as a capacitor, thereby reducing its contact resistance and improving the performance of the device.

[0042] Please refer to Fig. 6A , 6B and 6C. After the contact holes 141 are formed, storage node contacts 143 are then formed in the contact holes 141, respectively. In one example, the top surface of the storage node contact 143 may be lower than the top surface of the hard mask pattern 117 of the bit line structure BLS. The storage node contact 143 may be formed by the following process: depositing a conductive layer to fill the contact hole 141, performing a planarization process to remove the conductive layer located above the top surface of the bit line structure BLS and the spacer structure 127, and performing a back etching process to recess the top surface of the conductive layer, thereby forming the storage node contact 143. The storage node contact 143 may include, for example, a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, and / or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), and / or a metal-semiconductor alloy (e.g., metal silicide).

[0043] In some other embodiments, the storage node contact 143 may include a polysilicon layer, a metal silicide layer, and a landing pad in order from bottom to top, and each corresponding capacitor may be connected thereto to serve as a storage node. Since the above-mentioned parts are not the focus of the present invention, in order to avoid blurring the focus of the invention, the detailed description of these parts will be omitted in this article.

[0044] According to the above-mentioned embodiments, the present invention proposes a novel semiconductor memory device, which includes a semiconductor substrate, a word line structure located in the semiconductor substrate and extending in a first direction, a bit line structure located above the word line structure and extending in a second direction across the word line structure, and a spacer structure located directly above the word line structure and between the bit line structures. The semiconductor memory device is characterized in that the spacer structure has an upper half and a lower half, the width of the upper half is greater than that of the lower half, and the spacer structure has a gap inside, and a contact structure located in the space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, include: a semiconductor substrate; A word line structure, located in the semiconductor substrate and extending in a first direction; A bit line structure, located above the word line structure and extending in a second direction across the word line structure; a spacer structure located directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half and a lower half, the width of the upper half is greater than the width of the lower half, the spacer structure has an outer layer and an inner layer, the bottom of the outer layer is lower than the bottom of the inner layer; as well as a storage node contact, located in a space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate, The bit line structure includes a stacked polysilicon pattern, a metal pattern and a hard mask pattern in sequence from bottom to top. The cross-sectional curves of the upper half and the lower half of the spacer structure are non-smooth. 2 . The semiconductor memory device according to claim 1 , wherein a width of the spacer structure tapers from top to bottom.

3. The semiconductor memory device according to claim 1, wherein both the upper half and the lower half of the spacer structure have cavities therein.

4. The semiconductor memory device as claimed in claim 1, wherein the spacer structure further comprises a third portion located on the upper half portion, and a width of the third portion is smaller than a width of the upper half portion.

5. The semiconductor memory device as claimed in claim 1, wherein an insulating layer is further provided between the spacer structure and the bit line structure. 6 . The semiconductor memory device as claimed in claim 5 , wherein a gate hard shield layer and the insulating layer are further provided between the spacer structure and the word line.

7. The semiconductor memory device according to claim 1, wherein the material of the outer layer is silicon oxynitride, and the material of the inner layer is silicon nitride.

8. The semiconductor memory device according to claim 1, wherein the outer layer covers at least a side wall of the inner layer.

9. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a gate hard mask pattern, the gate hard mask pattern being located on a side of the word line structure close to the spacer structure, and the bottom of the outer layer being lower than the top of the gate hard mask pattern. 10 . The semiconductor memory device of claim 9 , wherein a bottommost portion of the outer layer is in complete physical contact with the gate hard mask pattern.

11. The semiconductor memory device of claim 1 , wherein the semiconductor memory device further comprises a gate hard mask pattern, wherein the gate hard mask pattern is located on a side of the word line structure close to the spacer structure, and a width of a bottom portion of the spacer structure is smaller than a width of an upper surface of the gate hard mask pattern.

12. A method for manufacturing a semiconductor memory device, include: Providing a semiconductor substrate; forming a word line structure extending in a first direction in the semiconductor substrate; forming a bit line structure on the word line structure and extending in a second direction across the word line structure; A spacer structure is formed directly above the word line structure and between the bit line structures, wherein the spacer structure has an upper half and a lower half, the width of the upper half is greater than the width of the lower half, the spacer structure has an outer layer and an inner layer, and the bottom of the outer layer is lower than the bottom of the inner layer; as well as forming a storage node contact connected to the semiconductor substrate in a space defined by the bit line structure and the spacer structure, The bit line structure includes a stacked polysilicon pattern, a metal pattern and a hard mask pattern in sequence from bottom to top. The cross-sectional curves of the upper half and the lower half of the spacer structure are non-smooth.

13. The method for manufacturing a semiconductor memory device according to claim 12, wherein the step of forming the spacer structure comprises: forming a sacrificial layer on the semiconductor substrate, wherein the sacrificial layer is located between adjacent bit line structures; Performing a first photolithography process to define a pattern of the spacer structure in the sacrificial layer; and The spacer structure is formed by filling a spacer material into the pattern of the spacer structure.

14. A method for manufacturing a semiconductor memory device as described in claim 13, wherein the first photolithography process further includes first performing a first etching step to form a pattern of the upper half of the spacer structure in the sacrificial layer, and then performing a second etching step to form a pattern of the lower half of the spacer structure in the sacrificial layer, wherein the anisotropy of the second etching step is greater than the anisotropy of the first etching step.

15. The method for manufacturing a semiconductor memory device as described in claim 13 further includes forming a second sacrificial layer on the sacrificial layer and performing a second photolithography process, wherein the second photolithography process etches the second sacrificial layer to form a third portion of the spacer structure, wherein the lateral etching rate of the second sacrificial layer is less than the lateral etching rate of the sacrificial layer, so that the width of the third portion of the spacer structure is less than the width of the upper half portion.

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