Three-dimensional memory and methods of making the same, memory systems

Abstract

The disclosure provides a three-dimensional memory and a manufacturing method thereof, and a storage system, and relates to the technical field of semiconductor chips, and aims to reduce the process difficulty of forming a channel hole with a large depth-width ratio. The manufacturing method of the three-dimensional memory comprises the following steps: forming an initial stack structure on a substrate, wherein the initial stack structure comprises alternately stacked sacrificial layers and first dielectric layers; forming an opening penetrating through the initial stack structure; removing, in a direction parallel to the substrate, a portion of the sacrificial layers close to the opening to form a first recess; forming a material layer on the inner wall of the opening with the first recess, wherein the surface of the material layer has a second recess located in the first recess; forming a protection portion in the second recess, wherein the first portion of the material layer is shielded by the protection portion, and the remaining portion is a second portion; modifying the second portion of the material layer; and removing the protection portion and the first portion of the material layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and its fabrication method and storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate. In 3D NAND, the memory cells are arranged in three dimensions, forming an array of memory cell strings.

[0004] To further increase the storage density of 3D NAND, more memory cell strings can be formed on a surface of a certain area. For example, the size of the channel structure in the memory cell string can be reduced. To reduce the size of the channel structure, the size of the vias containing the channel structure can be reduced. This increases the aspect ratio of the vias. However, high aspect ratio etching processes are more difficult to execute, and the resulting via morphology has many defects, such as warpage, striations, and uneven via size, which affect the performance of 3D NAND. Summary of the Invention

[0005] The embodiments of this disclosure provide a three-dimensional memory and a method for fabricating the same, as well as a storage system, which aim to reduce the difficulty of forming channel holes with a large aspect ratio.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a method for fabricating a three-dimensional memory is provided. The method includes: forming an initial stacked structure on a substrate, the initial stacked structure including alternating sacrificial layers and a first dielectric layer; forming an opening penetrating the initial stacked structure; removing a portion of the sacrificial layer near the opening along a direction parallel to the substrate to form a first recess; forming a material layer on the inner wall of the opening having the first recess, the surface of the material layer having a second recess located within the first recess; forming a protective portion in the second recess, the portion of the material layer obscured by the protective portion being a first portion, and the remaining portion being a second portion; modifying the second portion of the material layer; and removing the protective portion and the first portion of the material layer.

[0008] In some embodiments, the protective portion includes a first end and a second end, and along a direction parallel to the substrate, the second end is farther away from the sacrificial layer than the first end.

[0009] In some embodiments, the dimension of the second end along the direction perpendicular to the substrate is greater than or approximately equal to the thickness of the sacrificial layer.

[0010] In some embodiments, the method for fabricating a three-dimensional memory further includes: before the step of forming a material layer, trimming the sidewalls of the first recess such that the portion of the sidewall of the first recess away from the sacrificial layer is arc-shaped, and the sidewalls of the first recess are formed by the first dielectric layer. The portion of the sidewall of the second recess away from the sacrificial layer is arc-shaped, and the protective portion contacts the arc-shaped portion of the sidewall of the second recess.

[0011] In some embodiments, the depth of the first recess is greater than the thickness of the material layer.

[0012] In some embodiments, forming a protective portion in the second recess includes: forming a mask layer on a material layer, the mask layer filling the second recess; and removing a portion of the mask layer to form the protective portion.

[0013] In some embodiments, modifying the second portion of the material layer includes oxidizing the second portion of the material layer.

[0014] In some embodiments, the material layer is made of polycrystalline silicon or silicon nitride.

[0015] In some embodiments, the opening having the first recess extends into the substrate, and the material layer also covers the surface of the substrate exposed by the opening having the first recess.

[0016] In some embodiments, the method of fabricating a three-dimensional memory further includes: forming a filling portion in a third recess, the third recess being formed by removing a protective portion and a first portion of the material layer.

[0017] In some embodiments, the material of the filler portion is the same as the material of the sacrificial layer.

[0018] In some embodiments, forming a filling portion in the third recess includes: forming a second dielectric layer on the inner wall of the opening having the third recess, the second dielectric layer filling the third recess; and removing a portion of the second dielectric layer to form the filling portion.

[0019] In some embodiments, the method of fabricating a three-dimensional memory further includes forming a semiconductor channel in the opening after removing a first portion of the protective portion and the material layer.

[0020] On the other hand, a three-dimensional memory is provided. The three-dimensional memory includes a stacked structure and a channel structure. The channel structure includes alternately stacked gate layers and a third dielectric layer. The channel structure extends through the stacked structure. The third dielectric layer includes a first dielectric layer and an extension portion, the extension portion being disposed between the first dielectric layer and the channel structure.

[0021] In some embodiments, the size of the expansion portion is smaller than or larger than the thickness of the first dielectric layer in the thickness direction of the three-dimensional memory.

[0022] In some embodiments, the side of the third dielectric layer that contacts the channel structure is substantially flush with the side of the gate layer that contacts the channel structure, or the side of the third dielectric layer that contacts the channel structure protrudes beyond the side of the gate layer that contacts the channel structure.

[0023] In some embodiments, in the third dielectric layer, the first dielectric layer and the expansion portion are made of the same material, or the material of the expansion portion contains more elements than the material of the first dielectric layer.

[0024] In some embodiments, the material of the first dielectric layer includes silicon oxide. The material of the extension includes at least one of silicon oxide or silicon oxynitride.

[0025] In another aspect, a storage system is provided. The storage system includes a controller and a three-dimensional memory as described in some of the embodiments above, the controller being coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0026] In the method for fabricating a three-dimensional memory provided in the embodiments of this disclosure, an opening penetrating the initial stacked structure (hereinafter referred to as the initial opening) is first formed in the initial stacked structure. Then, subsequent steps are performed to retain a second portion of the modified material layer within the initial opening. Thus, in the opening formed by this fabrication method (which can be referred to as the final opening, such as a channel via), the size of the second portion containing the material layer can be smaller than the size of the initial opening. That is, by performing this fabrication method, the size of at least a portion of the initial opening can be reduced, making the size of at least a portion of the final opening smaller. Furthermore, in the method for fabricating a three-dimensional memory provided in the embodiments of this disclosure, a first portion of the material layer can be removed, allowing the subsequently formed gate layer to be coupled to a semiconductor channel disposed in the final opening to form a memory cell transistor. Based on the above, when fabricating a three-dimensional memory, an initial opening with a small aspect ratio can be formed first, and then, by performing the above fabrication method, a final opening with a smaller size (larger aspect ratio) can be formed. This final opening can serve as a channel via, thereby reducing the technological difficulty of forming a channel via with a large aspect ratio.

[0027] It is understood that the three-dimensional memory provided in the above embodiments of this disclosure can be manufactured by the above-described three-dimensional memory manufacturing method. The storage system provided in the above embodiments of this disclosure includes the above-described three-dimensional memory, and the beneficial effects it can achieve can be referred to the beneficial effects of the three-dimensional memory manufacturing method described above, which will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments;

[0030] Figure 2 for Figure 1 The equivalent circuit diagram of the three-dimensional memory in the image;

[0031] Figure 3 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line AA;

[0032] Figure 4 for Figure 1 A top view of the multiple channel structures in the three-dimensional memory shown;

[0033] Figure 5 for Figure 4 A magnified view of two adjacent channel structures in the middle position;

[0034] Figure 6 A flowchart illustrating a method for fabricating a three-dimensional memory according to some embodiments;

[0035] Figures 7A to 7M A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0036] Figure 8 for Figure 7C A magnified view of region A in the initial stacked structure;

[0037] Figure 9 for Figure 7D A magnified view of region B in the initial stacked structure;

[0038] Figure 10A for Figure 7EA magnified view of region C in the initial stacked structure;

[0039] Figure 10B for Figure 7E A magnified view of region C in the initial stacked structure;

[0040] Figure 11A A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0041] Figure 11B for Figure 11A A magnified view of region D of the initial stacked structure;

[0042] Figure 11C This is a structural diagram of the second recess in a method for manufacturing a three-dimensional memory according to some embodiments;

[0043] Figure 12A A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0044] Figure 12B A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0045] Figure 13A A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0046] Figure 13B A process flow diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0047] Figure 14 This is a structural diagram of a three-dimensional memory according to some embodiments;

[0048] Figure 15A for Figure 14 A magnified view of region E in the three-dimensional memory;

[0049] Figure 15B for Figure 14 A magnified view of region E in the three-dimensional memory;

[0050] Figure 15C for Figure 14 A magnified view of region E in the three-dimensional memory;

[0051] Figure 16 This is a structural diagram of a three-dimensional memory according to some embodiments;

[0052] Figure 17 This is a structural diagram of a three-dimensional memory according to some embodiments;

[0053] Figure 18 This is a block diagram of a storage system according to some embodiments;

[0054] Figure 19 This is a block diagram of a storage system according to some embodiments. Detailed Implementation

[0055] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0056] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0057] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0058] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0059] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0060] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0061] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0062] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0063] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0064] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0065] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0066] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0067] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0068] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on a surface (e.g., the surface of a substrate) and extending in a direction perpendicular to that surface. As used herein, the term "perpendicularly" means nominally perpendicular to the surface.

[0069] Embodiments of this disclosure provide a three-dimensional memory. Figure 1 This is a three-dimensional structural diagram of a three-dimensional memory. Figure 2 for Figure 1 The equivalent circuit diagram of the three-dimensional memory in the image. Figure 3 for Figure 1 A cross-sectional view of a storage cell string in a three-dimensional memory along section line AA'.

[0070] See Figure 1 The three-dimensional memory 1 includes a stacked structure 100. The stacked structure 100 includes alternating gate layers G and a third dielectric layer ( Figure 1 (Not shown in the diagram, but will be described below). The gate layer G and the third dielectric layer extend along the first direction X. The stacked structure 100 may have a stepped morphology.

[0071] The three-dimensional memory 1 also includes at least one (e.g., one; or more) channel structure 200 that runs through each gate layer G along the thickness direction of the three-dimensional memory 1 (e.g., parallel to the third direction Z). A channel structure 200 can connect the gate layers G in series to form a memory cell string NS.

[0072] The three-dimensional memory 1 may also include a source terminal SL. The source terminal SL may be coupled to one or more channel structures 200.

[0073] The three-dimensional memory 1 may also include an array interconnect layer 11. The array interconnect layer 11 may include at least one (e.g., one; or more) bit lines BL, each bit line BL being coupled to one or more memory cell strings NS.

[0074] See Figures 1-3 A storage cell string NS (e.g., each storage cell string NS) may include multiple storage cell transistors MC (referred to as storage cells MC in this document), such as storage cells MC1 to MC4. Multiple storage cells MC can be connected in series. Storage cells MC can be configured to store data.

[0075] In some embodiments, the memory cell string NS may further include at least one (e.g., one; or more) string select transistors SST and at least one (e.g., one; or more) ground select transistors GST located on both sides of the interconnected memory cells MC. The at least one string select transistor SST and the at least one ground select transistor GST may be connected in series with the respective memory cells MC. Furthermore, one terminal (e.g., the drain) of a string select transistor SST may be coupled to the bit line BL, and one terminal (e.g., the source) of a ground select transistor GST may be coupled to the source terminal SL.

[0076] Accordingly, in the stacked structure 100, along the third direction Z, the bottommost gate layer G (e.g., closest to the source terminal SL) of the multilayer gate layer G can be configured as a source select gate SGS, and a source select gate SGS can be configured as the gate of one or more ground select transistors GST. The topmost gate layer G (e.g., furthest from the source terminal SL) of the multilayer gate layer G can be configured as a drain select gate SGD, and a drain select gate SGD can be configured as the gate of one or more string select transistors SST. The gate layer G located in the middle layer of the multilayer gate layer G can be configured as multiple word lines WL (e.g., including word lines WL0 to WL4), and a word line WL can be configured as the gate of a memory cell transistor MC.

[0077] In some embodiments, the three-dimensional memory 10 may include a plurality of memory cell strings NS, which may be arrayed in an XY plane (e.g., a plane defined by a first direction X and a second direction Y). Correspondingly, the channel structures 200 of the plurality of memory cell strings NS may also be arrayed in the XY plane. Exemplarily, Figure 4 This is a top view of multiple strings of memory cells in a three-dimensional memory, showing multiple channel structures. It should be noted that... Figure 4 The specific structure of the channel is omitted. See also Figure 4Multiple channel structures 200 are arranged in multiple channel rows distributed sequentially along the second direction Y. The channel structures 200 located in the odd-numbered channel rows can be arranged in an array, and the channel structures 200 located in the even-numbered channel rows can be arranged in an array. Furthermore, the channel structures 200 in two adjacent channel rows can be staggered. In this way, multiple channel structures 200 (or memory cell strings) can form an interleaved columnar array.

[0078] See also Figures 1-3 To achieve higher storage density, the number of storage cells MC in a storage cell string NS can be increased. For example, the number of stacked layers in the stacked structure of the three-dimensional memory 10 can be increased, and the number of gate layers G can be increased, thereby increasing the number of storage cells MC in a storage cell string NS.

[0079] However, in the fabrication process of the 3D memory 10, it is necessary to first form channel holes extending along the thickness direction of the 3D memory 10, for example, through an etching process. Then, a channel structure is formed within the channel holes. As the number of stacked layers in the 3D memory increases, the aspect ratio of the channel holes will increase. High aspect ratio etching processes are technically challenging, and the resulting channel hole morphology also exhibits numerous defects, such as warpage, striations, and uneven channel hole dimensions.

[0080] See Figure 4 To achieve higher storage density, more channel structures 200 can be formed on a given area of ​​the XY plane. For example, the size of the channel structure 200 can be reduced, and the distance between two adjacent channel structures 200 can be decreased. Correspondingly, in the semiconductor structure fabrication process, the size of the channel via CH can be reduced, and the distance between two adjacent channel via CH can be decreased; in other words, the minimum distance between the edges of two adjacent channel via CH can be reduced.

[0081] For example, see Figure 5 , Figure 5 for Figure 4A magnified view of two adjacent channel structures. The dimensions of a channel hole CH can be characterized by its critical dimension (CD). The critical dimension CD of a channel hole CH can be the average diameter of the channel hole CH. Furthermore, the distance between two adjacent channel holes CH can be the distance P (pitch) between the centers (e.g., the center of a circle) of these two channel holes CH. When the critical dimensions CD of all channel holes CH are approximately equal, the minimum distance SP (called channel hole space, CH space) between the edges of two adjacent channel holes CH can be equal to the difference between the distance P between the centers of these two channel holes CH and the critical dimension CD of one channel hole CH.

[0082] Based on the above, when the critical dimension CD of the channel hole CH decreases, the aspect ratio of the channel hole CH also increases accordingly. High aspect ratio etching processes are more difficult to execute, and forming smaller channel holes CH through deep-hole etching is quite challenging.

[0083] Furthermore, in the fabrication process of 3D memory, an initial stacked structure can be formed first, comprising alternating sacrificial layers and a first dielectric layer. Channel vias (CH) and channel structures 200 can be formed in the initial stacked structure. Subsequently, the sacrificial layers can be removed, and a gate layer can be formed in the sacrificial gap formed after the removal of the sacrificial layers. When the minimum distance SP between the edges of two adjacent channel vias (CH) decreases, the process difficulty of removing the sacrificial layer material between the two channel vias (CH) also increases accordingly. Moreover, after removing the sacrificial layer material between the two channel vias (CH), since the minimum distance SP between the edges of the two adjacent channel vias (CH) is small, the process difficulty of filling the gate layer material within this small distance is also greater, and the resistance of the gate layer filled within this small distance is larger, thus affecting the electrical performance of the gate layer and consequently affecting the electrical properties of the 3D memory.

[0084] To address the aforementioned problems, some embodiments of this disclosure provide a method for fabricating a three-dimensional memory. This method allows for the fabrication of the three-dimensional memory as described in any of the above embodiments.

[0085] Figure 6 This is a flowchart illustrating a method for fabricating a three-dimensional memory in some embodiments. Figures 7A-7J This is a process flow diagram of the fabrication method of the three-dimensional memory in some embodiments.

[0086] See Figure 6 and Figures 7A-7J The method for fabricating a three-dimensional memory includes the following steps:

[0087] S1. An initial stacked structure is formed on the substrate, the initial stacked structure comprising alternating sacrificial layers and a first dielectric layer.

[0088] See Figure 7A The substrate S may be made of one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The substrate S may also be made of a non-conductive material such as glass, plastic, or sapphire wafer. In some embodiments, the substrate S is made of monocrystalline silicon.

[0089] The initial stacked structure 300 may include at least one (e.g., one; or multiple) sacrificial layer 310 and at least one (e.g., one; or multiple) first dielectric layer 320. Furthermore, the sacrificial layers 310 and the first dielectric layers 320 are stacked alternately. Exemplarily, in the thickness direction of the initial stacked structure 300 (e.g., parallel to the third direction Z), a first dielectric layer 320 is disposed between two adjacent sacrificial layers 310, and a sacrificial layer 310 is disposed between two adjacent first dielectric layers 320.

[0090] The material of the sacrificial layer 310 may be one or a combination of silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments, the material of the sacrificial layer 310 is silicon nitride.

[0091] The material of the first dielectric layer 320 may be one or a combination of silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments, the material of the first dielectric layer 320 is silicon oxide.

[0092] The materials of the sacrificial layer 310 and the first dielectric layer 320 can be used in combination. For example, in the fabrication process of a three-dimensional memory, the sacrificial layer 310 can be removed by an etching process while retaining the first dielectric layer 320, so that a gate layer can be subsequently formed in the void created by removing the sacrificial layer 310. In the above etching process, the etching selectivity ratio between the materials of the sacrificial layer 310 and the first dielectric layer 320 can be relatively large. It should be noted that, in this document, the etching selectivity ratio of A to B can refer to the ratio of the etching rate of A to the etching rate of B under certain etching conditions (e.g., etching using an etchant). Based on the above, a relatively large etching selectivity ratio between the materials of the sacrificial layer 310 and the first dielectric layer 320 can mean that, under certain etching conditions, the etching rate of the material of the sacrificial layer 310 is faster than the etching rate of the material of the first dielectric layer 320. Thus, in the process of removing the sacrificial layer 310 and retaining the first dielectric layer 320 by etching, the material of the sacrificial layer 310 can be removed while the material of the first dielectric layer 320 is retained.

[0093] In some embodiments, a sacrificial layer 310 and a first dielectric layer 320 may be formed on a substrate S by a thin film deposition process. The thin film deposition process may be one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or electroplating.

[0094] S2, forming an opening that penetrates the initial stacked structure.

[0095] See Figure 7B The opening H1 penetrates the initial stacked structure 300, thus exposing the side surfaces 310a of each sacrificial layer 310 in the initial stacked structure 300. The side surfaces (e.g., side surface 310a) of the sacrificial layers 310 can be surfaces where the sacrificial layers 310 are distributed along a direction parallel to the substrate S (or a direction perpendicular to the thickness direction of the three-dimensional memory, or a direction perpendicular to the thickness direction of the initial stacked structure 300, such as parallel to the XY plane). Similarly, the opening H1 can also expose the side surfaces 320a of each first dielectric layer 320 in the initial stacked structure 300, where the side surfaces (e.g., side surface 320a) of the first dielectric layer 320 can be surfaces where the first dielectric layer 320 is distributed along a direction parallel to the substrate S.

[0096] Furthermore, the side surface 310a of the sacrificial layer and the side surface 320a of the first dielectric layer adjacent to the sacrificial layer can be substantially flush. In this document, "substantially flush" can include "A and B being completely flush," or it can include a distance between A and B within an acceptable range of deviation. Specifically, "substantially flush" can include "side surface 310a and side surface 320a being completely flush," or it can include a distance between side surface 310a and side surface 320a being less than or equal to 5% of the dimension of the opening H1 along the first direction X (e.g., the average dimension of the opening H1 along the first direction X).

[0097] In some embodiments, the opening H1 may extend to the substrate S. The extension of the opening H1 to the substrate S can mean one of two things: first, the bottom of the opening H1 may be flush with the interface IF1 between the substrate S and the initial stacked structure 300; second, the bottom of the opening H1 may protrude beyond the interface IF1 between the substrate S and the initial stacked structure 300. Because the opening H1 extends to the substrate S, it may also expose a portion of the substrate S.

[0098] The opening H1 can be formed by an etching process. The etching process can be, for example, dry etching or wet etching. Exemplarily, a mask layer with the opening can be formed on the initial stacked structure 300, the material of which includes, for example, a photoresist material. Using this mask layer as a mask, the opening H1 can be formed by an anisotropic etching process.

[0099] S3. Along a direction parallel to the substrate, remove the portion of the sacrificial layer near the opening to form a first recess.

[0100] See Figure 7B , Figure 7C and Figure 8 ,in, Figure 8 for Figure 7C A magnified view of region A in the initial stacked structure shows the structure of a first recess. The material is removed along a direction parallel to the substrate S (e.g., parallel to the XY plane). Figure 7B The portion of the sacrificial layer 310 near the opening H1 can form Figure 7C The side 310b of the sacrificial layer. Based on this, Figure 7C Compared to the side 310b of the sacrificial layer in the middle Figure 7B The side 310a of the sacrificial layer is recessed.

[0101] The first recess R1 is surrounded by the side surface 310b of the sacrificial layer 310 and the first dielectric layers 320 on both sides of the sacrificial layer 310. The first dielectric layers 320 on both sides of the sacrificial layer 310 are, for example, first dielectric layers 321 and second dielectric layers 322 located on both sides of the sacrificial layer 310 along a direction perpendicular to the substrate S (e.g., parallel to the third direction Z).

[0102] Based on the above, along a direction parallel to the substrate, one or more sacrificial layers 310 near the opening H1 are removed (see...). Figure 7B The portion of ) can form an opening H2 (see Figure 7C The opening H2 has one or more first recesses R1. Alternatively, the opening H2 may expose one or more side surfaces 310b of the sacrificial layer 310 and the side surfaces 320a of the multiple first dielectric layers 320, and the side surfaces 310b of the sacrificial layer are further away from the axis H2c of the opening H2 than the side surfaces 320a of the first dielectric layers.

[0103] In some embodiments, the initial stacked structure 300 includes a plurality of sacrificial layers 310 and a plurality of first dielectric layers 320. In step S3, portions of the plurality of (e.g., each) sacrificial layers 310 near the opening H1 may be removed, forming a plurality of first recesses R1. Exemplarily, a first recess R1 may be provided between every two adjacent first dielectric layers 320 in a direction perpendicular to the substrate S (e.g., parallel to the third direction Z).

[0104] The portion of the sacrificial layer 310 adjacent to the opening H1 can be removed by an etching process (e.g., dry / wet etching). A suitable etchant can be selected such that, during the etching process, the etching rate of the material of the sacrificial layer 310 is greater than the etching rate of the material of the first dielectric layer 320, so that more material of the sacrificial layer 310 can be removed while less (or no) material of the first dielectric layer 320 is removed to form the first recess R1.

[0105] S4. A material layer is formed on the inner wall of the opening having the first recess. The surface of the material layer has a second recess located in the first recess.

[0106] See Figure 7C and Figure 7D A material layer 400 can be formed on the inner wall of the opening H2. After the material layer 400 is formed on the inner wall of the opening H2, an opening H3 can be formed, and the material layer 400 can be exposed in the opening H3.

[0107] In some embodiments, the material of the material layer 400 is polycrystalline silicon. In other embodiments, the material of the material layer 400 is silicon nitride. The material of the material layer 400 may also be other suitable materials, and the embodiments of this disclosure are not limited thereto.

[0108] Material layer 400 can be formed by thin film deposition process. Thin film deposition process is, for example, one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or electroplating process.

[0109] In some embodiments, the process for forming the material layer 400 is a thin-film deposition process with uniform film thickness. Therefore, the material layer 400 can be conformally formed on the surface exposed by the opening H2, that is, a continuously distributed material layer 400 can be formed on the surface exposed by the opening H2. In this case, the inner wall of the opening H3 can be formed by the material layer 400.

[0110] Furthermore, in some embodiments, since the material layer 400 can be conformally formed on the surface exposed by the opening H2, the material of the material layer 400 can also be deposited on the exposed surfaces of the initial stacked structure 300 and the exposed surfaces of the substrate S. Exemplarily, a portion of the material layer 400 can also be located on the surface 300a of the initial stacked structure 300 away from the substrate S. Also exemplary, the opening H2 having the first recess R1 extends into the substrate S. The description of the opening H2 extending into the substrate S can be found above regarding the description of the opening H1 extending into the substrate S, and will not be repeated here. Since the opening H2 extends into the substrate S, the material layer 400 also covers the surface Sa of the substrate S exposed by the opening H2 having the first recess R1.

[0111] Since the opening H2 has a first recess R1, the surface 400a of the material layer 400 has one or more second recesses R2, and a second recess R2 (e.g., each second recess R2) is located in a first recess R1. Alternatively, the opening H3 may have one or more second recesses R2.

[0112] See Figure 9 , Figure 9 for Figure 7D A partially enlarged view of region B of the initial stacked structure. In some embodiments, the recess depth R1h of the first recess R1 is greater than the thickness 400h of the material layer 400. This allows for a larger recess depth R2h in the second recess R2, which is beneficial for the subsequent formation of a protective portion in the second recess R2. For example, the recess depth R1h of the first recess R1 can be 6nm, 7nm, 8nm, 9nm, or 10nm. The thickness 400h of the material layer 400 can be 3nm, 4nm, or 5nm.

[0113] S5. A protective portion is formed in the second recess. The portion of the material layer that is covered by the protective portion is the first portion, and the remaining portion is the second portion.

[0114] See Figure 7E A protective portion M can be formed in a second recess R2 (e.g., each second recess R2).

[0115] The material of the protective part M can be an inorganic material; for example, the material of the protective part M is Al2O3.

[0116] See Figure 7E and Figure 10A ,in, Figure 10A for Figure 7EThe image shows a partial enlarged view of region C in the initial stacked structure. The material layer 400 being shielded by the protective portion M can mean that the protective portion M is provided on the material layer 400 along a direction parallel to the substrate S (e.g., parallel to the XY plane). Based on this, in the material layer 400, the portion directly opposite the protective portion M along a direction parallel to the substrate S (e.g., parallel to the XY plane) can be the first portion 410 shielded by the protective portion M, and the remaining portion is the second portion 420.

[0117] In some embodiments, see Figure 7E and Figure 10B ,in, Figure 10B for Figure 7E A partially enlarged view of region C in the initial stacked structure. The protective portion M includes a first end M1 and a second end M2. The second end M2 is further away from the sacrificial layer 310 than the first end M1 in a direction parallel to the substrate S (e.g., parallel to the XY plane). Furthermore, the dimension M2h of the second end M2 in a direction perpendicular to the substrate S (e.g., parallel to the third direction Z) is larger than the dimension M1h of the first end M1 in the same direction. Thus, since the dimension M2h of the second end M2 is approximately equal to the dimension M1h of the first end M1, the protective portion M with the second end M2 can shield more of the material layer 400.

[0118] See Figure 10B , Figure 11A , Figure 11B and Figure 11C ,in Figure 11A This is a process flow diagram illustrating the fabrication method of the three-dimensional memory in some embodiments. Figure 11B for Figure 11A A magnified view of region D of the initial stacked structure. Figure 11C In order to be in Figure 11B The diagram shows the structure of the second recess formed by forming a material layer in the first recess. To ensure that the size M2h of the second end M2 of the protective portion M is larger than the size M1h of the first end M1, in some possible implementations, before step S4, the sidewall R1a of the first recess R1 can be trimmed so that the portion of the sidewall R1a of the first recess away from the sacrificial layer 310 is arc-shaped. The sidewall R1a of the first recess R1 is formed by the first dielectric layer 320; for example, the sidewall R1a of the first recess R1 is the inner wall of the first recess R1 distributed along the thickness direction of the semiconductor structure. Thus, the portion of the sidewall R2a of the subsequently formed second recess R2 away from the sacrificial layer 310 can also be arc-shaped.

[0119] Furthermore, the protective portion M in the second recess R2 can contact the arcuate portion of the sidewall R2a of the second recess R2. For example, the protective portion M can contact the entire arcuate portion of the sidewall R2a of the second recess. Also for example, the protective portion M can contact only a portion of the arcuate portion of the sidewall R2a of the second recess. Because the protective portion M in the second recess R2 contacts the arcuate portion of the sidewall R2a of the second recess R2, the size of the second end portion M2 of the protective portion M can be made larger than the size of the first end portion M1.

[0120] In some embodiments, the first dielectric layer 320 can be removed through opening H2 by an etching process (e.g., dry / wet etching process) (see [link]). Figure 7C The exposed edge portion causes the surface of the first dielectric layer 320 to include an arcuate surface, thereby making the portion of the sidewall R1a of the first recess away from the sacrificial layer 310 arcuate. Exemplarily, a low-concentration hydrofluoric acid can be used as the etchant, and by controlling the etching time (e.g., using a shorter etching time), the first dielectric layer 320 can be removed through the opening H2 (see...). Figure 7C A portion of the exposed edge causes the surface of the first dielectric layer 320 to include an arcuate surface.

[0121] See Figure 12A and Figure 12B In some embodiments, step S5 may include the following sub-steps; or, in other words, forming the protective portion M in the second recess R2 may include the following sub-steps:

[0122] S51, see also Figure 12A A mask layer 500 is formed on the material layer 400. The mask layer 500 fills the second recess R2. Specifically, the mask layer 500 may fill part or all of the second recess R2. In some embodiments, the mask layer 500 fills all of the second recess R2, that is, the surface 500a of the mask layer 500 may protrude from the second recess R2. Exemplarily, the thickness of the mask layer 500 is 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm.

[0123] S52, see also Figure 12A and Figure 12B A portion of the mask layer 500 is removed to form one or more protective portions M. Exemplarily, a portion of the mask layer 500 can be removed by an etching process (e.g., a dry / wet etching process). For example, isotropic etching can be performed on the mask layer 500, and by controlling the etching time, the portion of the mask layer 500 filling the second recess R2 can be retained to form one or more protective portions M.

[0124] See also Figure 7EAfter performing step S5, an opening H4 can be formed. The opening H4 can expose the second part 420 of the material layer 400, and can also expose one or more protective parts M.

[0125] S6. Modify the second part of the material layer.

[0126] See Figure 7E and Figure 7F After step S6 is executed, the second portion 420 of the material layer 400 is modified so that the material of the second portion 420 in the material layer 400 is different from the material of the first portion 410. For ease of explanation, the modified second portion 420 will be referred to as the extension portion 600 below.

[0127] In some embodiments, step S6 may include a second portion 420 of the oxide material layer. Exemplarily, this can be achieved through an opening H4 (see...). Figure 7E The second portion 420 of the material layer that is not shielded by the protective part M (or exposed by the protective part M) is oxidized using an oxidation process. Specifically, through the opening H4, the second portion 420 of the material layer exposed by the protective part M can come into contact with oxygen (such as oxygen in oxygen gas or water vapor), and thus can be oxidized. However, the first portion 410 of the material layer 400 that is shielded by the protective part M cannot come into contact with oxygen and therefore cannot be oxidized.

[0128] Furthermore, after the second portion 420 of the material layer is oxidized, its material differs from the unoxidized first portion 410. For example, the material of the material layer 400 is polycrystalline silicon. After performing step S6, the second portion 420 of the material layer 400 can be oxidized to form silicon oxide; that is, after performing step S6, the material of the expanded portion 600 includes silicon oxide. The first portion 410 of the material layer is not oxidized, and its material remains polycrystalline silicon. Alternatively, for another example, the material of the material layer 400 is silicon nitride. After performing step S6, the second portion 420 of the material layer 400 can be oxidized to form silicon oxide or silicon oxynitride; that is, after performing step S6, the material of the expanded portion 600 includes silicon oxide and / or silicon oxynitride. The first portion 410 of the material layer is not oxidized, and its material remains silicon nitride.

[0129] In some possible implementations, as described above, the material of the material layer 400 can be polycrystalline silicon. In this case, after modifying (e.g., oxidizing) the second portion 420 of the material layer, the material of the resulting extension 600 can include silicon oxide. Furthermore, the thickness of the extension 600 containing silicon oxide can be greater than the thickness of the material layer 400 containing polycrystalline silicon. For example, the thickness of the material layer 400 is 5 nm, while the thickness of the extension 600 formed after modifying (e.g., oxidizing) the second portion 420 of the material layer can be approximately 11 nm.

[0130] In some embodiments, see Figure 7D and Figure 7F A portion of the material layer 400 may also be located on the surface 300a of the initial stacked structure 300 away from the substrate S, and a portion of the material layer 400 may also cover the surface Sa of the substrate S exposed by the opening H2 with the first recess R1. Since none of the aforementioned portions of the material layer 400 are obscured by the protective portion M, they can all belong to the second portion 420 of the material layer. In step S6, the aforementioned portions of the material layer 400 may also be modified.

[0131] S7. Remove the first part of the protective layer and material layer.

[0132] See Figure 7F and Figure 7G By removing the protective portion M and the first portion 410 of the material layer, an opening H5 with a third recess R3 can be formed. The third recess R3 is formed by the side surface 310b of the sacrificial layer 310, first dielectric layers 320 on both sides of the sacrificial layer 310 (e.g., first dielectric layer 321 and second dielectric layer 322), and expansion portions 600 (e.g., expansion portions 610 and 620) located on these two first dielectric layers 320. The opening H5 exposes the side surface 600a of the expansion portion 600 (i.e., the side surface of the second portion 420 of the modified material layer) and the side surface 310b of the sacrificial layer.

[0133] In some embodiments, step S7 may include the following sub-steps:

[0134] S71, Remove the protection section M.

[0135] S72, Remove the first part of the material layer 410.

[0136] In some embodiments, the protective portion M and the first portion 410 of the material layer can be removed by an etching process (e.g., a dry / wet etching process). In some possible implementations, sub-steps S71 and S72 can be performed in the same process. Exemplarily, in the etching process, a suitable etchant can be selected such that the etching rate of the material of the protective portion M is similar to the etching rate of the material of the first portion 410 of the material layer, thus allowing the protective portion M and the first portion 410 of the material layer to be removed in the same etching process. In other possible implementations, sub-step S71 can be performed by one etching process, and sub-step S72 by another etching process.

[0137] Furthermore, referring to the explanation above, after performing step S6, for material layer 400, the material of the first portion 410 shielded by the protective portion M and the material of the modified second portion 420 (i.e., the expanded portion 600) can be different. Therefore, in step S7, a suitable etchant can be selected so that the etching selectivity between the material of the first portion 410 and the material of the expanded portion 600 is relatively large. In this way, the first portion 410 can be removed, while less or no part of the expanded portion 600 can be removed.

[0138] Furthermore, in step S7, a suitable etchant can be selected so that the etching options for the material of the protective part M and the material of the expanded part 600 are relatively large. In this way, the protective part M can be removed, while less or no part of the expanded part 600 can be removed.

[0139] After performing steps S1 to S7, an opening H5 can be formed. Since the opening H5 exposes the side surface of the expansion portion 600, the minimum dimension of the opening H5 (e.g., the minimum dimension along the first direction X) is relatively smaller than... Figure 7B The minimum size of the opening H1 (e.g., the minimum size along the first direction X) can be reduced. When fabricating the semiconductor structure, an opening H1 with a relatively large minimum size (small depth-to-width ratio) can be formed first in the initial stacked structure 300, and then steps S3-S7 can be performed to form an opening H5 with a smaller minimum size (larger depth-to-width ratio). This reduces the technological difficulty of forming an opening with a large depth-to-width ratio.

[0140] Furthermore, as described above, in some embodiments, the material of the material layer 400 can be polycrystalline silicon. In this case, after modifying (e.g., oxidizing) the second portion 420 of the material layer, the material of the resulting extension 600 can include silicon oxide. Moreover, the thickness of the extension 600 containing silicon oxide can be greater than the thickness of the material layer 400 containing polycrystalline silicon. This allows for a further reduction in the size of the opening H5.

[0141] In addition, see Figure 7G and Figure 10B As described above, in some embodiments, for a protective portion M, along a direction perpendicular to the substrate S (e.g., parallel to the third direction Z), the size M2h of the second end M2 is larger than the size M1h of the first end M1, so the protective portion M can shield more of the material layer 400. Therefore, after removing the first portion 410 of the material layer, the distance t between two adjacent expansion portions 600 along the direction perpendicular to the substrate S can be larger.

[0142] Referring to the above description, in the subsequent process of removing the sacrificial layer 310 and forming the gate layer, the size of the interface between the formed gate layer and the channel structure (e.g., the channel length of the memory cell transistor corresponding to the gate layer) can be approximately the same as the distance t between two adjacent expansion portions 600. Since the size M2h of the second end M2 of the protection portion M is larger than the size M1h of the first end M1, the distance t between two adjacent expansion portions 600 can be larger. Therefore, the interface size between the subsequently formed gate layer and the channel structure can also be larger, which can ensure the channel length of the memory cell transistor in the three-dimensional memory, thereby improving the performance of the three-dimensional memory.

[0143] See also the following for some possible implementations. Figure 7G and Figure 10B The dimension M2h of the second end M2 of the protective portion M along the direction perpendicular to the substrate S (e.g., parallel to the third direction Z) is greater than or approximately equal to the thickness 310h of the sacrificial layer 310 (e.g., the dimension of the sacrificial layer 310 along the direction perpendicular to the substrate S). Here, "the dimension M2h of the second end M2 is approximately equal to the thickness 310h of the sacrificial layer 310" can mean that the difference between the dimension M2h of the second end M2 and the thickness 310h of the sacrificial layer 310 is less than or equal to 5% of the dimension M2h of the second end M2 or the thickness 310h of the sacrificial layer 310. Based on the above, since the dimension M2h of the second end M2 of the protective portion M is greater than or approximately equal to the thickness 310h of the sacrificial layer 310, after removing the first portion 410 of the material layer, the distance t between two adjacent expansion portions 600 along the direction perpendicular to the substrate S can be greater than or approximately equal to the thickness 310h of the sacrificial layer 310. This further ensures the channel length of the memory cell transistor in the three-dimensional memory, thereby improving the performance of the three-dimensional memory.

[0144] For other possible implementations, see [link to relevant documentation]. Figure 7G and Figure 10B For a protective portion M, along a direction perpendicular to the substrate S (e.g., parallel to the third direction Z), the size M2h of the second end M2 is larger than the size M1h of the first end M1, and the size M2h of the second end M2 is smaller than the thickness 310h of the sacrificial layer 310. After removing the first portion 410 of the material layer, the size of the expansion portion 600 along the direction perpendicular to the substrate S can be relatively large. In subsequent processes where the sacrificial layer 310 may be removed and the gate layer is formed, the larger size of the expansion portion 600 can improve the problem of short circuits between two adjacent gate layers (e.g., adjacent along a direction perpendicular to the substrate S) due to insufficient distance.

[0145] S8 (optionally), a filling portion is formed in the third recess, which is formed by removing the first portion of the protective portion and the material layer.

[0146] See Figure 7G and Figure 7H A filling portion F can be formed in one (e.g., each) third recess R3. After performing step S8, an opening H6 can be formed, which can expose the side surface Fa of the filling portion F and the side surface 600a of the expansion portion 600.

[0147] In some embodiments, the filling portion F may fill a portion of the third recess R3, that is, the side surface Fa of the filling portion F is farther away from the axis H6a of the opening H6 than the side surface 600a of the expansion portion 600. In other embodiments, the filling portion F may fill the entire third recess R3, that is, the side surface Fa of the filling portion F is substantially flush with the side surface 600a of the expansion portion 600. The substantially flush alignment of the side surface Fa of the filling portion F with the side surface 600a of the expansion portion 600 may include the side surface Fa being completely flush with the side surface 600a, or the distance between the side surface Fa and the side surface 600a being less than or equal to 5% of the dimension of the opening H6 along the first direction X (e.g., the average dimension of the opening H6 along the first direction X).

[0148] Since the filling part F can fill part or all of the third recess R3, the inner wall of the opening H6 formed after step S8 can be relatively flat.

[0149] The size of the opening H6 formed in step S8 (e.g., the average size along the first direction X) is compared to Figure 7B The size of the opening H1 (e.g., the average size along the first direction X) can be reduced. When fabricating the semiconductor structure, a larger opening H1 (smaller depth-to-width ratio) can be formed in the initial stacked structure 300 first, and then steps S3-S8 can be performed to form a smaller opening H6 (larger depth-to-width ratio). This reduces the process difficulty of forming openings with a larger depth-to-width ratio. Furthermore, since the size of opening H6 is smaller than that of opening H1, and the center distance between adjacent openings H6 is approximately the same as the center distance between adjacent openings H1, the minimum distance between the edges of adjacent openings H6 can be larger than the minimum distance between the edges of adjacent openings H1. Based on this, in step S2, the minimum distance between the edges of adjacent openings H1 can be reduced, allowing more openings H1 to be formed within a given area of ​​the XY plane. After executing steps S3 to S8, the minimum distance between the edges of adjacent openings H6 is greater than the minimum distance between the edges of adjacent openings H1. This allows the minimum distance between the edges of adjacent openings H6 to provide a larger process window for subsequent possible steps of removing the sacrificial layer 310 and fabricating the gate layer. It can also improve the resistance of the gate layer, thereby increasing the storage density of the three-dimensional memory while ensuring its performance.

[0150] In some embodiments, the material of the filler portion F is the same as the material of the sacrificial layer 310. This results in better bonding between the filler portion F and the sacrificial layer 310, improving the structural stability of the semiconductor structure. Furthermore, since the material of the filler portion F is the same as the material of the sacrificial layer 310, the subsequent process of removing the sacrificial layer 310 and the filler portion F to form the gate layer can be simpler and more controllable.

[0151] See Figure 13A and Figure 13B In some embodiments, step S8 may include the following sub-steps; or, in other words, forming the filling portion F in the third recess R3 may include the following sub-steps:

[0152] S81, see also Figure 7G and Figure 13A A second dielectric layer 700 is formed on the inner wall of the opening H5 having the third recess R3. The second dielectric layer 700 fills the third recess R3. Specifically, the second dielectric layer 700 may fill part or all of the third recess R3. In some embodiments, the second dielectric layer 700 fills all of the third recess R3, that is, the surface 700a of the second dielectric layer 700 may protrude from the third recess R3.

[0153] S82, see also Figure 13A and Figure 13B A portion of the second dielectric layer 700 is removed to form one or more filling portions F. Exemplarily, a portion of the second dielectric layer 700 can be removed by an etching process (e.g., a dry / wet etching process). For example, isotropic etching can be performed on the second dielectric layer 700, and by controlling the etching time, a portion of the second dielectric layer 700 filling the third recess R3 can be retained, thereby forming one or more filling portions F.

[0154] S9 (optionally), after removing the first portion of the protective layer and the material layer, a semiconductor channel is formed in the opening.

[0155] See Figure 7G and Figure 7I In some embodiments, a semiconductor channel 210 may be formed in the opening H5 formed after step S7. The semiconductor channel 210 may serve as the channel for each transistor in a string of memory cells of a three-dimensional memory. The material of the semiconductor channel 210 may be a semiconductor material, such as amorphous, polycrystalline, or monocrystalline silicon, or a combination of one or more of these. In some embodiments, the material of the semiconductor channel 210 includes polycrystalline silicon.

[0156] In some possible implementations, a functional layer 220 may also be formed in the opening H5. The functional layer 220 and the semiconductor channel 210 can form a channel structure 200. Specifically, the functional layer 220 may be disposed between the semiconductor channel 210 and the initial stacked structure 300. The functional layer 220 may include a tunneling layer. The functional layer 220 may also include a charge storage layer, which may be disposed between the tunneling layer and the semiconductor channel 210. The functional layer 220 may also include a barrier layer, which may be disposed between the charge storage layer and the initial stacked structure 300.

[0157] See Figure 7G and Figure 7J In some embodiments, the functional layer 220 formed in the opening H5 is relatively thick, enough to fill the entire third recess R3; that is, the surface 220a of the functional layer 220 can protrude from the third recess R3. In this case, the surface of the semiconductor channel 210 disposed on the surface of the functional layer 220 can be relatively flat.

[0158] See Figure 7H and Figure 7K In some embodiments, a semiconductor channel 210 can be formed in the opening H6 formed after step S8. In some possible implementations, a functional layer 220 can also be formed in the opening H6, and the functional layer 220 and the semiconductor channel 210 can form a channel structure 200. The structure and position of the functional layer 220 can be referred to the description above, and will not be repeated here. Referring to the description above, since the inner wall of the opening H6 can be relatively flat, the surface of the channel structure 200 formed in the opening H6 can also be relatively flat.

[0159] See Figure 7G and Figure 7L In some embodiments, before performing step S9, a portion 420a of the second part of the material layer located at the bottom of opening H5 (i.e., the side of opening H5 closest to the substrate) can be removed before performing step S9. This makes it easier for the source terminal to couple with the semiconductor channel 210 in subsequent possible steps of removing the substrate S to fabricate the source terminal, thereby improving the electrical connection stability between the semiconductor channel 210 and the source terminal. Similarly, see... Figure 7H and Figure 7M In some embodiments, before performing step S9, a portion 420b of the second part of the material layer located at the bottom of opening H6 (i.e., the end of opening H6 near the substrate) can be removed before performing step S9. This can also improve the stability of the electrical connection between the semiconductor channel and the source end.

[0160] Figure 14 This is a structural diagram of a three-dimensional memory in some embodiments of this disclosure. See also... Figure 14Based on the above description, in a three-dimensional memory according to some embodiments, such as a three-dimensional memory fabricated by the fabrication method of any of the above embodiments, the stacked structure 100 may include at least one (e.g., one; or more) gate layer G and at least one (e.g., one; or more) third dielectric layer 900. Furthermore, the respective gate layers G and the respective third dielectric layers 900 are alternately stacked. Exemplarily, in the thickness direction of the stacked structure 100 (e.g., parallel to the third direction Z), a third dielectric layer 900 is disposed between two adjacent gate layers G, and a gate layer G is disposed between two adjacent third dielectric layers 900.

[0161] The gate layer G can be made of one or more of the following materials: tungsten, cobalt, copper, aluminum, doped silicon, and silicide. The third dielectric layer 900 can be made of one or more of the following materials: silicon nitride, silicon oxide, and silicon oxynitride.

[0162] The three-dimensional memory 1 also includes a vertical structure 800. The vertical structure 800 extends through the stacked structure 100. In some embodiments, the vertical structure 800 includes a semiconductor channel 210. In this case, the vertical structure 800 can be a channel structure. The vertical structure 800 (e.g., a channel structure) may also include a functional layer 220. The functional layer 220 may be disposed between the semiconductor channel 210 and the stacked structure 100. The structure of the functional layer 220 can be referred to the description above, and will not be repeated here.

[0163] The three-dimensional memory 1 may also include a source end SL. The material of the source end SL may be a semiconductor material, such as one or more combinations of amorphous, polycrystalline, or monocrystalline silicon. In some embodiments, part or all of the source end SL may be doped.

[0164] The vertical structure 800 can be coupled to the source terminal SL. Exemplarily, the vertical structure 800 (e.g., a channel structure) includes a semiconductor channel 210, which can be coupled to the source terminal SL.

[0165] In some embodiments, the vertical structure 800 (e.g., a channel structure) further includes an insulating portion IB. The insulating portion IB may be disposed on the side of the semiconductor channel 210 away from the stacked structure 100.

[0166] In the laminated structure 100, the third dielectric layer 900 includes a first dielectric layer 320 and an extension portion 600, the extension portion 600 being disposed between the first dielectric layer 320 and the vertical structure 800 (e.g., a channel structure). Specifically, the description of the first dielectric layer 320 and the extension portion 600 can be found above, and will not be repeated here.

[0167] An interface may exist between the first dielectric layer 320 and the expansion portion 600. In some embodiments, the material of the first dielectric layer 320 includes silicon oxide, and the material of the expansion portion 600 also includes silicon oxide. In this case, exemplarily, the first dielectric layer 320 and the expansion portion 600 can form an integral structure, resulting in better bonding and improved structural stability of the three-dimensional memory. Also exemplarily, since the fabrication processes of the first dielectric layer 320 and the expansion portion 600 may be different, an interface may exist between them. In other embodiments, the material of the first dielectric layer 320 includes silicon oxide, and the material of the expansion portion 600 includes silicon oxynitride. In this case, an interface may exist between the first dielectric layer 320 and the expansion portion 600.

[0168] See Figure 10B , Figure 14 and Figure 15A ,in, Figure 15A for Figure 14 A partially enlarged view of region E in the three-dimensional memory. In some embodiments, in the thickness direction of the three-dimensional memory 1 (e.g., parallel to the third direction Z), the size 600h of the expansion portion 600 is greater than the thickness 320h of the first dielectric layer 320. Referring to the above description, in some embodiments, along the thickness direction of the three-dimensional memory, the size M2h of the second end portion M2 of the protection portion can be smaller than the thickness 310h of the sacrificial layer 310. In this case, in the three-dimensional memory fabricated by performing the above-described three-dimensional memory fabrication method, in the thickness direction of the three-dimensional memory, the size 600h of the expansion portion 600 can be greater than the thickness 320h of the first dielectric layer 320. In this case, the distance t between two adjacent expansion portions 600 can be smaller. This can improve the insulation performance of the third dielectric layer 900 and improve the problem of short-circuiting gate layers of two adjacent memory cell transistors in the memory cell string.

[0169] See Figure 10B , Figure 14 and Figure 15B ,in, Figure 15B for Figure 14A partially enlarged view of region E in the three-dimensional memory. In other embodiments, the size 600h of the expansion portion 600 is smaller than the thickness 320h of the first dielectric layer 320 in the thickness direction of the three-dimensional memory 1. Referring to the above description, in some embodiments, the size of the second end portion M2 of the protection portion M can be larger than the thickness of the sacrificial layer 310 along the thickness direction of the three-dimensional memory. In this case, in the three-dimensional memory fabricated by the above-described three-dimensional memory fabrication method, the size 600h of the expansion portion 600 can be smaller than the thickness 320h of the first dielectric layer 320 in the thickness direction of the three-dimensional memory 1. In this case, the distance t between two adjacent expansion portions 600 can be larger. In this way, the size of the interface between the gate layer G and the vertical structure 800 (e.g., a channel structure) can be increased, thereby ensuring the channel length of the memory cell transistors in the memory cell string and improving the performance of the three-dimensional memory.

[0170] See Figure 10B , Figure 14 and Figure 15C , Figure 15C for Figure 14 A partially enlarged view of region E in the three-dimensional memory. In other embodiments, the size 600h of the expansion portion 600 in the thickness direction of the three-dimensional memory 1 may be approximately the same as the thickness 320h of the first dielectric layer 320. Referring to the above description, in some embodiments, the size of the second end portion M2 of the protection portion M may be approximately the same as the thickness 310h of the sacrificial layer 310 along the thickness direction of the semiconductor structure. In this case, in the three-dimensional memory fabricated by the above-described three-dimensional memory fabrication method, the size 600h of the expansion portion 600 in the thickness direction of the three-dimensional memory may be approximately the same as the thickness 320h of the first dielectric layer 320. In this way, the channel length of the memory cell transistor in the memory cell string can be guaranteed while ensuring the insulation performance of the third dielectric layer 900, thereby improving the performance of the three-dimensional memory.

[0171] See also Figure 14 In some embodiments, the side 900a of the third dielectric layer 900 that contacts the vertical structure 800 (e.g., a channel structure) and the side 310a' of the gate layer G that contacts the vertical structure 800 are substantially flush. The substantially flush nature of the side surfaces 900a and 310a' can include the side surfaces 900a and 310a' being completely flush, or the distance between the side surfaces 900a and 310a' being less than or equal to 5% of the dimension of the vertical structure 800 along the first direction X.

[0172] See Figure 16 and Figure 17 , Figure 16 This is a structural diagram of a three-dimensional memory according to some embodiments of the present disclosure. Figure 17This is a structural diagram of a three-dimensional memory according to some embodiments of the present disclosure. In some embodiments, the side 900a of the third dielectric layer 900 that contacts the vertical structure 800 (e.g., a channel structure) protrudes beyond the side 310a' of the gate layer G that contacts the vertical structure 800. Alternatively, side 900a is closer to the axis 800a of the vertical structure 800 than side 310a'. See, for example, [link to relevant documentation]. Figure 16 The thickness of the functional layer 220 can be relatively small, such that the surface of the semiconductor channel 210 disposed on the functional layer 220 has one or more recesses. See also, by example, […]. Figure 17 The thickness of the functional layer 220 can be relatively large, so that the surface of the semiconductor channel 210 disposed on the functional layer 220 can be relatively flat.

[0173] See also Figure 14 In some embodiments, the materials of the first dielectric layer 320 and the expansion portion 600 are the same in the third dielectric layer 900. Referring to the above description, the material of the first dielectric layer 320 can be silicon oxide, and the material of the expansion portion 600 can also be silicon oxide. In other embodiments, the material of the expansion portion 600 in the third dielectric layer 900 contains more elements than the material of the first dielectric layer 320. For example, referring to the above description, the material of the expansion portion 600 can include silicon oxynitride, in which case the material of the expansion portion 600 can contain oxygen, nitrogen, and silicon. The material of the first dielectric layer 320 can be silicon oxide, in which case the material of the first dielectric layer 320 can contain oxygen and silicon.

[0174] Embodiments of this disclosure also provide a storage system. Figure 18 This is a block diagram of a storage system according to some embodiments. Figure 19 This is a block diagram of a storage system according to other embodiments. See also... Figure 18 and Figure 19 The storage system MS includes a three-dimensional memory 1 and a controller 2. The three-dimensional memory 1 can be any of the three-dimensional memory provided in the above embodiments. The controller 2 is coupled to the three-dimensional memory 1 to control the storage of data in the three-dimensional memory 1.

[0175] The storage system (MS) can be integrated into various types of storage devices, for example, within the same package (e.g., Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) package). In other words, the storage system (MS) can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0176] In some embodiments, see Figure 18 The storage system MS includes a controller 2 and a three-dimensional memory 1. The storage system MS can be integrated into a memory card.

[0177] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0178] In other embodiments, see Figure 19 The storage system MS includes a controller 2 and multiple three-dimensional storage devices 1. The storage system MS can be integrated into solid-state drives (SSDs).

[0179] In some embodiments of the storage system MS, the controller 2 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0180] In other embodiments, the controller 2 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as a data storage device for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0181] In some embodiments, controller 2 may be configured to manage data stored in the 3D memory 1 and to communicate with external devices (e.g., a host). In some embodiments, controller 2 may also be configured to control the operation of the 3D memory 1, such as read, erase, and program operations. In some embodiments, controller 2 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory 1, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 2 is also configured to process error correction codes relating to data read from or written to the 3D memory 1.

[0182] Of course, controller 2 can also perform any other suitable functions, such as formatting the three-dimensional memory 1. For example, controller 2 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0183] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0184] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: An initial stacked structure is formed on a substrate, the initial stacked structure comprising alternating sacrificial layers and a first dielectric layer; An opening is formed that penetrates the initial stacked structure; Along a direction parallel to the substrate, the portion of the sacrificial layer near the opening is removed to form a first recess; A material layer is formed on the inner wall of the opening having the first recess, and the surface of the material layer has a second recess located in the first recess; A protective portion is formed in the second recess, and the portion of the material layer that is covered by the protective portion is the first portion, and the remaining portion is the second portion; The second portion of the material layer is modified; Remove the protective portion and the first portion of the material layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The protective portion includes a first end and a second end, and is arranged in a direction parallel to the substrate, wherein the second end is farther away from the sacrificial layer than the first end; The dimension of the second end in the direction perpendicular to the substrate is greater than the dimension of the first end in the direction perpendicular to the substrate.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The dimension of the second end along the direction perpendicular to the substrate is greater than or equal to the thickness of the sacrificial layer.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Also includes: Before the step of forming the material layer, the sidewall of the first recess is trimmed so that the portion of the sidewall of the first recess away from the sacrificial layer is arc-shaped, and the sidewall of the first recess is formed by the first dielectric layer. The portion of the sidewall of the second recess that is away from the sacrificial layer is arc-shaped, and the protective portion contacts the arc-shaped portion of the sidewall of the second recess.

5. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The depth of the first recess is greater than the thickness of the material layer.

6. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Forming a protective portion in the second recess includes: A mask layer is formed on the material layer, and the mask layer fills the second recess; A portion of the mask layer is removed to form the protective portion.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Modifying the second portion of the material layer includes: The second portion of the material layer is oxidized.

8. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The material of the material layer is polycrystalline silicon or silicon nitride.

9. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The opening having the first recess extends into the substrate, and the material layer also covers the surface of the substrate exposed by the opening having the first recess.

10. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Also includes: A filling portion is formed in the third recess, which is formed by removing the protective portion and the first portion of the material layer.

11. The method for manufacturing a three-dimensional memory according to claim 10, characterized in that, The material of the filling portion is the same as the material of the sacrificial layer.

12. The method for manufacturing a three-dimensional memory according to claim 10, characterized in that, The formation of a filling portion in the third recess includes: A second dielectric layer is formed on the inner wall of the opening having the third recess, and the second dielectric layer fills the third recess; A portion of the second dielectric layer is removed to form the filling portion.

13. The method for manufacturing a three-dimensional memory according to any one of claims 1 to 12, characterized in that, Also includes: After removing the protective portion and the first portion of the material layer, a semiconductor channel is formed in the opening.

14. A three-dimensional memory, characterized in that, The three-dimensional memory is manufactured using the method for manufacturing a three-dimensional memory as described in any one of claims 1 to 13; The three-dimensional memory includes: A stacked structure comprising alternating gate layers and a third dielectric layer; A channel structure that penetrates the stacked structure; The third dielectric layer includes a first dielectric layer and an expansion portion, wherein the expansion portion is located between the first dielectric layer and the channel structure.

15. The three-dimensional memory according to claim 14, characterized in that, In the thickness direction of the three-dimensional memory, the size of the expansion portion is smaller than or larger than the thickness of the first dielectric layer.

16. The three-dimensional memory according to claim 14, characterized in that, The side of the third dielectric layer that contacts the channel structure and the side of the gate layer that contacts the channel structure are flush. or, The side of the third dielectric layer that contacts the channel structure protrudes beyond the side of the gate layer that contacts the channel structure.

17. The three-dimensional memory according to claim 14, characterized in that, In the third dielectric layer, the first dielectric layer and the expanded portion are made of the same material, or the expanded portion contains more elements than the material of the first dielectric layer.

18. The three-dimensional memory according to claim 14, characterized in that, The material of the first dielectric layer includes silicon oxide; The material of the expansion section includes at least one of silicon oxide or silicon oxynitride.

19. A storage system, characterized in that, It includes a controller and a three-dimensional memory as described in any one of claims 14 to 18, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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