Phase change memory and its manufacturing, programming and reading methods

Abstract

Various embodiments of the present disclosure relate to phase change memories and methods for manufacturing, programming, and reading the same. A phase change memory (PCM) includes: a semiconductor body housing a selection transistor; an electrically insulating body disposed above the semiconductor body; a conductive region extending through the electrically insulating body and electrically coupled to the selection transistor; and a plurality of heater elements in the electrically insulating body. Each of the plurality of heater elements includes a first end electrically contacting a corresponding portion of the conductive region and a second end extending away from the conductive region. The PCM also includes a plurality of phase change elements extending in the electrically insulating body and including data storage areas, wherein each of the data storage areas is electrically and thermally coupled to a corresponding heater element at the second end of a corresponding heater element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Italian application No. 102020000032270, filed on December 23, 2020, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to memories, and more particularly to phase change memories and methods for manufacturing, programming and reading phase change memories. Background Art

[0004] As is known, phase-change memories use a class of materials that have the property of switching between two phases with different electrical properties associated with two different crystalline structures of the material, specifically a non-ordered amorphous phase and an ordered crystalline or polycrystalline phase. These two phases are therefore associated with resistivity values ​​that differ significantly from each other, even by two or more orders of magnitude.

[0005] Currently, elements from Group XVI of the periodic table (e.g., Te or Se, also known as chalcogenide materials or chalcogenides) can be used for phase change memory cells. For example, as shown in “Overcoming Temperature Limitations in Phase Change Memories With Optimized Ge” by P. Zuliani et al., published in IEEE Transactions on Electron Devices on November 1, 2013, x Sb y Te z "Volume 60, Issue 12, Pages 4020-4026, it is known that alloys of Ge, Sb and Te (Ge x Sb y Te z , such as Ge2Sb2Te5), which is optimized by appropriately selecting the percentages of the elements forming the alloy.

[0006] The temperature at which the phase transition occurs depends on the phase change material used. In the case of Ge2Sb2Te5 alloy, for example, below 150°C, both the amorphous and crystalline phases are stable. If the temperature is increased above 200°C, a rapid rearrangement of the crystals is observed, and the material becomes crystalline. In order to bring the chalcogenide into the amorphous state, it is necessary to increase the temperature further to the melting point (approximately 600°C) and then cool it rapidly.

[0007] Many memories are known that utilize phase change materials as elements for storing two stable states (amorphous and crystalline), each of which can be associated with a corresponding bit at "1" or "0". In these memories, a plurality of memory cells are arranged in rows and columns to form an array. Each memory cell is coupled to a corresponding selection element, which can be implemented by any switching device (such as a PN diode, a bipolar junction transistor, or a MOS transistor) and typically includes a chalcogenide region in contact with a resistive contact (also called a heater). The storage element is formed in the contact area between the chalcogenide region and the heater. The heater is connected to a conductive terminal of the selection element.

[0008] From an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through a resistive contact that is in direct contact with or functionally coupled to the chalcogenide material, thereby heating it by the Joule effect.

[0009] Various processes for producing phase-change memory cells are known from the prior art; however, these processes have certain drawbacks and limitations. In particular, in known types of PCM, each storage element is typically configured to store only one bit. To overcome this limitation, multi-level storage elements have been proposed, in which a cell can be programmed with two or more resistance values, allowing for the storage of correspondingly multiple pieces of information in the cell. This multiple resistance value can be achieved using controlled write pulses capable of setting intermediate resistance states between a "set" state and a "reset" state.

[0010] Since the resistance value drifts over time and temperature, the stability of the resistor's mid-level is a critical aspect.

[0011] Therefore, there is a need to provide a phase change memory (PCM) block, a phase change memory including a plurality of PCM blocks, a method for manufacturing a PCM block, and a method for programming and reading a PCM block that meet the above needs. Summary of the Invention

[0012] In one embodiment, a phase change memory (PCM) includes a semiconductor body housing a select transistor; an electrically insulating body disposed over the semiconductor body; a conductive region extending through the electrically insulating body and electrically coupled to the select transistor; and a plurality of heater elements within the electrically insulating body. Each of the plurality of heater elements includes a first end electrically contacting a corresponding portion of the conductive region and a second end extending away from the conductive region. The PCM further includes a plurality of phase change elements extending within the electrically insulating body and including data storage regions, wherein each of the data storage regions is electrically and thermally coupled to a corresponding heater element at a second end of the corresponding heater element.

[0013] In one embodiment, a method of manufacturing a phase-change memory device includes forming a select transistor in a semiconductor body; forming an electrically insulating body on the semiconductor body; forming a conductive region extending through the electrically insulating body, the conductive region electrically coupled to the select transistor; and forming a plurality of heater elements in the electrically insulating body. Each of the plurality of heater elements includes a first end electrically contacting a corresponding portion of the conductive region and a second end extending away from the conductive region. The method also includes forming a plurality of phase-change elements extending in the electrically insulating body and including data storage regions, each data storage region being electrically and thermally coupled to a corresponding heater element at its second end.

[0014] Another embodiment describes a method for programming a phase-change memory device, wherein the phase-change memory device includes at least one row line; a plurality of column lines; and a plurality of phase-change memory cells, each of the phase-change memory cells being coupled between the row line and a corresponding column line. The method includes, during a first operating condition associated with a first time interval, applying a reset programming voltage to the plurality of phase-change memory cells to program the plurality of phase-change memory cells to a first logic state. The method includes, during a second operating condition associated with a second time interval after the first time interval, applying a set programming voltage to selected phase-change memory cells of the plurality of phase-change memory cells to program the selected phase-change memory cells to a second logic state, wherein a maximum voltage value of the reset programming voltage is higher than a maximum voltage value of the set programming voltage.

[0015] Embodiments describe a method for reading a phase-change memory device, wherein the phase-change memory device includes a plurality of row lines; a plurality of column lines; and a plurality of phase-change memory cells, wherein each of the phase-change memory cells is coupled between a row line and a corresponding column line. The method includes biasing one of the plurality of row lines, to which a phase-change memory cell to be read is connected, to a ground reference voltage; biasing the remaining row lines of the plurality of row lines to a read voltage; biasing the plurality of column lines to the read voltage; and acquiring, via a sense amplifier, current flowing through the plurality of column lines to which the phase-change memory cell to be read is connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order that the present invention may be better understood, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0017] Figure 1A and 1B shows corresponding views of a PCM block according to an embodiment of the present invention;

[0018] Figure 1C Shown include Figure 1B A PCM memory of multiple PCM blocks, where Figure 1A shows a portion of a PCM memory (hereinafter referred to as a "PCM block") in a three-axis system of mutually orthogonal axes X, Y, and Z, and Figure 1B Shows the XZ plane Figure 1A PCM blocks, and Figure 1C shows a portion of a PCM memory comprising a plurality of PCM blocks;

[0019] Figure 2 yes Figure 1B Schematic electrical representation of the PCM block;

[0020] Figure 3 shows set and reset pulses to be applied to a PCM cell in various embodiments in order to program the PCM cell in corresponding logic states;

[0021] Figure 4A 、 4B Schematically shows Figure 1A a circuit representation of a PCM block, wherein an exemplary biasing scheme is used to program the PCM block;

[0022] Figure 5A 、 5B Schematically shows a system comprising multiple PCM blocks Figure 1C A circuit representation of a PCM memory and an exemplary biasing scheme method for programming the PCM memory;

[0023] Figure 6 Schematically shows Figure 1A A circuit representation of a PCM block and an exemplary biasing scheme for reading the PCM block;

[0024] Figures 7 to 11 Shown in various embodiments Figure 1A Subsequent method steps of the PCM block;

[0025] Figure 12 Schematically shows the Figure 1A or one or more PCM blocks of 1B or Figure 1C Embodiments of a PCM memory system; and

[0026] Figure 13 is another embodiment of a PCM block. DETAILED DESCRIPTION

[0027] Embodiments of the present invention relate to a phase change memory (PCM) block, a phase change memory comprising a plurality of PCM blocks, a method for manufacturing a PCM block, and a method for programming and reading a PCM block. In particular, the PCM block is of a physical multi-level type.

[0028] The PCM block 1 is manufactured by processing a substrate of a silicon wafer through front-end processing steps (particularly manufacturing steps of a CMOS process). In particular, formed in the substrate are insulating regions that delimit the active regions (in the Figure 1A Formed in the active region (eg, by implantation of dopant species) are the drain, source, and gate regions of the respective MOS transistors 15.

[0029] The PCM block 1 also includes a plurality of contacts 11 (e.g., tungsten) that function as electrical contacts with the aforementioned MOS transistors 15. Each contact 11 extends with electrical continuity in the direction of the Z axis. The MOS transistors 15, also known as select transistors, are operable to address the memory cells of the PCM block 1 during use.

[0030] refer to Figure 1A In one embodiment, the contact 11 extends in the form of a pillar.

[0031] A plurality of phase change material elements (hereinafter, "PCM elements") 50, for example, a chalcogenide such as a GST (Ge-Sb-Te) compound, in particular Ge2Sb2Te5, extend in strips along respective directions parallel to the Y axis; each PCM element 50 is thermally and electrically separated (or isolated) from the other PCM elements 50.

[0032] There are also a plurality of resistive zones 34 (ie heaters having the function of locally heating the PCM element 50 to trigger a selective phase change of the heated portion). Figure 1B , a plurality of resistive regions 34 extend transversely to each contact 11. Considering a contact 11, each of such a plurality of resistive regions 34 is arranged transversely to the contact 11 in question, having one end electrically coupled to the contact 11 and another end electrically and thermally coupled to a portion of the PCM element 50 designed to store logical data (i.e., designed to undergo a set or reset type phase change). In other words, a plurality (two or more) of resistive regions 34 are electrically coupled to each contact 11. More specifically, for each contact 11, a resistive region 34 is coupled between the contact 11 and the corresponding PCM element 50.

[0033] Figure 2 yes Figure 1B Schematic electrical diagram of (showing a column 11 to which the resistive region 34 and PCM element 50 are coupled). Further reference Figure 2 One end of each resistance area 34 is electrically in contact with a corresponding portion of a contact 11; the other end of each resistance area 34 is electrically coupled to a corresponding control switch M1, M2, ... MN (at Figures 1A-1CThe other electrical terminal of each control switch M1-MN is connected to the bias voltage V DD (For example, each control switch M1-MN is a MOS transistor, and the electrical terminals are a source terminal and a drain terminal. The gate terminal of each control switch M1-MN can be biased by a corresponding control signal Vb1-VbN provided by a corresponding control line to turn on / off the corresponding control switch M1-MN.)

[0034] Portions of the PCM element 50 are directly coupled to one respective resistive region 34, and such resistive regions 34 form a PCM cell that can be programmed (in logic states referred to as set and reset) and read to respectively retrieve the logic data stored in the phase change memory element.

[0035] During a write (program) operation, by activating (i.e., turning on) the control switches M1, M2, ..., MN and the selector transistor 15 to which the corresponding contacts 11 are coupled, current flows through the PCM cell, causing the corresponding resistive region 34 to generate heat through the Joule effect. During use, to program the set or reset state of the memory element, the PCM cell is biased with a write voltage by applying a voltage VDD across it. A PCM element 50 is coupled to each resistive region 34 in a manner known per se to receive heat generated by the Joule effect through the resistive region 34.

[0036] The resistance of contact 11 (in the range of a few Ω or tens of Ω) is negligible relative to the resistance (in the range of a few kΩ or tens of kΩ) of resistive region (heater) 34. Therefore, the programming voltage drops almost entirely across resistive region 34.

[0037] refer to Figure 3, shows set and reset pulses; during time interval T1, a reset pulse is generated, which is an electrical pulse suitable for programming an addressed PCM cell in logic state "0." Similarly, during time interval T2, a set pulse is generated, which is an electrical pulse suitable for programming an addressed PCM cell in logic state "1." It is known that set and reset pulses have different shapes, both in terms of duration and maximum voltage / current values. In particular, the reset voltage pulse has a duration T1 that is lower than the duration T2 of the set pulse; however, the maximum voltage value V1 (or corresponding current value) required for the reset pulse is higher than the maximum voltage value V2 (or corresponding current value) required for the set pulse. In this specification, the voltage value to be applied to PCM element 50 to program the reset state is considered to be V1 = 3V; the voltage value to be applied to PCM element 50 to program the set state is considered to be V2 = 2V; and the voltage value to be applied to PCM element 50 to not change an already programmed state is considered to be V3 < 1V (equal to 0.6V during a read operation). Obviously, these values ​​do not limit the present invention and are only used to improve the understanding of the present invention in the following disclosure. Of course, other voltage values ​​can be used depending on the specific design of the memory, the phase change material used, etc. In general, it is assumed that V1 = Vreset according to technology and design parameters, V2 is selected to be equal to 2 / 3×Vreset, and V3 is selected to be lower than or equal to 1 / 3×Vreset (in any case, lower than the "reset" threshold).

[0038] refer to Figure 4A 、 4B 5A and 5B describe the write or programming operation of the PCM block 1 and the PCM memory 1'. Figure 4A 、 4B shows a simplified electrical representation of one PCM block 1 of a PCM memory 1'; Figure 5A 、 5B A simplified electrical representation of a plurality of PCM blocks 1 is shown.

[0039] exist Figure 4A 、 4B 5A and 5B, each line r1-r3 corresponds to a respective stripe of PCM elements 50 to be biased, and each line c1-c3 corresponds to a bias line for biasing the gate terminals of select transistors 15 belonging to a different PCM block 1 and aligned along the x-axis. For ease of representation, Figure 4A 、 4B 5A and 5B only show three lines r1 - r3 and three lines c1 - c3 ; it is clear that the teaching is applicable to any number of lines.

[0040] The PCM cells are connected between lines r1-r3 and lines c1-c3 to form a matrix. For programming the PCM cells, the present invention eliminates the double writing step.

[0041] Figure 4A and 5A The voltage profile during the first write step, which is intended to write (i.e., program) the PCM cells connected to the same line r2, is shown. During this operation, all cells in the addressed line r2 are written to the "reset" or "0" state (i.e., by applying a pulse of V1=3V across them), regardless of whether such PCM cells are to be programmed to the reset state or the set state. To this end, line r2 is biased at a reference voltage of 0V (e.g., ground), while lines r1 and r3 are biased at V1=3V. In order to have the required voltage drop across the PCM cells to be programmed, all lines c1-c3 are biased at V1=3V. Consequently, only the PCM cells coupled to r2 experience a voltage drop of 3V, while the PCM cells coupled to r1 and r3 experience a voltage drop of 0V. Consequently, the PCM cells coupled between r2 and c1-c3 are all programmed to the reset state, while the remaining PCM cells retain their current state.

[0042] In the second writing step ( Figure 4B and 5B In a further embodiment (performed after the first write step), a set pulse is selectively applied to those PCM cells coupled to line r2 that are to be programmed to the set state, while maintaining the unchanged programmed reset state in those PCM cells that are to be programmed to the reset state. To this end, line r2 is biased at a reference potential of 0 V, while lines r1 and r3 are biased at an intermediate voltage of 1 V.

[0043] In this example, it is assumed that only the PCM cell coupled between r2 and c1 is to be programmed to the set state. Therefore, line c1 is biased at V2=2V so that the voltage drop across the PCM cell coupled between r2 and c1 is V2=2V, and the PCM cell is programmed to the set state.

[0044] Lines c2 and c3 are biased at an intermediate voltage of 1 V so that the voltage drop across all other PCM cells is either 0 V or 1 V, and in any case, within a voltage range that does not change the already programmed state of such cells. In this case, there is dummy power consumption, but it is not limited to the size of the PCM block 1 considered.

[0045] Specific reference Figure 5A and 5B , it will be appreciated that the desired voltage value for a column 11 can be obtained by biasing the gate terminal of the select transistor 15 using lines c1-c3 and using the threshold voltage drop to have the desired voltage on the corresponding contact 11. In this example, the gate terminal is biased at 4V, and with a threshold assumed to be equal to 1V, one can have V1=3V on the corresponding contact 11. Note that, as in Figure 5A and 5B As shown in , the other PCB blocks that are not currently being programmed are not stressed (all their lines are biased at 0V).

[0046] Figure 6 The diagram illustrates a possible reading scheme based on a schematic representation of a PCM memory having a matrix-like arrangement of rows and columns and PCM cells coupled between such rows and columns. Only the addressed PCM cells are read, while all other cells are unstressed, i.e., the voltage applied to the PCM cells not being read is zero.

[0047] The line r2 to which the PCM cell to be read is coupled is biased with a reference voltage of 0 V, while all other lines r1 and r3 are biased at V3 = 0.6 V. All lines c1-c3 are biased at V3 = 0.6 V. Consequently, a voltage drop of V3 = 0.6 V is applied only across the PCM cells coupled between line r2 and lines c1-c3; the remaining PCM cells experience zero voltage drop. It is therefore apparent that no stray current is consumed during the read operation. The actual read operation is performed by sense amplifier 16 in a manner known per se. Sense amplifier 16 performs the reading of the data stored in the PCM cells, comparing the current (or an electrical quantity related thereto) flowing in the selected PCM cell with a reference current flowing in a reference cell (so-called dual-ended reading) or with a reference current supplied by a reference current generator (so-called single-ended reading).

[0048] Note that each line c1-c3 and r1-r3 is connected to a corresponding transistor that connects / disconnects such line to / from the bias voltage. In reality, all these transistors are not equal in size (they are designed according to the maximum voltage / current they must sustain during use). In order to perform a write operation, it is necessary for current to flow through the transistors associated with lines r1-r3, thereby achieving a "row-by-row" write operation and allowing the corresponding transistors to sink only the current associated with the single PCM cell to be written. During read, the sense amplifier 16 should not be connected "row-by-row" because, as Figure 6 As shown in , line r2 "sees" the total current of all PCM cells connected to it. Taking the above into account, one solution is to write "row by row" and read "column by column", that is, to connect the sense amplifier 16 to lines c1-c3 during the read operation to read the current flowing through line r2, which is the only line selected for reading. Figure 6 The matrix shown in is symmetrical, so comparators can also be connected to lines r1-r3 to perform a read operation. Figure 5A and 5BA 3D representation of the matrix is ​​shown; in this case, comparators must be connected to lines r1-r3 to perform a read operation. In any case, it should be noted that currently known methods for reading PCM memories can be applied analogously to PCM memories according to the present application.

[0049] refer to Figure 7-11 According to an embodiment of the present invention, a method for manufacturing a PCM memory 1' is disclosed.

[0050] refer to Figure 7 A wafer 100 is provided, which includes a semiconductor body 102 (including a substrate and optionally one or more epitaxial layers on the substrate, such as silicon). A plurality of select transistors 15 are formed in the semiconductor body 102 using known techniques, such as standard CMOS processes. The select transistors 15 define the active area of ​​the semiconductor body 102. A dielectric or insulating layer 104 is formed over the semiconductor body 102, for example, by growing or depositing silicon oxide or silicon nitride.

[0051] Through a photolithography step, trenches are formed in the dielectric layer 104 that reach and expose the conductive terminals of the select transistor 15. Conductive material (e.g., metal) is deposited in the trenches to form corresponding local interconnect lines LIL or plugs 106 that are in electrical contact with the select transistor 15 (particularly with the conductive terminals, such as the drain terminal, of the select transistor 15). The plugs 106 connect the select transistor 15 to another conductive layer to be formed above the dielectric layer 104 (such as the contact 11).

[0052] Then, attach Figure 8 , steps are performed to form the resistive area 34 (heater) and the PCM element 50. To this end, a step of depositing a resistive layer (e.g., doped titanium nitride (doped TiN)) is performed on the dielectric layer 104 and the plug 106. This step is followed by forming a phase change material layer in a known manner, for example by depositing a chalcogenide, such as a GST (Ge-Sb-Te) compound, such as Ge2Sb2Te5. Other phase change materials may be used. The formation of the PCM layer is performed above the resistive layer.

[0053] The resistive layer, and thus the PCM layer, is patterned, for example, by photolithography and etching, to form a stack comprising resistive regions 34 and the previously described PCM element 50, having a shape and extension according to the design of the PCM memory 1. It should be noted that the PM element 50 is a continuous strip along the Y-axis, while the resistive regions 34 extend at selective areas of the PCM element 50 (i.e., at areas of the PCM element 50 designed to form memory cells). Between one resistive region 34 and another resistive region 34, extending along the Y-axis of the PM element 50, a dielectric or insulating material may be deposited.

[0054] A protective layer 110 (eg, of silicon nitride) is formed over the resistive region 34 and the PCM element 50. The protective layer 110 may also extend over the dielectric layer 104 and over portions of the plug 106 not covered by the resistive layer 34.

[0055] Then, in Figure 9 In the embodiment of the present invention, another dielectric or insulating layer 112 is formed (e.g., deposited) over the resistive region 34, the PCM element 50, the protective layer 110, the dielectric layer 104, and the plugs 106. A CMP (chemical mechanical polishing) step is performed on the dielectric layer 112. Trenches are opened through the dielectric layer 112 and the protective layer 110 to the region of the plugs 106 that is transverse to the stack formed by the resistive region 34 and the PCM layer 50. The trenches are then filled with a conductive material (particularly a metal, more specifically tungsten). Thus, plugs 116 are formed that extend completely through the dielectric layer 112 and are in electrical contact with the corresponding plugs 106.

[0056] Then, in Figure 10 In the embodiment of the present invention, steps are performed to deposit and pattern a metal layer 118 over the dielectric layer 112. The metal layer 118 is patterned in a manner to define a plurality of local interconnects 118', each of which is electrically connected to a corresponding plug 116.

[0057] Then copy Figure 10 (except for forming transistor 15 and plug 106), such as Figure 11 shown.

[0058] refer to Figure 11 The previously described steps are repeated to form additional stacks of resistive regions 34 and PCM elements 50, as well as additional plugs 120 (similar to plugs 116 described previously) above local interconnects 118′ and in electrical contact with corresponding local interconnects 118′. A dielectric or insulating layer 121 is formed similarly to dielectric layer 112, and additional metal interconnects 122 (similar to metal interconnects 118′) are formed on dielectric layer 121.

[0059] Specifically, use the attached Figure 11 The stack, designated by reference numeral 128 in FIG. 1 , comprises a plug 106 extending in electrical contact with one of the select transistors 15, a plug 116 extending in electrical contact with such a plug 106, a metal interconnect 118′ extending in electrical contact with such a plug 116, a further plug 120 and a further metal interconnect 122 extending in electrical contact with such a plug 120, forming (at least in part) one of the contacts 11 previously described. A plurality of PCM elements 50 (each including a respective heater 34) extend one above the other along the Z axis and are electrically connected to the same stack 128 (contact 11), as shown in FIG. Figures 1A-1C As in the embodiment of .

[0060] According to the design of PCM memory 1, Figure 11 The steps can be replicated as many times as needed.

[0061] Figure 12 A portion of a system 200 is shown that can be implemented in various devices, such as a PDA, a portable computer, a phone, an image camera, a video camera, etc. The system 200 may include one or more of a controller 210 (e.g., a microprocessor), input / output devices 220 (e.g., a keypad and a display), a chip provided in an integrated form, a PCM memory 1', a wireless interface 240, and a random access memory (RAM) 260 connected together via a bus system 250. According to one embodiment, the system 200 may be powered by a battery 280 or alternatively by a mains power supply. Obviously, the scope of the present disclosure is not limited to including Figure 12 For example, one or more of random access memory (RAM) 260, wireless interface 240, battery 280, and input / output device 220 may be omitted.

[0062] The advantages of the present disclosure clearly appear from the foregoing description.

[0063] For example, the area per bit of the PCM memory according to the present invention is significantly reduced compared to known PCM memories. The increase in level also increases the area gain depending on the number of stacked cells.

[0064] Finally, it should be clear that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0065] For example, Figure 13 FIG. 3 shows a PCM block 300 according to another embodiment of the present invention. Figure 1B The same elements of the PCM block 1 are identified by the same reference numerals. Figure 13 As shown in FIG, a further resistive zone (heater) 34′ extends away from the contact 11 on the side of the contact 11 opposite the side facing the resistive zone 34. The resistive zone 34′ has similar properties to the resistive zone 34 and is manufactured accordingly during the same process steps in a manner apparent to a person skilled in the art. Similar to the PCM element 50, the PCM element 50 is electrically and thermally coupled to the resistive zone 34′. The functionality of the PCM block 300 is identical to that of the PCM block 1 and will not be described further.

Claims

1. A phase change memory (PCM), comprising: a semiconductor body housing a select transistor; an electrically insulating body disposed over the semiconductor body; a conductive region extending through the electrically insulating body and electrically coupled to the select transistor; a plurality of heater elements in the electrically insulative body, each heater element of the plurality of heater elements including a first end in electrical contact with a corresponding portion of the electrically conductive region and a second end extending away from the electrically conductive region; a plurality of phase change material elements extending within the electrically insulating body and including data storage regions, each of the data storage regions being electrically and thermally coupled to a respective heater element at the second end thereof, wherein each of the plurality of phase change material elements is a continuous strip along a direction parallel to a major surface of the semiconductor body, and wherein subsets of the plurality of heater elements are disposed at different locations along each of the continuous strips and are separated by insulating regions; as well as a sealing layer of dielectric or insulating material covering side walls of a stack including one of the heater elements and a corresponding one of the data storage areas coupled thereto, the sealing layer covering a top major surface of the corresponding one of the data storage areas, wherein a portion of the electrically insulating body covers the sealing layer above the stack.

2. The PCM of claim 1 , wherein the electrically insulating body comprises a plurality of electrically insulating layers, each heater element and associated data storage area extending in a respective one of the electrically insulating layers.

3. The PCM of claim 2, wherein the conductive region comprises a plurality of electrically interconnected plugs, each plug extending within a respective one of the electrically insulating layers.

4. The PCM of claim 3 , wherein the plurality of electrically insulating layers comprises one or more stacks of overlapping electrically insulating layers, each stack comprising a respective first electrically insulating layer on a respective second electrically insulating layer, and wherein for each stack a respective interconnecting wire extends between the first electrically insulating layer and the second electrically insulating layer, The interconnect wire is electrically connected to a plug extending in the first electrically insulating layer and a plug extending in the second electrically insulating layer, thereby forming an electrically conductive path between the first electrically insulating layer and the second electrically insulating layer.

5. The PCM of claim 4, wherein the interconnecting wire is further electrically connected to the heater element extending in the first electrically insulating layer. 6 . The PCM of claim 1 , wherein the heater elements are aligned with each other along a vertical direction normal to the major surface of the semiconductor body.

7. The PCM according to claim 1, wherein the conductive zone has a main extension along a first direction orthogonal to the main surface of the semiconductor body, each heater element being arranged transversely to the conductive zone.

8. The PCM of claim 1 , further comprising a plurality of switching transistors, each switching transistor having its own first conductive terminal coupled to a corresponding phase change material element, its own second conductive terminal coupled to a bias potential, and its own control terminal, wherein the selection transistor comprises its own first conduction terminal coupled to the conduction region, its own second conduction terminal coupled to a reference potential, and its own control terminal, The control terminal of the select transistor and the control terminal of the switch transistor are operable to selectively connect a corresponding heater element and the associated phase change material element between the reference potential and the bias potential.

9. The PCM of claim 1 , wherein the PCM is integrated into a chip including a bias circuit arrangement, the bias circuit arrangement comprising: a programming stage comprising a voltage generator configured to cause a set or reset programming current to flow through selected heater elements to generate heat by the Joule effect so as to induce a controlled phase change of an associated said data storage region of said phase change material element; as well as The read stage includes a plurality of sense amplifiers, each sense amplifier being coupled to a corresponding data storage region to read a current flowing through the corresponding data storage region during a read operation of the block of PCM.

10. A method for manufacturing a phase change memory, the method comprising: forming a select transistor in the semiconductor body; forming an electrically insulating body on the semiconductor body; forming a conductive region through the electrically insulating body, the conductive region being electrically coupled to the select transistor; forming a plurality of heater elements in the electrically insulating body, each heater element including a first end in electrical contact with a corresponding portion of the conductive region and a second end extending away from the conductive region; forming a plurality of phase change material elements extending within the electrically insulating body and including data storage regions, each data storage region being electrically and thermally coupled to a respective heater element at the second end thereof, wherein each phase change material element of the plurality of phase change material elements is a continuous strip along a direction parallel to a major surface of the semiconductor body, and wherein subsets of the plurality of heater elements are disposed at different locations along each of the continuous strips and are separated by insulating regions; as well as a sealing layer of dielectric or insulating material covering side walls of a stack including one of the heater elements and a corresponding one of the data storage areas coupled thereto, the sealing layer covering a top major surface of the corresponding one of the data storage areas, wherein a portion of the electrically insulating body covers the sealing layer above the stack.

11. The method of claim 10, wherein forming the electrically insulating body comprises: A plurality of electrically insulating layers are formed, and wherein forming the heater elements and the data storage regions includes burying each heater element and associated data storage region in a respective one of the electrically insulating layers.

12. The method of claim 11, wherein forming the conductive region comprises: Plugs are formed in a corresponding one of the electrically insulating layers, and each of the plugs is electrically connected to each other.

13. The method of claim 12, wherein forming the plurality of electrically insulating layers comprises: forming one or more stacks of overlapping electrically insulating layers, each stack comprising a respective first electrically insulating layer on a respective second electrically insulating layer, The method further comprises: for each stack, forming a corresponding interconnect wire between the first electrically insulating layer and the second electrically insulating layer, The interconnect wire is formed to electrically connect with the plug extending in the first electrically insulating layer and the plug extending in the second electrically insulating layer, thereby forming a conductive path between the first electrically insulating layer and the second electrically insulating layer.

14. The method of claim 13, wherein the interconnect wire is further electrically connected to the heater element extending in the first electrically insulating layer. 15 . The method of claim 10 , wherein the heater elements are formed aligned with each other along a vertical direction normal to the main surface of the semiconductor body. 16 . The method of claim 10 , wherein the conductive region is formed with a main extension along a first direction orthogonal to the main surface of the semiconductor body, each heater element being formed transversely to the conductive region.

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