Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel includes a substrate, a pixel structure, and a driving circuit; the pixel structure includes a cathode; the driving circuit includes a data signal line and a virtual data signal line, the data signal line and the virtual data signal line are located on the side of the cathode close to the substrate, and both overlap with the cathode; the signal on the data signal line and the signal on the virtual data signal line have opposite phases; the display panel also includes a touch electrode, the touch electrode is located on the side of the cathode away from the substrate, and at least partially overlaps with the cathode. The above solution reduces or even eliminates the display noise generated by the above signal jump. In addition, the influence of display noise on touch recognition is reduced or even eliminated, ensuring the normal operation of touch recognition.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Typically, the cathode of an organic light emitting diode (OLED) display panel is a flat electrode. The overlap of the data signal line with the cathode creates a certain amount of parasitic capacitance. Transitions in the data signal transmitted on the data signal line can couple to the cathode, causing display noise.

[0003] Furthermore, as display panel size increases, so does display noise. In touch-enabled display panels, particularly those using Flexible Multi-Layer On-Cell (FMLOC) technology, the proximity between the touch electrode and cathode creates a significant load on the second parasitic capacitor formed between them. This allows display noise to couple to the touch electrode via the second parasitic capacitor. In some images with display noise, the intensity of the display noise approaches that of a finger touch signal or an active pen, causing touch recognition failure. Summary of the Invention

[0004] The present application aims to provide a display panel, a touch display panel, and a display device, which are used to at least reduce display noise.

[0005] In a first aspect, the present invention provides a display panel comprising: a substrate, a pixel structure, and a driving circuit;

[0006] The pixel structure includes a cathode;

[0007] The driving circuit includes a data signal line and a dummy data signal line, wherein the data signal line and the dummy data signal line are located on a side of the cathode close to the substrate and overlap with the cathode; the signal on the data signal line and the signal on the dummy data signal line have opposite phases;

[0008] The display panel further includes a touch electrode. The touch electrode is located on a side of the cathode away from the substrate and at least partially overlaps with the cathode.

[0009] As an implementable manner, an inverter is further included, wherein the input end of the inverter is connected to the data signal line, the output end of the inverter is connected to the virtual data signal line, and the inverter is used to invert the signal on the data signal line and transmit it to the virtual data signal line.

[0010] As an implementation method, the inverter includes a first switching element and a second switching element;

[0011] The control electrode of the first switching element and the control electrode of the second switching element are connected to each other and to the data signal line;

[0012] The first electrode of the first switching element is connected to a first voltage, the second electrode of the first switching element is connected to the first electrode of the second switching element, and is connected to the virtual data signal line;

[0013] The second electrode of the second switching element is connected to a second voltage;

[0014] The first voltage is higher than the second voltage, and the first switch element is a P-type switch element, and the second switch element is an N-type switch element.

[0015] As an achievable method, the display panel includes a display area and a non-display area surrounding the display area; the inverter is arranged in the non-display area; the number of the data signal lines is greater than or equal to the number of the virtual data signal lines, and each of the virtual data signal lines is connected to the inverter in a one-to-one correspondence.

[0016] As an implementable manner, the non-display area is provided with a first voltage line for providing a first voltage to the inverter, and a second voltage line for providing a second voltage, and the first voltage line and the second voltage line are staggered.

[0017] As an implementable manner, the display panel includes a display area and a non-display area surrounding the display area; the display area includes a plurality of pixels, and the inverter is provided corresponding to each pixel position.

[0018] As an implementable manner, the first voltage routing line and the second voltage routing line are staggered, specifically:

[0019] The first voltage routing includes first voltage sub-routings arranged side by side along a first direction and second voltage sub-routings arranged side by side along a second direction;

[0020] The second voltage routing includes a third voltage sub-routing arranged side by side along the first direction and a fourth voltage sub-routing arranged side by side along the second direction;

[0021] In the first direction, the first voltage sub-routes and the third voltage sub-routes are alternately arranged;

[0022] In the second direction, the second voltage sub-routing and the fourth voltage sub-routing are alternately arranged;

[0023] The first direction is perpendicular to the second direction.

[0024] As an implementable manner, the display area is provided with a first voltage line for providing a first voltage to the inverter, and a second voltage line for providing a second voltage, and the first voltage line and the second voltage line are staggered.

[0025] As an implementable manner, the first voltage routing is a VDD voltage routing, and the second voltage routing is a GND voltage routing or a VSS voltage routing.

[0026] As an implementation manner, the inverter includes an active layer, the active layer includes a first active pattern and a second active pattern, one of the first active pattern and the second active pattern is a P-type active pattern, and the other is an N-type active pattern;

[0027] A first gate insulating layer is provided on the active layer;

[0028] A gate layer is provided on the first gate insulating layer;

[0029] A second gate insulating layer is provided on the gate layer;

[0030] An interlayer dielectric layer is provided on the second gate insulating layer;

[0031] A metal wiring layer is provided on the interlayer dielectric layer, the metal wiring layer including a first metal wiring pattern, a second metal wiring pattern, and a third metal wiring pattern; a first electrode of the first active pattern is connected to the first metal wiring pattern, a second electrode of the first active pattern and a first electrode of the second active pattern are both connected to the second metal wiring pattern, and a second electrode of the second active pattern is connected to the third metal wiring pattern;

[0032] The first metal wiring pattern is connected to a first voltage, the second active pattern is connected to the dummy data signal line, the third metal wiring pattern is connected to a second voltage, and the gate layer is connected to the data signal line.

[0033] As an implementable manner, an encapsulation layer is provided on the cathode, the touch electrode is provided on a side of the encapsulation layer away from the cathode, and the touch electrode includes a first touch electrode and a second touch electrode that cross and are insulated from each other.

[0034] In a second aspect, the present invention provides a display device comprising the above-mentioned display panel.

[0035] In the above solution, because a dummy data signal (Dummy Source) line is provided and overlaps with the cathode, the signal on the data signal line and the signal on the dummy data signal line have opposite phases. Therefore, when the signal on the data signal line transitions, the signal provided on the dummy data signal line transitions in the opposite direction. The potentials of these two oppositely transitioned signals coupled to the cathode cancel each other out, thereby reducing or even eliminating the display noise generated by the signal transitions. This, in turn, reduces or even eliminates the impact of display noise on touch recognition, ensuring the proper functioning of touch recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of an inverter provided in an embodiment of the present invention;

[0039] Figure 3 A schematic structural diagram of a display panel provided in another embodiment of the present invention;

[0040] Figure 4 A schematic structural diagram of an inverter provided in an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a driving signal according to an embodiment of the present invention;

[0042] Figure 6 A comparison diagram of whether display noise is eliminated in the embodiment of the present invention and in the prior art is shown. DETAILED DESCRIPTION

[0043] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0044] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] See also Figures 1-6As shown, an embodiment of the present invention shows a display panel, which may be, for example but not limited to, an OLED display panel or a quantum dot light emitting diode (QLED). The display panel includes a substrate, a pixel structure, and a driving circuit. The driving circuit is disposed on the substrate, and the pixel structure is disposed on the driving circuit.

[0046] The pixel structure includes a cathode 8; for example, the pixel structure includes an anode, a cathode 8, and a light-emitting material disposed between the anode and the cathode 8; the cathode 8 may be a planar electrode, and different pixels share the planar electrode.

[0047] The driving circuit includes a data signal line 1 and a virtual data signal line 2, wherein the data signal line 1 and the virtual data signal line 2 are located on the side of the cathode 8 close to the substrate and both overlap with the cathode 8; the signal Source on the data signal line 1 and the signal Dummy sourse on the virtual data signal line 2 are in opposite phase; the virtual data signal line 2 mentioned here refers to a signal that does not directly participate in the display driving of the display panel and is mainly used to transmit a signal Dummy sourse with an opposite phase to the signal Source on the data signal line 1; since the data signal line 1 and the virtual data signal line 2 both overlap with the cathode 8, there is a parasitic capacitance between the data signal line 1 and the virtual data signal line 2 and the cathode 8. When the signal Source on the data signal line 1 jumps, the signal Dummy sourse provided on the virtual data signal line 2 jumps in the opposite direction. The two oppositely jumping signals, coupled to the potential of the cathode 8, cancel each other out, thereby reducing or even eliminating the display noise generated by the above-mentioned signal jump. How much the display noise can be reduced or whether it can be eliminated can be determined by controlling the amplitude of the signal Dummy sourse on the virtual data signal line 2 according to actual conditions.

[0048] The display panel also includes a touch electrode, which is located on the side of cathode 8 away from the substrate and at least partially overlaps cathode 8. When the signal Source on data signal line 1 transitions, the potential coupled to cathode 8 is offset, thereby reducing or even eliminating the impact of display noise on touch recognition, ensuring normal operation of touch recognition.

[0049] The data signal line 1 and the virtual data signal line 2 can be connected to the same signal source, such as the same driver integrated circuit (IC). In this case, the inverter 3 described below can be connected between the virtual data signal line 2 and the driver IC4 to achieve opposite phases of the signal on the data signal line 1 and the signal on the virtual data signal line 2. Of course, in other cases, the data signal line 1 and the virtual data signal line 2 can be connected to different signal sources, as long as the phases of the signal on the data signal line 1 and the signal on the virtual data signal line 2 are opposite, such as when the data signal line 1 is connected to the driver IC4 and the virtual data signal line 2 is connected to a signal generator that can emit a signal that is opposite to the signal on the data signal line 1.

[0050] As an achievable method, Figure 2 As shown, the display device further includes an inverter 3, wherein the input terminal IN of the inverter 3 is connected to the data signal line 1, and the output terminal OUT of the inverter 3 is connected to the virtual data signal line 2. The inverter 3 is used to invert the signal on the data signal line 1 and transmit it to the virtual data signal line 2. By providing the inverter 3, the signal on the data signal line 1 can be inverted and transmitted to the virtual data signal line 2, so that the signal on the data signal line 1 and the signal on the virtual data signal line 2 are highly synchronized, and since the two are in opposite directions, the synchronized high and low levels cancel each other out, thereby better reducing or even eliminating the display noise generated by the signal jump on the data signal line 1.

[0051] As an achievable method, Figure 2 As shown, the inverter 3 includes a first switching element T1 and a second switching element T2. Each of the first and second switching elements T1 and T2 can be a transistor. These transistors can be devices with similar characteristics, such as thin film transistors (TFTs), triodes, or metal oxide semiconductor field effect transistors (MOSFETs). They can be either N-type or P-type transistors. The choice of transistor type primarily considers their conduction mode: N-type transistors are conducted at a low level, while P-type transistors are conducted at a high level. To distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other as the second electrode. The control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; alternatively, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0052] The control electrode of the first switch element T1 and the control electrode of the second switch element T2 are connected to each other and connected to the data signal line 1;

[0053] The first electrode of the first switch element T1 is connected to a first voltage, the second electrode of the first switch element T1 is connected to the first electrode of the second switch element T2 and is connected to the virtual data signal line 2;

[0054] The second electrode of the second switch element T2 is connected to a second voltage;

[0055] The first voltage is higher than the second voltage, and the first switch element T1 is a P-type switch element, and the second switch element T2 is an N-type switch element.

[0056] Since the first voltage is higher than the second voltage, and the first switch element T1 is a P-type switch element and the second switch element T2 is an N-type switch element, when the signal on the data signal line 1 is at a high level, the second switch element T2 is turned on, the first switch element T1 is turned off, and the inverter 3 outputs a low level to the virtual data signal line 2; conversely, when the signal on the data signal line 1 is at a low level, the second switch element T2 is turned off, the first switch element T1 is turned on, and the inverter 3 outputs a high level to the virtual data signal line 2; thereby achieving the purpose of having the signal on the data signal line 1 and the signal on the virtual data signal line 2 have opposite phases.

[0057] As an implementation, the display panel includes a display area AA and a non-display area BB surrounding the display area AA; the inverter 3 is disposed in the non-display area BB; the number of the data signal lines 1 is greater than or equal to the number of the dummy data signal lines 2, and each of the dummy data signal lines 2 is connected to the inverter 3 in a one-to-one correspondence. The inverter 3 is disposed in the non-display area BB, for example, but not limited to, within a fan-out area. This area has a large free space, such as a large spacing between various signal lines, and lacks pixel structures. Therefore, a larger inverter 3 can be fabricated. If both the first switching element T1 and the second switching element T2 are TFTs, the aspect ratio of the TFTs fabricated here can reach 160 / 4 μm, or even larger. Increasing the size of the inverter 3 can increase its load capacity.

[0058] Generally, each column of pixels corresponds to a data signal line 1, and each column of pixels may correspond to a virtual data signal line 2, or a plurality of columns of pixels may correspond to a virtual data signal line 2. Preferably, each column of pixels may correspond to a virtual data signal line 2, so that the potential induced on the cathode 8 by the signal transition on each data signal line 1 can be offset, thereby enhancing the effect of reducing display noise.

[0059] As an implementation method, the non-display area BB is provided with a first voltage trace 6 for providing a first voltage to the inverter 3, and a second voltage trace 5 for providing a second voltage, and the first voltage trace 6 and the second voltage trace 5 are arranged in a staggered manner. For example, but not limited to, the first voltage trace 6 and the second voltage trace 5 can both extend along the direction of a row of pixels. The staggered arrangement herein means that, in an orthographic projection perpendicular to the display surface of the display panel, the first voltage trace 6 and the second voltage trace 5 do not overlap, that is, the first voltage trace 6 and the second voltage trace 5 are arranged side by side with an interval in the direction of a column of pixels.

[0060] As an achievable method, Figure 3 As shown, the display panel includes a display area AA and a non-display area BB surrounding the display area AA; the display area AA includes a plurality of pixels, and an inverter 3 is provided at each pixel position. Providing an inverter 3 at each pixel position can reduce the difference in signal strength at different positions on the same virtual data signal line 2.

[0061] As an implementable method, the display area AA is provided with a first voltage line 6 for providing a first voltage to the inverter 3, and a second voltage line 5 for providing a second voltage. The first voltage line 6 and the second voltage line 5 are staggered to reduce the parasitic capacitance generated by the two.

[0062] Specifically, the staggered arrangement of the first voltage trace 6 and the second voltage trace 5 mentioned herein may refer to the following: within the display area AA, the first voltage trace 6 includes a first voltage sub-trace 61 arranged side by side along a first direction and a second voltage sub-trace 62 arranged side by side along a second direction; the second voltage trace 5 includes a third voltage sub-trace 51 arranged side by side along the first direction and a fourth voltage sub-trace 52 arranged side by side along the second direction; in the first direction, the first voltage sub-trace 61 and the third voltage sub-trace 51 are arranged alternately; in the second direction, the second voltage sub-trace 62 and the fourth voltage sub-trace 52 are arranged alternately; and the first direction is perpendicular to the second direction. For example, but not limited to, the first direction is the row direction of pixels, and the second direction is the column direction of pixels. Of course, the first direction may also be the column direction of pixels, and the second direction may be the row direction of pixels. The number of first voltage sub-routes 61, second voltage sub-routes 62, third voltage sub-routes 51, and fourth voltage sub-routes 52 matches the number of rows and columns of pixels in display area AA, ensuring that the inverter 3 corresponding to each pixel position is connected to its corresponding first voltage route 6 and second voltage route 5. To further reduce the difference in signal strength at different positions on the same virtual data signal line 2, the first voltage route 6 and the second voltage route 5 are metal routes with low resistivity, such as composite layered metal routes of Ti / Al / Ti, to reduce the voltage drop across the first voltage route 6 and the second voltage route 5.

[0063] As an implementable manner, the first voltage line 6 is a VDD voltage line, and the second voltage line 5 is a GND voltage line or a VSS voltage line.

[0064] As an achievable method, Figure 4 As shown, the inverter 3 includes an active layer, which includes a first active pattern 29 and a second active pattern 30. One of the first active pattern 29 and the second active pattern 30 is a P-type active pattern, and the other is an N-type active pattern. Both the first active pattern 29 and the second active pattern 30 may include semiconductor regions 292 and 302, and conductive regions 291, 293, 301, and 303 located on either side of the semiconductor regions. The conductive regions 291, 293, 301, and 303 are the first and second poles of the corresponding active pattern, respectively. In practical applications, a buffer layer 23, a polyimide (PI) layer 22, and a substrate 21 may also be disposed beneath the active layer.

[0065] A first gate insulating layer 24 is provided on the active layer;

[0066] A gate layer 27 is provided on the first gate insulating layer 24;

[0067] A second gate insulating layer 25 is provided on the gate layer 27;

[0068] An interlayer dielectric layer 26 is provided on the second gate insulating layer 25;

[0069] A metal wiring layer 28 is provided on the interlayer dielectric layer 26. The metal wiring layer 28 includes a first metal wiring pattern 281, a second metal wiring pattern 282, and a third metal wiring pattern 283. The first electrode of the first active pattern 29 is connected to the first metal wiring pattern 281. The second electrode of the first active pattern 29 and the first electrode of the second active pattern 30 are both connected to the second metal wiring pattern 282. The second electrode of the second active pattern 30 is connected to the third metal wiring pattern 283.

[0070] The first metal wiring pattern 281 is connected to a first voltage, the second active pattern 30 is connected to the dummy data signal line 2 , the third metal wiring pattern 283 is connected to a second voltage, and the gate layer 27 is connected to the data signal line 1 .

[0071] As an implementation manner, an encapsulation layer is provided on the cathode 8 , and the touch electrode is provided on a side of the encapsulation layer away from the cathode 8 . The touch electrode includes a first touch electrode and a second touch electrode that are crossed and insulated from each other.

[0072] The invention is exemplified below with a specific solution, which should not be understood as the sole limitation of the invention.

[0073] Example 1

[0074] At least see Figure 1 、 Figure 2 and Figure 4 As shown, the display panel includes a substrate, a pixel structure, and a driving circuit. The driving circuit is arranged on the substrate, and the pixel structure is arranged on the driving circuit. Depending on the actual situation, other layered structures can be arranged between the substrate, the pixel structure, and the driving circuit.

[0075] The display panel includes a display area AA and a non-display area BB surrounding the display area AA. A pixel structure is provided in the display area AA. The pixel structure includes an anode, a cathode 8, and a light-emitting material disposed between the anode and cathode 8; the cathode 8 is a planar electrode.

[0076] The driving circuit includes a data signal line 1 and a dummy data signal line 2 . Each column of pixels corresponds to a data signal line 1 and a dummy data signal line 2 . Both the data signal line 1 and the dummy data signal line 2 overlap with the cathode 8 .

[0077] The non-display area BB is provided with an inverter 3 corresponding to each virtual data signal line 2. The inverter 3 includes a first switching element T1 and a second switching element T2. Here, the first switching element T1 and the second switching element T2 are both TFTs. The control electrode of the first switching element T1 and the control electrode of the second switching element T2 are interconnected and connected to the data signal line 1. In other words, the input terminal IN of the inverter 3 is connected to the data signal line 1, and the data signal line 1 is connected to the driver IC 4. The first electrode of the first switching element T1 is connected to the VDD voltage, and the second electrode of the first switching element T1 and the first electrode of the second switching element T2 are interconnected and connected to the virtual data signal line 2. In other words, the output terminal OUT of the inverter 3 is connected to the virtual data signal line 2. The second electrode of the second switching element T2 is grounded (GND). The first switching element T1 is a P-type TFT, and the second switching element T2 is an N-type TFT.

[0078] Among them, the specific structure of the inverter 3 may include an active layer, the active layer includes a first active pattern 29 and a second active pattern 30, the first active pattern 29 is a P-type active pattern, and the second active pattern 30 is an N-type active pattern; the first active pattern 29 and the second active pattern 30 may both include a semiconductor region and a conductive region located on both sides of the semiconductor region, and the two conductive regions are the first pole and the second pole of the corresponding active pattern, respectively. A first gate insulating layer 24 is provided on the active layer; a gate layer 27 is provided on the first gate insulating layer 24; a second gate insulating layer 25 is provided on the gate layer 27; an interlayer dielectric layer 26 is provided on the second gate insulating layer 25; a metal wiring layer 28 is provided on the interlayer dielectric layer 26, and the metal wiring layer 28 includes a first metal wiring pattern 281, a second metal wiring pattern 282 and a third metal wiring pattern 283; the first electrode of the first active pattern 29 is connected to the first metal wiring pattern 281, the second electrode of the first active pattern 29 and the first electrode of the second active pattern 30 are both connected to the second metal wiring pattern 282, and the second electrode of the second active pattern 30 is connected to the third metal wiring pattern 283; the first metal wiring pattern 281 is connected to the VDD voltage, the second active pattern 30 is connected to the virtual data signal line 2, the third metal wiring pattern 283 is grounded, and the gate layer 27 is connected to the data signal line 1.

[0079] An encapsulation layer is provided on the cathode 8. Touch electrodes are provided on the side of the encapsulation layer facing away from the cathode 8. The touch electrodes include first and second touch electrodes that intersect and are insulated from each other. The first touch electrodes can be touch drive electrodes Tx, and the second touch electrodes can be touch sensing electrodes Rx.

[0080] like Figure 5 、 Figure 6 As shown, the effect of this solution in eliminating display noise is explained by switching between black and white lines. The black and white line switching here can be understood as the display panel switching between grayscale 0 and grayscale 255. Correspondingly, the signal Source on the data signal line 1 switches between high and low potentials. Since there is a first parasitic capacitor 7 between the data signal line 1 and the cathode 8, when the signal on the data signal line 1 switches between high and low potentials, an induced potential (the induced potential is noise) appears on the cathode 8. Since there is a second parasitic capacitor 9 between the cathode 8 and the touch electrode, the potential induced on the cathode 8 will cause the touch electrode to induce a certain potential, thereby affecting the normal operation of touch recognition. Figure 6In the present application, a virtual data signal line 2 is provided to transmit a signal Dummysource, which is opposite in phase to that on the data signal line 1, to offset the induced potential on the cathode 8 when the signal Source on the data signal line 1 switches between high and low potentials. That is, after the optimization of the present application, the cathode 8 and the touch electrode are respectively at the same potential, that is, their potentials are displayed as the straight line in the figure, thereby achieving the purpose of reducing or eliminating display noise and thus ensuring the normal operation of touch recognition.

[0081] Example 2

[0082] like Figure 3 As shown, the main difference between this example and the above-mentioned Example 1 is that an inverter 3 is provided corresponding to each pixel position, and a first voltage line 6 for providing a first voltage to each inverter 3 and a second voltage line 5 for providing a second voltage are provided in the display area AA, and the first voltage line 6 and the second voltage line 5 are staggered, wherein the first voltage is the VDD voltage and the second voltage is the ground voltage.

[0083] The first voltage trace 6 includes a first voltage sub-trace 61 arranged side by side in a first direction and a second voltage sub-trace 62 arranged side by side in a second direction; the second voltage trace 5 includes a third voltage sub-trace 51 arranged side by side in the first direction and a fourth voltage sub-trace 52 arranged side by side in the second direction; in the first direction, the first voltage sub-trace 61 and the third voltage sub-trace 51 are arranged alternately; in the second direction, the second voltage sub-trace 62 and the fourth voltage sub-trace 52 are arranged alternately; the first direction is perpendicular to the second direction. That is, in this example, the first voltage trace 6 and the second voltage trace 5 are staggered, including the first voltage sub-trace 61 and the third voltage sub-trace 51 being arranged alternately, and the second voltage sub-trace 62 and the fourth voltage sub-trace 52 being arranged alternately.

[0084] In a second aspect, the present invention provides a display device comprising the above-mentioned display panel.

[0085] The display device in this embodiment can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, or the like.

[0086] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0087] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A display panel, characterized in that: include: Substrate, pixel structure and driving circuit; The pixel structure includes a cathode; The driving circuit includes a data signal line and a dummy data signal line, wherein the data signal line and the dummy data signal line are located on a side of the cathode close to the substrate and overlap with the cathode; the signal on the data signal line and the signal on the dummy data signal line have opposite phases; The display panel further includes a touch electrode. The touch electrode is located on a side of the cathode away from the substrate and at least partially overlaps with the cathode.

2. The display panel according to claim 1, wherein: It also includes an inverter, the input end of the inverter is connected to the data signal line, the output end of the inverter is connected to the virtual data signal line, and the inverter is used to invert the signal on the data signal line and transmit it to the virtual data signal line.

3. The display panel according to claim 2, wherein: The inverter includes a first switching element and a second switching element; The control electrode of the first switching element and the control electrode of the second switching element are connected to each other and to the data signal line; The first electrode of the first switching element is connected to a first voltage, the second electrode of the first switching element is connected to the first electrode of the second switching element, and is connected to the virtual data signal line; The second electrode of the second switching element is connected to a second voltage; The first voltage is higher than the second voltage, and the first switch element is a P-type switch element, and the second switch element is an N-type switch element.

4. The display panel according to claim 2 or 3, wherein: The display panel includes a display area and a non-display area surrounding the display area; the inverter is arranged in the non-display area; the number of the data signal lines is greater than or equal to the number of the virtual data signal lines, and each of the virtual data signal lines is connected to the inverter in a one-to-one correspondence.

5. The display panel according to claim 4, wherein: The non-display area is provided with a first voltage line for providing a first voltage to the inverter, and a second voltage line for providing a second voltage, and the first voltage line and the second voltage line are staggered.

6. The display panel according to claim 2 or 3, characterized in that: The display panel includes a display area and a non-display area surrounding the display area; the display area includes a plurality of pixels, and the inverter is provided corresponding to each pixel position.

7. The display panel according to claim 6, wherein: The display area is provided with a first voltage line for providing a first voltage to the inverter, and a second voltage line for providing a second voltage, and the first voltage line and the second voltage line are staggered.

8. The display panel according to claim 7, wherein: The first voltage wiring and the second voltage wiring are staggered, specifically: The first voltage routing includes first voltage sub-routings arranged side by side along a first direction and second voltage sub-routings arranged side by side along a second direction; The second voltage routing includes a third voltage sub-routing arranged side by side along the first direction and a fourth voltage sub-routing arranged side by side along the second direction; In the first direction, the first voltage sub-routes and the third voltage sub-routes are alternately arranged; In the second direction, the second voltage sub-routing and the fourth voltage sub-routing are alternately arranged; The first direction is perpendicular to the second direction.

9. The display panel according to claim 5, 7 or 8, wherein: The first voltage line is a VDD voltage line, and the second voltage line is a GND voltage line or a VSS voltage line.

10. The display panel according to claim 2 or 3, characterized in that: The inverter includes an active layer, the active layer includes a first active pattern and a second active pattern, one of the first active pattern and the second active pattern is a P-type active pattern, and the other is an N-type active pattern; A first gate insulating layer is provided on the active layer; A gate layer is provided on the first gate insulating layer; A second gate insulating layer is provided on the gate layer; An interlayer dielectric layer is provided on the second gate insulating layer; A metal wiring layer is provided on the interlayer dielectric layer, the metal wiring layer including a first metal wiring pattern, a second metal wiring pattern, and a third metal wiring pattern; a first electrode of the first active pattern is connected to the first metal wiring pattern, a second electrode of the first active pattern and a first electrode of the second active pattern are both connected to the second metal wiring pattern, and a second electrode of the second active pattern is connected to the third metal wiring pattern; The first metal wiring pattern is connected to a first voltage, the second active pattern is connected to the dummy data signal line, the third metal wiring pattern is connected to a second voltage, and the gate layer is connected to the data signal line.

11. The display panel according to any one of claims 1 to 3, characterized in that: An encapsulation layer is disposed on the cathode. The touch electrodes are disposed on a side of the encapsulation layer away from the cathode. The touch electrodes include first touch electrodes and second touch electrodes that cross and are insulated from each other.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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