Display substrate and display device

Abstract

The display substrate comprises a display area and an edge area located at the periphery of the display area, and the edge area comprises: a composite insulating layer arranged on a substrate, a gate drive circuit arranged on the composite insulating layer, and a power supply line arranged on the side of the gate drive circuit away from the substrate; the power supply line and the gate drive circuit have overlapping projections on the substrate. The display substrate provided by the embodiment can reduce the frame by arranging the power supply line and the gate drive circuit on different layers and making the projections of the two overlap.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, display technology, and particularly to a display substrate and a display device. Background Technology

[0002] With the rise of Active Matrix Organic Light Emitting Diode (AMOLED) screens in recent years, market demand for AMOLED screens has been continuously increasing. Furthermore, major mobile phone manufacturers are constantly pushing to increase the screen-to-body ratio of mobile phones. To achieve this goal, narrowing the screen bezels is imperative. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device that achieves reduced bezel size.

[0005] This disclosure provides a display substrate, which includes a display area and an edge area surrounding the display area. The edge area includes: a composite insulating layer disposed on a substrate, a gate driving circuit disposed on the composite insulating layer, and a power line disposed on the side of the gate driving circuit away from the substrate; the orthographic projection of the power line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

[0006] In one exemplary embodiment, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit, the second gate driving circuit being disposed on the side of the first gate driving circuit away from the display area, and the orthographic projection of the power line on the substrate overlaps with the orthographic projection of the second gate driving circuit on the substrate.

[0007] In an exemplary embodiment, the orthogonal projection of the power line onto the substrate is located outside the orthogonal projection of the first gate drive circuit onto the substrate.

[0008] In an exemplary embodiment, the edge region further includes an isolation dam disposed on the side of the first gate driving circuit and the second gate driving circuit away from the substrate, wherein the orthographic projection of the isolation dam on the substrate overlaps with the orthographic projection of the second gate driving circuit on the substrate.

[0009] In an exemplary embodiment, the edge region further includes a first planarization layer covering the first gate driving circuit and the second gate driving circuit, wherein the orthographic projection of the isolation dam onto the substrate lies within the orthographic projection of the first planarization layer onto the substrate.

[0010] In one exemplary embodiment, the isolation dam includes a first isolation dam and a second isolation dam, wherein the second isolation dam is disposed on the side of the first isolation dam away from the display area;

[0011] The edge region also includes: an auxiliary power line disposed on the side of the power line away from the substrate;

[0012] The first isolation dam is disposed on the power line, and the auxiliary power line is disposed in the first isolation dam. The auxiliary power line located on the side of the first isolation dam closer to the display area and the auxiliary power line located on the side of the first isolation dam farther from the display area are both connected to the power line; or, the first isolation dam is disposed on the auxiliary power line, and the auxiliary power line located on the side of the second isolation dam closer to the display area is connected to the power line.

[0013] In an exemplary embodiment, the edge region further includes a connection electrode, which is disposed in the first isolation dam. The connection electrode located on the side of the first isolation dam closer to the display area and the connection electrode located on the side of the first isolation dam farther from the display area are both connected to the auxiliary power line.

[0014] In an exemplary embodiment, the first isolation dam includes a third dam base and a fifth dam base. The third dam base is disposed on the auxiliary power line. The third dam base includes a third surface on the side away from the power line, a third proximal surface on the side adjacent to the display area, and a third distal surface on the side away from the display area.

[0015] The connecting electrode completely covers the third surface, the third proximal side, and the third distal side of the third dam foundation; the fifth dam foundation is disposed on the connecting electrode covering the third surface; or, the connecting electrode completely covers the third proximal side and the third distal side, and partially covers the third surface, and the fifth dam foundation is disposed on the connecting electrode partially covering the third surface.

[0016] In an exemplary embodiment, the first isolation dam further includes a first dam base disposed on the power line. The first dam base includes a first surface away from the power line, a first proximal side adjacent to the display area, and a first distal side away from the display area. The auxiliary power line completely covers the first surface, the first proximal side, and the first distal side of the first dam base. Alternatively, the auxiliary power line completely covers the first proximal side and the first distal side of the first dam base and partially covers the first surface of the first dam base.

[0017] In an exemplary embodiment, the second isolation dam includes a second dam base, a fourth dam base, and a sixth dam base; the second dam base is disposed on the side of the power line away from the substrate, the fourth dam base is disposed on the side of the auxiliary power line away from the substrate, and the sixth dam base is disposed on the side of the connecting electrode away from the substrate; the second dam base includes a second surface away from the power line, a second proximal side adjacent to the display area, and a second distal side away from the display area, wherein the auxiliary power line completely covers the second proximal side of the second dam base and partially covers the second surface of the second dam base.

[0018] In an exemplary embodiment, the display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed in the same layer as the second source / drain metal layer of the driving structure layer, and the connecting electrode is disposed in the same layer as the anode of the light-emitting element.

[0019] This disclosure provides a display device including the display substrate described in any of the above embodiments.

[0020] This disclosure includes a display substrate and a display device. The display substrate includes a display area and an edge area surrounding the display area. The edge area includes: a composite insulating layer disposed on a substrate, a gate driving circuit disposed on the composite insulating layer, and a power line disposed on the side of the gate driving circuit away from the substrate. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate. The display substrate provided in this embodiment achieves a reduced bezel by disposing the power line and the gate driving circuit on different layers, with their orthographic projections overlapping (i.e., spatially overlapping).

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0024] Figure 1 A schematic diagram of a display substrate provided for a technical solution;

[0025] Figure 2A plan view of a display substrate provided for an exemplary embodiment;

[0026] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the display substrate.

[0027] Figure 4 A schematic diagram of a display substrate provided for another exemplary embodiment;

[0028] Figure 5 A schematic diagram of a display substrate provided for yet another exemplary embodiment;

[0029] Figure 6 A schematic diagram of a display substrate provided for yet another exemplary embodiment;

[0030] Figure 7 A schematic diagram of a display substrate provided for another exemplary embodiment. Detailed Implementation

[0031] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0032] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0034] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, embodiments of this disclosure are not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0036] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0037] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0038] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0039] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and "drain electrode" can be interchanged.

[0040] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0041] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes a state in which the angle is greater than or equal to 85° and less than 95°.

[0042] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0043] The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0044] Figure 1 This is a schematic diagram of a display substrate. (Example) Figure 1 As shown, the display substrate includes a display area 100 and an edge area 300. In a plane parallel to the substrate 10 of the display substrate, the edge area 300 includes a circuit area 301, an isolation dam area 302, and a crack dam area 303 sequentially arranged along a direction away from the display area 100. The circuit area 301 includes a first gate driving circuit 13 and a second gate driving circuit 14, which are connected to pixel driving circuits in the display area 100. The isolation dam area 302 includes a power line 15, a first isolation dam 410, and a second isolation dam 420, which extend along a direction parallel to the edge of the display area and are configured to block moisture from entering the display area 100 from the edge area 300. The second isolation dam 420 is disposed on the side of the first isolation dam 410 away from the display area 100. The crack dam area 303 includes a plurality of cracks provided on the composite insulation layer. The plurality of cracks are configured to reduce the stress on the display area 100 and the circuit area 301 during the cutting process, prevent the cracks from propagating in the direction of the display area 100 and the circuit area 301, and avoid affecting the film structure of the display area 100 and the circuit area 301. The edge of the display area is the edge of the display area 100 adjacent to the edge area 300.

[0045] like Figure 1As shown, in the direction perpendicular to the substrate 10, in the edge region 300, the display substrate may include the substrate 10, a first insulating layer 11 disposed on the substrate 10, a second insulating layer 12 disposed on the side of the first insulating layer 11 away from the substrate 10, a first gate driving circuit 13, a second gate driving circuit 14 and a power line 15 disposed on the side of the second insulating layer 12 away from the substrate 10, a first planarization layer 16 disposed on the side of the first gate driving circuit 13, the second gate driving circuit 14 and the power line 15 away from the substrate 10, a second planarization layer 17 disposed on the side of the first planarization layer 16 away from the substrate 10, a connection electrode 20 disposed on the side of the second planarization layer 17 away from the substrate 10, a pixel definition layer 21 disposed on the side of the connection electrode 20 away from the substrate 10, an organic light-emitting layer 22 disposed on the side of the pixel definition layer 21 away from the substrate 10, a cathode 23 disposed on the side of the organic light-emitting layer 22 away from the substrate 10, and an encapsulation layer 24 disposed on the side of the cathode 23 away from the substrate 10. As can be seen, the dimensions of the first gate drive circuit 13, the second gate drive circuit 14, and the power line 15 occupy a large portion of the bezel size. Therefore, optimizing the design of this part can bring significant bezel reduction benefits in order to achieve a narrow bezel.

[0046] This disclosure provides a display substrate, which includes a display area and an edge area surrounding the display area. The edge area includes: a composite insulating layer disposed on the substrate, a gate driving circuit disposed on the composite insulating layer, and a power line disposed on the side of the gate driving circuit away from the substrate. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

[0047] The display substrate provided in this embodiment can reduce the bezel by placing the power line and the gate drive circuit on different layers, and the two overlap in their orthogonal projections on the substrate (i.e., they overlap in space).

[0048] Figure 2 This is a schematic diagram of a display substrate provided for an exemplary embodiment. For example... Figure 2As shown, in an exemplary embodiment, the display substrate includes a display area 100, a bonding area 200 located on one side of the display area 100, and an edge area 300 located on the other sides of the display area 100. The display area 100 includes at least a plurality of regularly arranged display units (sub-pixels), the bonding area 200 includes at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of display units to an external driving device, and the edge area 300 includes at least an isolation dam, a gate driving circuit, and a second power line VSS that transmits voltage signals to the plurality of display units. The isolation dam of the bonding area 200 and the edge area 300 forms a ring structure surrounding the display area 100.

[0049] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display unit includes a driving structure layer disposed on the substrate, a light-emitting element disposed on the driving structure layer, and an encapsulation layer disposed on the light-emitting element. The driving structure layer includes a pixel driving circuit, the light-emitting element is connected to the pixel driving circuit, the light-emitting element is configured to emit light, and the pixel driving circuit is configured to drive the light-emitting element. In an exemplary embodiment, the pixel driving circuit may include multiple thin-film transistors (TFTs) and storage capacitors, such as 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C, etc., which are not limited in this disclosure. In an exemplary embodiment, the low voltage (VSS) required by the pixel driving circuit in the display area 100 is introduced from the bonding pads of the bonding area 200, enters the edge area 300 after passing through the bonding area 200, and is delivered to each pixel driving circuit through the ring-shaped power line of the edge area 300.

[0050] Figure 3 A schematic diagram of a display substrate provided in an exemplary embodiment is shown. Figure 2 A cross-sectional schematic diagram of region C. (See diagram below.) Figure 3 As shown, the display substrate provided in this embodiment includes a display area 100 and an edge area 300. The edge area 300 includes a circuit area 301, an isolation dam area 302, and a crack dam area 303 arranged sequentially along a direction away from the display area 100.

[0051] In an exemplary embodiment, the edge region 300 of the display substrate may include:

[0052] Base 10;

[0053] A first insulating layer 11 disposed on the substrate 10;

[0054] A second insulating layer 12 is disposed on the side of the first insulating layer 11 away from the substrate 10; the second insulating layer 12 of the crack dam region 303 forms a crack dam 31 including multiple cracks;

[0055] A first gate driving circuit 13 and a second gate driving circuit 14 are disposed on the side of the second insulating layer 12 away from the substrate 10; the second gate driving circuit 14 is disposed on the side of the first gate driving circuit 13 away from the display area 100; the second gate driving circuit 14 is at least partially disposed in the isolation dam region 302; the first gate driving circuit 13 may include a first transistor ( Figure 3 (not shown in the image), the second gate drive circuit 14 may include a second transistor ( Figure 3 (Not shown in the image), the first transistor may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the second transistor may include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate driving circuit 13, the second gate driving circuit 14, and the pixel driving circuit of the display area 100 may be arranged on the same layer, that is, the pixel driving circuit includes a third transistor, the third transistor may include a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, the first active layer, the second active layer, and the third active layer may be arranged on the same layer, the first gate electrode, the second gate electrode, and the third gate electrode may be arranged on the same layer, and the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode may be arranged on the same layer. In an exemplary embodiment, the first transistor may be a scan transistor that outputs a scan (SCAN) signal, and the second transistor may be an enable transistor that outputs an enable (EM) signal.

[0056] A first planarization layer 16 is disposed on the side of the first gate driving circuit 13 and the second gate driving circuit 14 away from the substrate 10, and the first planarization layer 16 covers the first gate driving circuit 13 and the second gate driving circuit 14; a power line 15 is disposed on the side of the first planarization layer 16 away from the substrate 10; the orthographic projection of the power line 15 on the substrate 10 overlaps with the orthographic projection of the second gate driving circuit 14; the first planarization layer 16 covers and fills the crack dam 31.

[0057] A second planarization layer 17 is disposed on the side of the power line 15 away from the substrate 10, and a first dam base 401 and a second dam base 402 are formed in the isolation dam area 302, the first dam base 401 being disposed on the power line 15; the orthographic projections of the first dam base 401 and the second dam base 402 onto the substrate 10 may lie within the orthographic projection of the first planarization layer 16 onto the substrate 10; the first dam base 401 is configured to form a first isolation dam, and the second dam base 402 is configured to form a second isolation dam; in an exemplary embodiment, the first length of the first dam base 401 may be approximately 20 μm to 60 μm. The first length of the second dam base 402 may be approximately 20 μm to 60 μm. In this disclosure, "first length" refers to a feature dimension along a direction away from the display area.

[0058] An auxiliary power line 18 is disposed on the side of the second flat layer 17 away from the substrate 10. The auxiliary power line 18 covers the first surface of the first dam base 401 away from the power line 15, the first near side of the first dam base 401 adjacent to the display area 100, and the first far side of the first dam base 401 away from the display area 100. The auxiliary power line 18 on the side of the first dam base 401 adjacent to the display area 100 and the auxiliary power line 18 on the side of the first dam base 401 away from the display area 100 are both connected to the power line 15. That is, the auxiliary power line 18 is disposed on the power line 15 exposed on both sides of the first dam base 401, so as to realize the connection between the power line 15 and the auxiliary power line 18. The auxiliary power line 18 can partially cover the second surface of the second dam base 402 away from the power line 15, and completely cover the second near side of the second dam base 402 adjacent to the display area 100. The power line 15 and the auxiliary power line 18 form a double-layer power line in the edge area 300. By overlapping in the isolation dam area 302, a parallel double-layer power line is achieved, which reduces the resistance of the power line in the edge area, minimizes the voltage drop of the voltage signal, improves the uniformity of the display brightness in the display area, and improves the display quality.

[0059] A third planarization layer 19 is disposed in the circuit area 301, forming a third dam base 403 and a fourth dam base 404 in the isolation dam area 302. The third dam base 403 is disposed on the auxiliary power line 18 covering the first surface, and the fourth dam base 404 is disposed on the auxiliary power line 18 located on the side of the first dam base 401 away from the display area 100. The orthographic projection of the first dam base 401 on the substrate 10 overlaps with the orthographic projection of the third dam base 403 on the substrate 10. The third dam base 403 and the fourth dam base 404 are configured to form two isolation dams. The first length of the third dam base 403 can be approximately 20 μm to 60 μm, and the first length of the fourth dam base 404 can be approximately 20 μm to 60 μm. In this embodiment, since the power line 15 is disposed on the side of the first gate drive circuit 13 and the second gate drive circuit 14 away from the substrate 10, the third planarization layer 19 is added to facilitate the formation of an isolation dam of sufficient height, improve the isolation effect of the isolation dam on water vapor, and improve product quality and service life.

[0060] The connecting electrode 20 is disposed on the side of the third flat layer 19 away from the substrate 10. The connecting electrode 20 covers the third surface of the third dam base 403 away from the auxiliary power line 18, the third near side of the third dam base 403 adjacent to the display area 100, and the third far side of the third dam base 403 away from the display area 100. The connecting electrode 20 on the side of the third dam base 403 adjacent to the display area 100 and the connecting electrode 20 on the side of the third dam base 403 away from the display area 100 are both connected to the auxiliary power line 18. Since the connecting electrode 20 is electrically connected to the auxiliary power line 18, and the auxiliary power line 18 is electrically connected to the power line 15, the connection between the connecting electrode 20 and the power line 15 is realized.

[0061] A pixel definition layer 21 is disposed on the side of the connecting electrode 20 away from the substrate 10, and a fifth dam base 405 and a sixth dam base 406 are disposed on the isolation dam area 302. The fifth dam base 405 is disposed on the connecting electrode 20 covering the third surface, and the sixth dam base 406 is disposed on the fourth dam base 404. The fifth dam base 405 covers the near side of the connecting electrode 20 close to the display area 100 and the far side away from the display area 100. The orthographic projection of the third dam base 403 on the substrate 10 can be located within the orthographic projection of the fifth dam base 405 on the substrate 10, and the orthographic projection of the fourth dam base 404 on the substrate 10 can be located within the orthographic projection of the sixth dam base 406 on the substrate 10. The first length of the fifth dam base 405 can be approximately 20 μm to 60 μm, and the first length of the sixth dam base 406 can be approximately 20 μm to 60 μm.

[0062] An organic light-emitting layer 22 is disposed on the side of the pixel definition layer 21 away from the substrate 10;

[0063] A cathode 23 is disposed on the side of the organic light-emitting layer 22 away from the substrate 10. The cathode 23 is disposed in the circuit area 301 and is connected to the connecting electrode 20. Since the cathode 23 is connected to the connecting electrode 20, the connecting electrode 20 is connected to the auxiliary power line 18, and the auxiliary power line 18 is connected to the power line 15, the connection between the cathode 23 and the power line 15 is realized.

[0064] The seventh dam foundation 407 and the eighth dam foundation 408 are set in the isolation dam area 302. The seventh dam foundation 407 is located on the side of the fifth dam foundation 405 away from the base 10, and the eighth dam foundation 408 is located on the side of the sixth dam foundation 406 away from the base 10. The first length of the seventh dam foundation 407 can be approximately 20 μm to 60 μm, and the first length of the eighth dam foundation 408 can be approximately 20 μm to 60 μm. The first dam foundation 401, the auxiliary power line 18 covering the first surface, the third dam foundation 403, the connecting electrode 20 covering the third surface, the fifth dam foundation 405, and the seventh dam foundation 407 form the first isolation dam 410. The second dam foundation 402, the auxiliary power line 18, the fourth dam foundation 404, the sixth dam foundation 406, and the eighth dam foundation 408 form the second isolation dam 420. The distance between the first isolation dam 410 and the second isolation dam 420 can be approximately 20 μm to 60 μm.

[0065] The encapsulation layer 24 covering the above structure, the encapsulation layer 24 of the circuit region 301 can be a stacked structure of inorganic material / organic material / inorganic material, and the encapsulation layer 24 of the isolation dam region 302 can be a stacked structure of inorganic material / inorganic material.

[0066] The display substrate provided in this embodiment achieves a reduced bezel by placing the power line on the side of the gate drive circuit away from the substrate, and the two overlap in their orthogonal projections onto the substrate.

[0067] In an exemplary embodiment, the power line 15 and the auxiliary power line 18 may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti.

[0068] In an exemplary embodiment, the orthographic projection of the power line 15 onto the substrate 10 may not overlap with the orthographic projection of the first gate driving circuit 13 onto the substrate 10, thereby reducing the mutual influence between the power line 15 and the first gate driving circuit 13.

[0069] In an exemplary embodiment, the first planarization layer 16 covering the first gate driving circuit 13 and the second gate driving circuit 14 includes: the first planarization layer 16 covering the first source electrode and the first drain electrode of the first transistor of the first gate driving circuit 13, and covering the second source electrode and the second drain electrode of the second transistor of the second gate driving circuit 14.

[0070] In an exemplary embodiment, the display area 100 may include a driving structure layer and a light-emitting element sequentially disposed on a substrate 10. The driving structure layer may include a first source / drain electrode layer and a second source / drain electrode layer. The first source / drain electrode layer may include the third source electrode and the third drain electrode. The second source / drain electrode layer may include a second connection electrode. The second connection electrode may be connected to the third drain electrode and to the anode of the light-emitting element of the display area. The power line 15 may be disposed on the same layer as the second source / drain electrode layer. The connection electrode 20 may be disposed on the same layer as the anode of the display area 100.

[0071] In an exemplary embodiment, the first thickness of the first dam base 401 along a direction perpendicular to the base 10 can be less than the second thickness of the second dam base 402 along a direction perpendicular to the base 10, and the first thickness is, for example, 30% to 70% of the second thickness. By reducing the thickness of the first dam base 401, the height of the first isolation dam 410 along a direction perpendicular to the base 10 is less than the height of the second isolation dam 420 along a direction perpendicular to the base 10, which facilitates better blocking of external moisture from entering the display area 100, improving product quality and service life. In an exemplary embodiment, a halftone or grayscale mask patterning process can be used to make the first thickness of the first dam base 401 less than the second thickness of the second dam base 402.

[0072] In one exemplary embodiment, such as Figure 4As shown, a first venting structure K1 is provided on the auxiliary power line 18. In an exemplary embodiment, the first dam base 401 includes a first surface away from the power line 15, a first near-side surface adjacent to the display area 100, and a first far-side surface away from the display area 100. The first venting structure K1 can be disposed on the auxiliary power line 18 covering the first surface of the first dam base 401. The orthographic projection of the first venting structure K1 onto the substrate 10 is located within the orthographic projection range of the first surface onto the substrate 10. In an exemplary embodiment, the first venting structure K1 can be at least one first through hole, in which the auxiliary power line 18 is removed, exposing the first surface of the first dam base 401. In an exemplary embodiment, a plurality of first through holes can be spaced apart along the edge direction of the display area. In a plane parallel to the display substrate, the shape of the first through holes can be triangular, rectangular, polygonal, circular, or elliptical, etc. In an exemplary embodiment, the shape of the first through-hole can be rectangular, with a first length of approximately 10 μm to 40 μm, a second length of approximately 10 μm to 40 μm, and a spacing between adjacent first through-holes of approximately 10 μm to 40 μm. In this disclosure, "second length" refers to the feature dimension along the edge direction of the display area.

[0073] In an exemplary embodiment, the first venting structure K1 provided on the auxiliary power line 18 is configured to form a venting channel to release the gas generated during the planarization of the film layer during the process, thereby avoiding film peeling and improving process quality.

[0074] In one exemplary embodiment, such as Figure 5 As shown, the connecting electrode 20 is provided with a second venting structure K2. In an exemplary embodiment, the third dam base 403 includes a third surface (upper surface) on the side away from the auxiliary power line 18, a third near-side surface on the side adjacent to the display area 100, and a third far-side surface on the side away from the display area 100. The second venting structure K2 is disposed on the connecting electrode 20 covering the third surface of the third dam base 403. The orthographic projection of the second venting structure K2 onto the substrate 10 is located within the orthographic projection range of the third surface onto the substrate 10. In an exemplary embodiment, the second venting structure K2 can be at least one second through hole, in which the connecting electrode 20 is removed, exposing the second surface of the third dam base 403. In an exemplary embodiment, a plurality of second through holes can be spaced apart along the edge direction of the display area. In a plane parallel to the display substrate, the shape of the second through holes can be triangular, rectangular, polygonal, circular, or elliptical, etc. In an exemplary embodiment, the shape of the second through hole can be rectangular, the first length of the rectangle can be about 10 μm to 40 μm, the second length of the rectangle can be about 10 μm to 40 μm, and the spacing between adjacent second through holes can be about 10 μm to 40 μm.

[0075] In an exemplary embodiment, the second venting structure K2 provided on the connecting electrode 20 is configured to form a venting channel to discharge the gas generated during the planarization of the film layer during the process, thereby avoiding film layer peeling and improving process quality.

[0076] Figure 5 In the display substrate shown, the auxiliary power line 18 is provided with a first venting structure K1, and the connecting electrode 20 is provided with a second venting structure K2. In another exemplary embodiment, only the connecting electrode 20 may be provided with the second venting structure K2, and the auxiliary power line 18 may not be provided with the first venting structure K1.

[0077] In an exemplary embodiment, the auxiliary power line 18 covering the first surface of the first dam base 401 away from the power line 15, the first near side of the first dam base 401 adjacent to the display area 100, and the first far side of the first dam base 401 away from the display area 100 can be: the auxiliary power line 18 completely covers the first surface of the first dam base 401 away from the power line 15, the first near side of the first dam base 401 adjacent to the display area 100, and the first far side of the first dam base 401 away from the display area 100; or, the auxiliary power line 18 completely covers the first near side and the first far side of the first dam base 401, and partially covers the first surface of the first dam base 401. Partially covering the first surface of the first dam base 401 means that the auxiliary power line 18 covers a portion of the first surface (first near area) adjacent to the display area 100 and a portion of the first surface (first far area) away from the display area 100, and the area between the first near area and the first far area is the location of the first through hole, exposing the first surface of the first dam base 401. In an exemplary embodiment, the auxiliary power line 18 completely covers the first near side and the first far side of the first dam foundation 401, that is, the first surface of the first dam foundation 401 is the location of the first through hole.

[0078] In an exemplary embodiment, the connecting electrode 20 covering the third surface of the third dam base 403 on the side away from the auxiliary power line 18, the third near-side on the side adjacent to the display area 100, and the third far-side on the side away from the display area 100 can be: the connecting electrode 20 completely covers the third surface of the third dam base 403 on the side away from the auxiliary power line 18, the third near-side on the side adjacent to the display area 100, and the third far-side on the side away from the display area 100; or, the connecting electrode 20 completely covers the third near-side on the side adjacent to the display area 100 and the third far-side on the side away from the display area 100, and partially covers the third surface of the third dam base 403 on the side away from the auxiliary power line 18. Partially covering the third surface of the third dam base 403 means that the connecting electrode 20 covers a portion of the third surface (third near-region) on the side adjacent to the display area 100 and a portion of the third surface (third far-region) on the side away from the display area 100, and the area between the third near-region and the third far-region is the location of the second through hole, exposing the third surface of the third dam base 403. In an exemplary embodiment, the connecting electrode 20 completely covers the third near side and the third far side of the third dam base 403, that is, the third surface of the third dam base 403 is the location of the third through hole.

[0079] In an exemplary embodiment, the crack dam region 303 includes a composite insulation layer disposed on the substrate 10, the composite insulation layer forming a crack dam 31, and a first planarization layer 16 covering and filling the crack dam 31.

[0080] In an exemplary embodiment, the composite insulating layer includes a first insulating layer 11 and a second insulating layer 12.

[0081] In an exemplary embodiment, the orthographic projection of the isolation dam onto the substrate 10 overlaps with the orthographic projection of the second gate driving circuit 14 onto the substrate 10. The isolation dam may include a first isolation dam 410 and a second isolation dam 420. The solution provided in this embodiment enables the gate driving circuit and the isolation dam to share space, thereby narrowing the bezel.

[0082] In an exemplary embodiment, the orthographic projection of the first isolation dam 410 onto the substrate 10 overlaps with the orthographic projection of the second gate driving circuit 14 onto the substrate 10.

[0083] In an exemplary embodiment, the orthographic projection of the first isolation dam 410 onto the substrate 10 may be located within the orthographic projection of the second gate drive circuit 14 onto the substrate 10.

[0084] In one embodiment, the first isolation dam 410 is projected onto the substrate 10 within the projected projection of the first planarization layer 16, and the second isolation dam 420 is projected onto the substrate 10 within the projected projection of the first planarization layer 16. In this embodiment, when reducing the bezel, the first planarization layer 16 is used to protect the first gate drive circuit and the second gate drive circuit, preventing particles in subsequent processes from affecting the first gate drive circuit 13 and the second gate drive circuit 14.

[0085] Figure 6 A schematic diagram of a display substrate provided for another exemplary embodiment. (See diagram below.) Figure 6 As shown, the display substrate provided in this embodiment includes a display area 100 and an edge area 300. The edge area 300 includes a circuit area 301, an isolation dam area 302, and a crack dam area 303 arranged sequentially along a direction away from the display area 100.

[0086] In an exemplary embodiment, the edge region 300 of the display substrate may include:

[0087] Base 10;

[0088] A first insulating layer 11 disposed on the substrate 10;

[0089] A second insulating layer 12 is disposed on the side of the first insulating layer 11 away from the substrate 10; the second insulating layer 12 of the crack dam region 303 forms a crack dam 31 including multiple cracks;

[0090] A first gate driving circuit 13 and a second gate driving circuit 14 are disposed on the side of the second insulating layer 12 away from the substrate 10; the second gate driving circuit 14 is disposed on the side of the first gate driving circuit 13 away from the display area 100; the second gate driving circuit 14 is at least partially disposed in the isolation dam area 302.

[0091] A first planarization layer 16 is disposed on the side of the first gate driving circuit 13 and the second gate driving circuit 14 away from the substrate 10, and the first planarization layer 16 covers the first gate driving circuit 13 and the second gate driving circuit 14; a power line 15 is disposed on the side of the first planarization layer 16 away from the substrate; the orthographic projection of the power line 15 on the substrate 10 overlaps with the orthographic projection of the second gate driving circuit 14.

[0092] A second flat layer 17 is disposed on the side of the power line 15 away from the substrate 10, and a second dam base 402 is formed in the isolation dam area 302, the orthographic projection of the second dam base 402 onto the substrate 10 being located within the orthographic projection of the first flat layer 16 onto the substrate 10; the second dam base 402 is configured to form a second isolation dam; in an exemplary embodiment, the first length of the second dam base 401 can be approximately 20 μm to 60 μm. In this disclosure, "first length" refers to a feature dimension along the direction away from the display area. In this embodiment, the first dam base 401 is not formed, which facilitates increasing the height difference between the first isolation dam 410 and the second isolation dam 420, thereby improving the water vapor barrier effect.

[0093] An auxiliary power line 18 is disposed on the side of the second flat layer 17 away from the substrate 10. The auxiliary power line 18 on the side of the second dam base 402 near the display area 100 overlaps with the power line 15. That is, the auxiliary power line 18 is disposed on the exposed power line 15 between the second flat layer 17 and the second dam base 402, thus connecting the power line 15 and the auxiliary power line 18. The auxiliary power line 18 can partially cover the second surface of the second dam base 402 away from the power line 15, and completely cover the second near-side surface of the second dam base 402 adjacent to the display area 100. The power line 15 and the auxiliary power line 18 form a double-layer power line in the edge region 300. This parallel double-layer power line arrangement, achieved by overlapping in the isolation dam area 302, reduces the resistance of the power line in the edge region, minimizes the voltage drop of the voltage signal, improves the uniformity of display brightness in the display area, and enhances display quality.

[0094] A third planarization layer 19 is disposed in the circuit area 301, forming a third dam base 403 and a fourth dam base 404 in the isolation dam area 302. The third dam base 403 is disposed on the auxiliary power line 18, and the fourth dam base 404 is disposed on the auxiliary power line 18 located on the side of the first dam base 401 away from the display area 100. The third dam base 403 is configured to form a first isolation dam. In this embodiment, since the power line 15 is disposed on the side of the first gate drive circuit 13 and the second gate drive circuit 14 away from the substrate 10, the third planarization layer 19 is added to facilitate the formation of an isolation dam of sufficient height, improve the isolation effect of the isolation dam on water vapor, and improve product quality and service life.

[0095] The connecting electrode 20 is disposed on the side of the third flat layer 19 away from the substrate 10. The connecting electrode 20 covers the third surface of the third dam base 403 away from the auxiliary power line 18, the third near side of the third dam base 403 adjacent to the display area 100, and the third far side of the third dam base 403 away from the display area 100. The connecting electrode 20 on the side of the third dam base 403 adjacent to the display area 100 and the connecting electrode 20 on the side of the third dam base 403 away from the display area 100 are both connected to the auxiliary power line 18. Since the connecting electrode 20 is electrically connected to the auxiliary power line 18, and the auxiliary power line 18 is electrically connected to the power line 15, the connection between the connecting electrode 20 and the power line 15 is realized.

[0096] A pixel definition layer 21 is disposed on the side of the connecting electrode 20 away from the substrate 10, and a fifth dam base 405 and a sixth dam base 406 are disposed on the isolation dam area 302; the fifth dam base 405 is disposed on the connecting electrode 20 covering the third surface, and the sixth dam base 406 is disposed on the fourth dam base 404; the fifth dam base 405 covers the near side of the connecting electrode 20 close to the display area 100 and the far side away from the display area 100; the orthographic projection of the third dam base 403 on the substrate 10 can be located within the orthographic projection of the fifth dam base 405 on the substrate 10, and the orthographic projection of the fourth dam base 404 on the substrate 10 can be located within the orthographic projection of the sixth dam base 406 on the substrate 10;

[0097] An organic light-emitting layer 22 is disposed on the side of the pixel definition layer 21 away from the substrate 10;

[0098] A cathode 23 is disposed on the side of the organic light-emitting layer 22 away from the substrate 10. The cathode 23 is disposed in the circuit area 301 and is connected to the connecting electrode 20. Since the cathode 23 is connected to the connecting electrode 20, the connecting electrode 20 is connected to the auxiliary power line 18, and the auxiliary power line 18 is connected to the power line 15, the connection between the cathode 23 and the power line 15 is realized.

[0099] The seventh dam foundation 407 and the eighth dam foundation 408 are set in the isolation dam area 302. The seventh dam foundation 407 is set on the side of the fifth dam foundation 405 away from the base 10, and the eighth dam foundation 408 is set on the side of the sixth dam foundation 406 away from the base 10. The third dam foundation 403, the connecting electrode 20 covering the third surface, the fifth dam foundation 405, and the seventh dam foundation 407 form the first isolation dam 410. The second dam foundation 402, the auxiliary power line 18, the fourth dam foundation 404, the sixth dam foundation 406, and the eighth dam foundation 408 form the second isolation dam 420. The distance between the first isolation dam 410 and the second isolation dam 420 can be approximately 20μm to 60μm.

[0100] The encapsulation layer 24 covering the above structure, the encapsulation layer 24 of the circuit region 301 can be a stacked structure of inorganic material / organic material / inorganic material, and the encapsulation layer 24 of the isolation dam region 302 can be a stacked structure of inorganic material / inorganic material.

[0101] The solution provided in this embodiment reduces the bezel by placing the power line on the side of the gate drive circuit away from the substrate, and by having the two overlapping in their orthogonal projections onto the substrate.

[0102] Figure 7 A schematic diagram of a display substrate provided for another exemplary embodiment. (See diagram below.) Figure 7 As shown, in this embodiment, with Figure 6 The illustrated embodiment is similar, but without the first isolation dam 401. In this embodiment, a second venting structure K2 is provided on the connecting electrode 20. The second venting structure K2 is disposed on the third surface of the connecting electrode 20 covering the third dam base 403, and the orthographic projection of the second venting structure K2 on the substrate 10 is within the orthographic projection range of the third surface on the substrate 10. Other details of the second venting structure K2 can be found in the aforementioned embodiment and will not be repeated here.

[0103] In one exemplary embodiment, the auxiliary power line 18 may be omitted. In this case, the connecting electrode 20 can be directly connected to the power line 15.

[0104] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0105] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and an edge area surrounding the display area. The edge area includes: a composite insulating layer disposed on the substrate, a gate driving circuit disposed on the composite insulating layer, and a power line disposed on the side of the gate driving circuit away from the substrate. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate. The edge region also includes a cathode and an auxiliary power line disposed on the side of the power line away from the substrate. The cathode is disposed in the circuit area of ​​the edge region. The power line and the auxiliary power line extend from the isolation dam area of ​​the edge region to the circuit area. The orthographic projection of the cathode on the substrate overlaps with the orthographic projections of the power line and the auxiliary power line on the substrate.

2. The display substrate according to claim 1, characterized in that, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The second gate driving circuit is disposed on the side of the first gate driving circuit away from the display area. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the second gate driving circuit on the substrate.

3. The display substrate according to claim 2, characterized in that, The orthographic projection of the power line onto the substrate is located outside the orthographic projection of the first gate drive circuit onto the substrate.

4. The display substrate according to claim 2, characterized in that, The edge region also includes an isolation dam disposed on the side of the first gate driving circuit and the second gate driving circuit away from the substrate, wherein the orthographic projection of the isolation dam on the substrate overlaps with the orthographic projection of the second gate driving circuit on the substrate.

5. The display substrate according to claim 4, characterized in that, The edge region further includes a first planarization layer covering the first gate driving circuit and the second gate driving circuit, the first planarization layer covering the first gate driving circuit and the second gate driving circuit, and the orthographic projection of the isolation dam on the substrate is located within the orthographic projection of the first planarization layer on the substrate.

6. The display substrate according to claim 4, characterized in that, The isolation dam includes a first isolation dam and a second isolation dam, wherein the second isolation dam is located on the side of the first isolation dam away from the display area; The first isolation dam is disposed on the power line, and the auxiliary power line is disposed in the first isolation dam. The auxiliary power line located on the side of the first isolation dam closer to the display area and the auxiliary power line located on the side of the first isolation dam farther from the display area are both connected to the power line; or, the first isolation dam is disposed on the auxiliary power line, and the auxiliary power line located on the side of the second isolation dam closer to the display area is connected to the power line.

7. The display substrate according to claim 6, characterized in that, The edge region also includes a connection electrode, which is provided in the first isolation dam. The connection electrode located on the side of the first isolation dam closer to the display area and the connection electrode located on the side of the first isolation dam farther from the display area are both connected to the auxiliary power line.

8. The display substrate according to claim 7, characterized in that, The first isolation dam includes a third dam base and a fifth dam base. The third dam base is disposed on the auxiliary power line. The third dam base includes a third surface away from the power line, a third proximal surface adjacent to the display area, and a third distal surface away from the display area. The connecting electrode completely covers the third surface, the third proximal side, and the third distal side of the third dam foundation; the fifth dam foundation is disposed on the connecting electrode covering the third surface; or, the connecting electrode completely covers the third proximal side and the third distal side, and partially covers the third surface, and the fifth dam foundation is disposed on the connecting electrode partially covering the third surface.

9. The display substrate according to claim 8, characterized in that, The first isolation dam further includes a first dam base, which is disposed on the power line. The first dam base includes a first surface away from the power line, a first near side adjacent to the display area, and a first far side away from the display area. The auxiliary power line completely covers the first surface, the first near side, and the first far side of the first dam base; or, the auxiliary power line completely covers the first near side and the first far side of the first dam base, and partially covers the first surface of the first dam base.

10. The display substrate according to claim 7, characterized in that, The second isolation dam includes a second dam base, a fourth dam base, and a sixth dam base; the second dam base is disposed on the side of the power line away from the substrate, the fourth dam base is disposed on the side of the auxiliary power line away from the substrate, and the sixth dam base is disposed on the side of the connecting electrode away from the substrate; the second dam base includes a second surface away from the power line, a second proximal side adjacent to the display area, and a second distal side away from the display area, and the auxiliary power line completely covers the second proximal side of the second dam base and partially covers the second surface of the second dam base.

11. The display substrate according to any one of claims 7 to 10, characterized in that, The display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed in the same layer as the second source / drain metal layer of the driving structure layer, and the connecting electrode is disposed in the same layer as the anode of the light-emitting element.

12. A display device comprising a display substrate as described in any one of claims 1 to 11.

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