Method for manufacturing thin film transistor, array substrate, and display device

Abstract

The application relates to the field of display devices, and provides a thin film transistor manufacturing method, an array substrate and a display device, wherein the thin film transistor manufacturing method comprises the following steps: forming a conductive thin film layer on a substrate; performing heat treatment on the conductive thin film layer; controlling the stress of the conductive thin film layer to be within a first preset range; forming an insulating layer on the substrate, and the insulating layer covers the conductive thin film layer; compared with the prior art, the stress range of the conductive thin film layer is controlled by controlling the forming method of the conductive thin film layer, so that the stress of the conductive thin film layer is matched with the stress of the insulating layer, and the bulging phenomenon between the conductive thin film layer and the insulating layer is avoided; the application further provides an array substrate and a display device; the array substrate comprises a thin film transistor; the display device comprises the array substrate; compared with the prior art, since the thin film transistor does not have the bulging phenomenon, the display device has better display effect.

Description

Technical Field

[0001] The present application relates to the field of display devices, and in particular to a method for manufacturing a thin film transistor, an array substrate, and a display device. Background Art

[0002] Oxide semiconductor materials, represented by transparent conductive materials such as gallium zinc oxide (IGZO) and indium tin oxide (ITO), have been a research hotspot in thin-film transistor liquid crystal displays (LCDs) and organic electroluminescent (AMOLED) displays in recent years. Due to their relatively high electron mobility and low leakage current, IGZO-based panels are primarily used in high-end, high-resolution, low-power products and large-size, 8K, high-refresh-rate TVs, and their market share continues to grow.

[0003] However, due to the strong intrinsic electron migration ability within the IGZO film layer, it is also extremely susceptible to the influence of external water vapor or hydrogen ions. If hydrogen (H) is captured to generate oxygen vacancies, it will also lead to an increase in carriers, which will eventually make the characteristics negatively biased. Therefore, oxide thin-film transistors often require a dense silicon nitride (SiN) film (insulating layer) to give it a strong ability to block hydrogen ions. Generally, the denser the silicon nitride film, the greater its compressive stress. However, due to the dense film quality of the transparent conductive film layer and the large compressive stress of the film layer, "bulging" is easily generated in the transparent conductive film layer. It is understandable that thin-film transistors generally have a layered structure. During the manufacturing process of thin-film transistors, there are often "bulging" defects between layers, that is, multiple "cavities" are formed between layers. The "bulging" will have an adverse effect on the performance of the transistor. For example, for field-effect transistors used in display devices, since in the display device, the light emitted by the light source will pass through the field-effect transistor. If a "bulging" problem occurs in the layered structure of the light-transmitting area of ​​the field-effect transistor, since the refractive index of the "bulging" area is different from that of the normal area, the "bulging" area will affect the propagation of light, thereby affecting the display effect of the display device.

[0004] Specifically, in the prior art, the bulging problem in thin-film transistors is mostly located between the conductive film layer and the insulating layer; since the conductive film layer has low crystallinity or even no crystallinity after formation, the prior art requires heat treatment after the conductive film layer is formed to improve the conductivity of the conductive film layer; however, the stress of the conductive film layer will change after a long period of heat treatment, resulting in a mismatch with the stress of the insulating layer, which will cause serious interlayer "bulging" problems. Summary of the Invention

[0005] An embodiment of the present invention discloses a method for manufacturing a thin film transistor. By adjusting the formation process of the conductive film and the insulating layer to control the stress range of the conductive film layer and the insulating layer, the conductive film layer and the insulating layer are deformed in the same direction and with similar deformation arcs, thereby solving the problem of bulging between the conductive film layer and the insulating layer in the prior art.

[0006] The method for manufacturing a thin film transistor provided by an embodiment of the present invention includes the following steps:

[0007] forming a conductive thin film layer on a substrate;

[0008] performing heat treatment on the conductive film layer; controlling the stress of the conductive film layer to be within a first preset range;

[0009] An insulating layer is formed on the substrate; the insulating layer covers the conductive film layer.

[0010] Optionally, controlling the stress of the conductive film layer 2 to be within a first preset range includes:

[0011] The stress of the conductive film layer is controlled to be within a range of -200 MPa to 100 MPa.

[0012] Optionally, the heat treatment of the conductive film layer includes:

[0013] The temperature of the heat treatment is less than 250°C.

[0014] Optionally, the heat treatment of the conductive film layer includes:

[0015] The heat treatment time is less than 60 minutes.

[0016] Optionally, the heat treatment of the conductive film layer includes:

[0017] The heat treatment time is 0 min.

[0018] Optionally, forming a conductive film layer on the substrate includes:

[0019] The conductive film is formed on the substrate by magnetron sputtering.

[0020] Optionally, the forming of the conductive film on the substrate by magnetron sputtering includes:

[0021] Under the condition that the sputtering power is 12kW-20kW, the conductive thin film layer is formed on the substrate by the magnetron sputtering method.

[0022] Optionally, forming the conductive film layer on the substrate by magnetron sputtering includes:

[0023] Under the conditions of sputtering power of 12 kW to 20 kW, chamber temperature of 25°C, sputtering time of 10 to 20 s, process pressure of 0.5 to 1 Pa, argon flow rate of 500 sccm to 1280 sccm and no water supply, the conductive film layer is formed on the substrate by the magnetron sputtering method.

[0024] Optionally, forming an insulating layer on the conductive film layer includes:

[0025] An insulating layer is formed on the substrate by low pressure chemical vapor deposition.

[0026] Optionally, forming an insulating layer on the substrate by low-pressure chemical vapor deposition includes:

[0027] The chamber pressure is controlled to be 700-1000 mtorr, and an insulating layer is formed on the substrate by the low pressure chemical vapor deposition method.

[0028] Optionally, the stress range of the insulating layer is -1000 MPa to -500 MPa, and the stress properties of the conductive film layer and the insulating layer are consistent.

[0029] Optionally, the stress difference between the insulating layer and the conductive film layer is less than or equal to 700 MPa.

[0030] Optionally, the method for manufacturing a thin film transistor further includes:

[0031] forming the conductive film layer on the substrate;

[0032] forming a gate on the substrate;

[0033] forming the insulating layer on the substrate; the insulating layer covers the conductive film layer and the gate;

[0034] An active layer, a source layer, and a drain layer are formed on the insulating layer.

[0035] Compared with the prior art, the manufacturing method of the above-mentioned thin film transistor provided in the embodiment of the present application adjusts the formation process of the conductive film and the insulating layer to control the stress range of the conductive film and the insulating layer, so that the stress properties of the conductive film layer and the insulating layer are consistent, so that the bending deformation directions of the conductive film layer and the insulating layer are consistent and the deformation curvatures are similar, thereby solving the problem of bulging between the conductive film layer and the insulating layer in the prior art.

[0036] An embodiment of the present invention provides an array substrate including the thin film transistor.

[0037] An embodiment of the present invention further provides a display device, comprising the array substrate as described above.

[0038] Since the thin film transistors of the array substrate of the liquid crystal display device are manufactured using the manufacturing method provided by the embodiment of the present invention, there is no bulging problem between the insulating layer and the conductive film layer, so it has a better display effect than the existing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 A flow chart of a method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0042] Figure 2 A layered structure diagram of a thin film transistor provided in an embodiment of the present application.

[0043] Figure 3 This is a schematic diagram of bulging between a conductive film layer and an insulating layer in the prior art.

[0044] Figure 4 This is a flow chart of another embodiment of the method for manufacturing a thin film transistor provided in an embodiment of the present application.

[0045] Figure 5 A layered structure diagram of a thin film transistor manufactured according to another embodiment of the present application.

[0046] Figure 6 This is a crystalline phase diagram from a top-down perspective of the conductive thin film layer formed by the method for manufacturing the thin film transistor provided by an embodiment of the present application.

[0047] Figure 7 This is a crystal phase diagram of the side cross-section of the thin film transistor formed by the manufacturing method of the thin film transistor provided by an embodiment of the present application.

[0048] Description of the drawings: 1. Substrate; 2. Conductive film layer; 3. Gate; 4. Insulating layer; 5. Source; 6. Drain; 7. Active layer. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0050] A thin film transistor generally includes a substrate, and an insulating layer, an active layer, a source layer, a gate layer, and a drain layer formed on the substrate; some thin film transistors are also provided with a COM electrode; the COM electrode is generally a layer of conductive film; the function of the COM electrode is to serve as an external circuit of the thin film transistor (TFT); the COM electrode can also form a capacitor with the pixel electrode layer to play a voltage stabilizing role.

[0051] The COM electrode is generally located between the substrate and the insulating layer, and the insulating layer is generally formed on the COM electrode. In the prior art, the conductive film of the COM electrode is generally formed by vacuum evaporation coating process. Since the crystallinity of the conductive film is low or even non-crystallized after film formation, it needs to be heat-treated after film formation to improve the crystallinity of the conductive film, thereby improving the electrical conductivity. However, the conductive film layer will generate large tensile stress after heat treatment, which will lead to the problem of "bulging" between the conductive film layer and the insulating layer. Figure 3 If the “bulge” is located in the light-transmitting area of ​​the array substrate, it will cause light to be refracted or reflected, thereby affecting the display effect of the display device manufactured using the array substrate.

[0052] In order to solve the problem of "bulging" between the conductive film layer and the insulating layer in the thin film transistor, an embodiment of the present invention provides a method for manufacturing a thin film transistor, wherein the manufacturing method of the thin film transistor controls the molding conditions of the conductive film layer and the insulating layer so that the stress of the conductive film layer and the insulating layer are matched. Figure 2 , thereby solving the problem of "bulging".

[0053] Combined with attachment Figure 1 , Figure 1 The flowchart of the method for manufacturing a thin film transistor provided in an embodiment of the present application is exemplarily described below: The method for manufacturing a thin film transistor provided in an embodiment of the present invention mainly includes the following steps:

[0054] S1. forming a conductive film layer 2 on a substrate 1;

[0055] S2. heat-treating the conductive film layer 2; controlling the stress of the conductive film layer 2 to be within a first preset range;

[0056] S3. An insulating layer 4 is formed on the substrate 1, and the stress properties of the insulating layer 4 are controlled to be consistent with the stress properties of the conductive film layer 2; the insulating layer 4 covers the conductive film layer 2. More specifically, the stress properties of the insulating layer 4 are controlled to be consistent with the stress properties of the conductive film layer 2, which means that if the conductive film layer 2 exhibits compressive stress, the insulating layer 4 also exhibits compressive stress; thus, the bending directions of the insulating layer 4 and the conductive film layer 2 are the same, thereby ensuring the adhesion between the two film layers, referring to Figure 2 , thereby avoiding the problem of "bulging" between the insulating layer 4 and the conductive film layer 2.

[0057] After a thin film is deposited on a substrate, it is in a state of strain. Based on the direction in which the film stress causes the substrate to bend, stress can be divided into tensile stress and compressive stress. Tensile stress occurs when the film is stretched outward by force, while the substrate is compressed inward, causing the film surface to concave. Due to the tensile stress, the film itself tends to shrink. If the tensile stress of the film exceeds the film's elastic limit, the film will rupture or even peel off the substrate and warp. Compressive stress presents the opposite phenomenon, with the film surface convex. Under the action of compressive stress, the film tends to expand toward the surface.

[0058] In one embodiment of the present invention, in step S1 of forming the conductive film layer 2, the substrate 1 is a transparent substrate, and a glass substrate may be selected as the substrate 1. The conductive film layer 2 is made of indium tin oxide (ITO). ITO is a mixture of 90% indium oxide (In2O3) and 10% tin oxide (SnO2), and is widely used as a transparent conductive film in liquid crystal displays.

[0059] In a specific embodiment of the present invention, in the step S1 of forming a conductive film layer 2, the conductive film layer 2 is formed in the light-transmitting area of ​​the array substrate. In addition to serving as a COM electrode, the conductive film layer 2 is a transparent conductive layer, which can also form a transparent capacitor with the insulating layer 4 and the pixel electrode layer in the light-transmitting area. In general, the capacitor of the array substrate is opaque, so it must be set in the non-light-transmitting area, thereby increasing the area of ​​the non-light-transmitting area and reducing the area of ​​the light-transmitting area. The capacitor of the embodiment of the present invention is a transparent capacitor, so that the capacitor area including the transparent capacitor can be located in the light-transmitting area, so that the pixel opening in the light-transmitting area can be designed to be larger, which is beneficial to improving the aperture ratio of the array substrate and improving the display effect.

[0060] In a specific embodiment of the present invention, in the step of heat treating the conductive film layer 2 in S2, the stress exhibited by the conductive film layer 2 after the heat treatment is related to the conditions of the heat treatment step. Generally speaking, the heat treatment temperature and heat treatment time will affect the crystallinity of the conductive film layer 2. High heat treatment temperature and long heat treatment time will increase the crystallinity of the conductive film layer 2. The higher the crystallinity, the greater the tensile stress of the conductive film layer 2.

[0061] If the stress of the conductive film layer 2 is less than -200 MPa, it will cause the conductive film layer 2 to become amorphous, thereby reducing the crystallinity of the conductive film layer 2. This reduced crystallinity will reduce the electrical conductivity of the conductive film layer 2 and cause the surface of the conductive film layer to be hydrogenated, affecting the transmittance of light. A negative stress value indicates that the conductive film layer 2 exhibits compressive stress; a positive stress value indicates that the conductive film layer 2 exhibits tensile stress. Since the insulating layer 4 often exhibits compressive stress after deposition, its negative stress value is generally large. Therefore, if the stress of the conductive film layer 2 is greater than 100 MPa, the conductive film layer 2 exhibits a large tensile stress, resulting in a significant difference between the stress of the conductive film layer 2 and the stress of the insulating layer 4. As a result, a "bulge" will form between the conductive film layer 2 and the insulating layer 4 after the insulating layer 4 is formed. If the "bulge" is located in a light-transmitting area, light passing through the "bulge" will be refracted, thereby affecting the display effect of the liquid crystal display device using the thin film transistor.

[0062] Therefore, considering the conductivity of the conductive film layer 2, its influence on light transmittance, and the stress matching problem with the insulating layer 4, the stress range of the conductive film layer 2 should be optionally controlled within a range of -200 MPa to 100 MPa.

[0063] Therefore, in order to control the stress range of the conductive film layer 2 to be between -200 MPa and 100 MPa, in the step S2, the temperature of the heat treatment is optionally selected to be less than 250°C.

[0064] During the heat treatment process, as the heat treatment temperature increases, the crystallinity of the conductive film layer 2 becomes higher, resulting in the conductive film layer 2 exhibiting more tensile stress; in order to reduce the tensile stress of the conductive film layer 2, the heat treatment temperature in the S2 step needs to be controlled at less than 250°C; under the above-mentioned heat treatment conditions, the stress range of the conductive film layer 2 is controlled between -200Mpa and -120Mpa, which is in line with the stress range of -200Mpa to 100Mpa.

[0065] In step S2, the heat treatment temperature may be selected to be less than 230°C. Under these heat treatment conditions, the stress range of the conductive film layer 2 is between -200 MPa and -150 MPa, exhibiting a stronger compressive stress, thereby matching the conductive film layer 2 with the insulating layer 4 and facilitating the reduction of "bulges" between the conductive film layer 2 and the insulating layer 4. It is understood that the stress range of the conductive film layer 2 can also be controlled by reducing the heat treatment time of the conductive film layer 2.

[0066] In the step S2, optionally, the heat treatment of the conductive film layer 2 includes: the heat treatment time is less than 60 minutes. In this embodiment, the stress range of the conductive film layer 2 is -130 MPa to -200 MPa.

[0067] In an optional embodiment of the present application, when the electrical conductivity of the conductive film layer 2 meets the basic requirements, in the S2 step, the heat treatment time is 0, that is, the heat treatment step can be skipped; after skipping the heat treatment step, the stress range of the conductive film layer 2 can generally be controlled within -200Mpa to 100Mpa; it can match the stress properties and stress range of the insulating layer 4, thereby avoiding the generation of "bulges" between the conductive film layer 2 and the insulating layer 4.

[0068] It should be understood that, in the step S2, the stress range of the conductive film layer 2 can be controlled within a range of -200 MPa to 100 MPa by simultaneously reducing the heat treatment temperature and the heat treatment time.

[0069] It should be understood that using indium tin oxide as the conductive film layer 2 is an optional embodiment. In other embodiments, the conductive film layer 2 may also be any of indium tin oxide, indium zinc oxide, aluminum zinc oxide, gallium-doped zinc oxide, zinc tin oxide, gallium tin oxide, fluorine-doped tin oxide, zinc oxide, and indium oxide. It should be understood that if other transparent conductive materials are used for the conductive film layer 2, the heat treatment conditions should also be modified accordingly, as long as the stress properties of the insulating layer 4 are controlled to be consistent with the stress properties of the conductive film layer 2.

[0070] In this embodiment, although the stress of the conductive film layer 2 can be controlled to be within an appropriate range, the electrical conductivity of the conductive film layer 2 provided in this embodiment will also be reduced compared to the conductive film layer 2 formed without reducing the heat treatment temperature or heat treatment time; in order to ensure that the electrical conductivity of the conductive film layer 2 still meets the design requirements, in the step of forming the conductive film layer 2 in S1, optionally, the forming of the conductive film layer 2 on the substrate 1 includes: forming the conductive film layer 2 on the substrate 1 by a magnetron sputtering method; the magnetron sputtering method refers to the electrons under the action of the electric field E, colliding with argon atoms in the process of flying toward the substrate, causing the electrons to ionize and generate argon positive ions and new electrons; the new electrons fly toward the substrate, and the argon ions are accelerated to fly toward the cathode target under the action of the electric field, and bombard the target surface with high energy, causing the target material to be sputtered. In the sputtered particles, neutral target atoms or molecules are deposited on the substrate to form a thin film; the forming methods of the conductive film layer 2 also include vacuum evaporation, chemical vapor deposition, spraying, hydrothermal method, sol-gel method, etc.; compared with the above methods, the film formed by the magnetron sputtering method has a better crystallization rate, so that the conductive film layer 2 formed by the magnetron sputtering method has better electrical conductivity even without heat treatment.

[0071] In a specific embodiment, the conductive film layer 2 is formed on the substrate 1 by magnetron sputtering, including: magnetron sputtering film formation under the conditions of sputtering power of 12 kW to 20 kW, chamber temperature of 25°C, sputtering time of 10 to 20 s, process pressure of 0.5 to 1 Pa, argon (Ar) flow rate of 500 sccm to 1280 sccm and no water supply.

[0072] In the above embodiment, the conductivity of the conductive film layer 2 formed by magnetron sputtering is related to the magnetron sputtering power. The greater the magnetron sputtering power, the thicker the conductive film layer 2 formed, the higher the crystallinity of the conductive film layer 2 formed, and the smaller the grain boundary ratio, thereby increasing the conductivity of the conductive film layer 2. It should be understood that excessive sputtering power may generate excessive high-energy particles. These high-energy particles bombard the conductive film layer 2, causing surface defects. Excessive defects may reduce the conductivity of the conductive film layer 2. Therefore, in this embodiment, the sputtering power is controlled within a range of 12 kW to 20 kW.

[0073] In the above embodiment, the argon gas flow rate is controlled at 500 sccm to 1280 sccm; if the argon gas flow rate is too high, it will lead to excessive sputtering particles and too fast film formation speed, thereby causing excessive defects in the conductive film layer 2 and reducing the conductivity of the conductive film layer 2; if the argon gas flow rate is too low, it will affect the ignition and is not conducive to the formation of the conductive film layer 2; therefore, considering the above reasons, the argon gas flow rate is controlled at 500 sccm to 1280 sccm.

[0074] In the above embodiment, the process pressure is controlled at 0.5 to 1 Pa. The formation of the coating film is that the target particles undergo adsorption, condensation, surface diffusion migration, collision and combination to form stable crystal nuclei. Then, through adsorption, the crystal nuclei grow into small islands. After the islands grow, they connect and coalesce to form a continuous film. The size of the gas pressure affects the energy of the particles, and thus affects the formation of the film nuclei. When the gas pressure is too low, the sputtered particles have high energy, which easily forms hillocks or voids on the substrate, causing defects in the coating film. As the pressure increases, the probability of the sputtered particles colliding with argon atoms in the process of flying towards the substrate increases, and the energy decreases when reaching the substrate, which is conducive to removing defects caused by high energy. However, when the gas pressure is too high, the energy of the sputtered particles is too low when they reach the substrate, which affects the crystallization of the coating film.

[0075] In the above embodiment, the average square resistance of the formed conductive film layer 2 is 70Ω / □.

[0076] In the embodiment of the present invention, the conditions of the magnetron sputtering method are controlled so that the formed conductive film layer 2 has excellent electrical conductivity. When the heat treatment temperature is lowered, the sheet resistance is also within the designed range.

[0077] Observe the crystal structure of the conductive film layer 2 formed in the above embodiment using a microscope; Figure 6 3 is a crystal phase diagram of the conductive film layer 2 when viewed from above. Figure 7 is a crystal phase diagram of a side cross-section of the thin film transistor; Figure 6 and Figure 7 The information shows that the conductive film layer 2 formed under the above magnetron sputtering conditions has a dense microcrystalline structure. The dense microcrystalline structure enables the conductive film layer 2 to have excellent electrical conductivity.

[0078] In a specific embodiment of the present invention, the step of forming the insulating layer in S3 includes:

[0079] An insulating layer 4 is formed on the substrate 1 by low-pressure chemical vapor deposition. In this embodiment, the insulating layer 4 may be a silicon nitride (SiN) film. Furthermore, the insulating layer 4 adopts low-pressure process conditions to obtain a dense SiN film, which has a strong ability to block H ions. Under the low-pressure process, the silicon nitride film is deposited slowly, so it is deposited more densely. The denser the silicon nitride film, the greater its compressive stress; at the same time, the denser the silicon nitride film, the greater its refractive index.

[0080] To prevent bulging between the insulating layer 4 and the conductive film layer 2, the stress difference between the insulating layer 4 and the conductive film layer 2 should not exceed 800 MPa. Considering that the refractive index of the insulating layer 4 needs to be greater than 1.8, in an optional embodiment, the stress range of the insulating layer 4 is controlled to be between -1000 MPa and -500 MPa. In an optional embodiment, the stress difference between the insulating layer 4 and the conductive film layer 2 is less than or equal to 700 MPa. By controlling the stress of the insulating layer 4 within the above range to match the stress range of the conductive film layer 2, the stress of the insulating layer 4 and the conductive film layer 2 is prevented from bulging. In the above embodiment, the stress range of the insulating layer 4 is controlled by controlling the molding process of the insulating layer 4. In an optional embodiment, the insulating layer 4 is formed on the conductive film layer 2, including: forming the insulating layer 4 under the conditions of power 5 to 8.5 kW, chamber pressure 700 mtorr to 1000 mtorr, silane (SiH4) flow rate 1400 to 2000 sccm, ammonia (NH3) flow rate 8000 to 11200 sccm, nitrogen (N2) flow rate 38000 to 50000 sccm, and film forming temperature 340 to 360°C.

[0081] It should be understood that the above-mentioned molding process of the insulating layer 4 is an optional embodiment. In other embodiments, the insulating layer 4 may also be made of silicon oxide (SiO x ) film or silicon oxide (SiO x ), silicon nitride (SiN x ) Laminated structure film.

[0082] In one embodiment, reference Figure 4 as well as Figure 5 , the manufacturing method of the thin film transistor comprises the following steps:

[0083] S01. The conductive film layer 2 is formed on the substrate 1;

[0084] S02. forming a gate 3 on the substrate 1,

[0085] S03. The insulating layer 4 is formed on the substrate 1; the insulating layer 4 covers the conductive film layer 2 and the gate 3;

[0086] S04. An active layer 7 , a source layer 5 and a drain layer 6 are formed on the insulating layer 4 .

[0087] The layered structure of the thin film transistor is referenced Figure 5 .

[0088] In the above embodiment, the active layer 7 , the source electrode 5 , and the drain electrode 6 are formed on the insulating layer 4 ; this includes forming the active layer 7 on the insulating layer 4 ; and forming the source electrode 5 and the drain electrode 6 on the active layer 7 .

[0089] In the above embodiment, the gate 3 is formed by photolithography and is made of Cu. The gate 3 is also stacked, including a molybdenum-niobium alloy (MoNb) layer and a copper (Cu) layer. The molybdenum-niobium alloy layer can improve the adhesion between the copper layer and the substrate 1. The gate 3 can also be made of one or more materials selected from molybdenum (Mo), aluminum (Al), copper (Cu), or alloys.

[0090] In the above embodiment, the gate 3 and the conductive film layer 2 are located in the same layer; the gate 3 is located in the non-light-transmitting area; and the conductive film layer 2 is located in the light-transmitting area.

[0091] In the above embodiment, the source stage 5 and the drain stage 6 can be made of one or more materials selected from molybdenum, aluminum, copper or alloys.

[0092] In the above embodiment, the active layer 7 can be made of any one or more materials selected from the group consisting of indium tin oxide, indium zinc oxide, aluminum zinc oxide, gallium-doped zinc oxide, zinc tin oxide, gallium tin oxide, fluorine-doped tin oxide, zinc oxide, and indium oxide. In the above embodiment, the light shielding layer 10 can be made of molybdenum or a mixed metal layer of molybdenum and copper.

[0093] In an optional embodiment, the thin film transistor may further include a light-shielding layer (not shown in the figure); the projection of the light-shielding layer on the substrate 1 covers the orthographic projection of the active layer 7 on the substrate 1; so as to achieve a light-shielding effect on the active layer 7.

[0094] In the above embodiment, the light shielding layer may be a metal light shielding layer;

[0095] In the above embodiment, the light-shielding layer can also be an amorphous silicon light-shielding layer. Compared with the metal light-shielding layer, the amorphous silicon light-shielding layer will not introduce any parasitic capacitance into the display panel, thereby improving the performance of the driving circuit, and the hydrogen in the amorphous silicon will not have any effect on the TFT active layer.

[0096] An embodiment of the present invention further provides an array substrate, the array substrate comprising the thin film transistor according to any one of the aforementioned embodiments;

[0097] Since the thin film transistor is manufactured using the aforementioned method, no “bulging” phenomenon will occur between the conductive film layer 2 and the insulating layer 4 .

[0098] This embodiment further provides a method for manufacturing the array substrate; the method for manufacturing the array substrate comprises the following steps:

[0099] S001: manufacturing the thin film transistor by using the method of any one of the aforementioned embodiments;

[0100] S002: forming a passivation layer (not shown) on the thin film transistor; the passivation layer serves to insulate and planarize the array substrate;

[0101] S003: forming a pixel electrode (not shown) on the passivation layer, wherein the pixel electrode passes through the contact hole of the passivation layer and is electrically connected to the drain electrode 6.

[0102] In the above step S002, the passivation layer may be a silicon oxide film or a silicon oxide and silicon nitride stacked structure film.

[0103] In the above step S003, the pixel electrode may be made of any one or more materials selected from the group consisting of indium tin oxide, indium zinc oxide, aluminum zinc oxide, gallium-doped zinc oxide, zinc tin oxide, gallium tin oxide, fluorine-doped tin oxide, zinc oxide and indium oxide.

[0104] An embodiment of the present invention further provides a display device, wherein the liquid crystal display device includes the array substrate described in any one of the aforementioned embodiments.

[0105] Since the array substrate does not have the aforementioned “bulging” defect, the display device has a better display effect compared to the prior art.

[0106] In an optional embodiment, the display device may be an LCD display device, comprising: a housing, a light source installed in the housing;

[0107] A polarizing lens and a filter mounted on the housing and located on the light-emitting side; and

[0108] a display module installed in the housing and located between the filter and the light source;

[0109] The display module includes the array substrate and liquid crystal.

[0110] The light source can be an LED light source or a Mini LED light source.

[0111] In an optional embodiment, the display device may be an OLED display device, which includes: a housing, a backlight module installed in the housing; and

[0112] A display screen mounted on the housing and not on the light-emitting side of the backlight module;

[0113] The backlight module includes the array substrate and a light-emitting layer formed on the array substrate.

[0114] The light-emitting layer includes a plurality of light-emitting elements distributed in an array, and the light-emitting elements correspond to the pixel openings of the array substrate. The light-emitting element includes an anode, a light-emitting structure located on the anode, and a cathode located on the light-emitting structure, and the pixel opening exposes the anode. The light-emitting layer may further include a first common layer and a second common layer. The first common layer includes a hole injection layer (HIL) located on the surface of the anode and a hole transport layer (HTL) located on the hole injection layer. The second common layer includes an electron transport layer (ETL) located on the surface of the light-emitting structure and an electron injection layer (EIL) located on the surface of the electron transport layer away from the light-emitting structure.

[0115] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0116] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to be embodied in the widest possible manner consistent with the principles and novel features claimed herein.

Claims

1. A method for manufacturing a thin film transistor, characterized in that: The following steps are involved: forming a conductive thin film layer on a substrate; performing heat treatment on the conductive film layer; controlling the stress of the conductive film layer to be within a first preset range; forming an insulating layer on the substrate; The insulating layer covers the conductive film layer, and the stress difference between the insulating layer and the conductive film layer is less than or equal to 700 MPa; The controlling the stress of the conductive film layer to be within a first preset range includes: Controlling the stress of the conductive film layer to be within a range of -200 MPa to 100 MPa; The step of forming an insulating layer on the substrate comprises: The chamber pressure is controlled to be 700-1000 mtorr, and an insulating layer is formed on the substrate by low-pressure chemical vapor deposition, wherein the stress range of the insulating layer is -1000 MPa to -500 MPa.

2. The method for manufacturing a thin film transistor according to claim 1, wherein: The heat treatment of the conductive film layer comprises: The temperature of the heat treatment is less than 250°C.

3. The method for manufacturing a thin film transistor according to claim 1, wherein: The heat treatment of the conductive film layer comprises: The heat treatment time is less than 60 minutes.

4. The method for manufacturing a thin film transistor according to claim 3, wherein: The heat treatment of the conductive film layer comprises: The heat treatment time is 0 min.

5. The method for manufacturing a thin film transistor according to claim 1, wherein: The step of forming a conductive film layer on a substrate comprises: The conductive film layer is formed on the substrate by magnetron sputtering.

6. The method for manufacturing a thin film transistor according to claim 5, wherein: The method of forming the conductive film layer on the substrate by magnetron sputtering includes: Under the condition that the sputtering power is 12kW-20kW, the conductive thin film layer is formed on the substrate by the magnetron sputtering method.

7. The method for manufacturing a thin film transistor according to claim 5, wherein: The method of forming the conductive film layer on the substrate by magnetron sputtering includes: Under the conditions of sputtering power of 12 kW to 20 kW, chamber temperature of 25°C, sputtering time of 10 to 20 s, process pressure of 0.5 to 1 Pa, argon flow rate of 500 sccm to 1280 sccm and no water supply, the conductive film layer is formed on the substrate by the magnetron sputtering method.

8. The method for manufacturing a thin film transistor according to claim 1, wherein: The method for manufacturing the thin film transistor includes: forming the conductive film layer on the substrate; forming a gate on the substrate; forming the insulating layer on the substrate; the insulating layer covers the conductive film layer; An active layer, a source layer, and a drain layer are formed on the insulating layer.

9. An array substrate, characterized in that: The invention comprises a thin film transistor obtained by the method for manufacturing a thin film transistor according to any one of claims 1 to 8.

10. A display device, characterized in that: Including the array substrate according to claim 9.

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