Nitride semiconductor light-emitting device and method for manufacturing the same

Abstract

The present invention provides a nitride semiconductor light-emitting element with high luminous efficiency. At least one barrier layer located between the first well layers among the plurality of barrier layers and at least one barrier layer located between the second well layers among the plurality of barrier layers include a first barrier layer containing an n-type impurity and a second barrier layer containing an n-type impurity with a lower n-type impurity concentration than that of the first barrier layer and located on the p-side nitride semiconductor layer side of the first barrier layer. The n-type impurity concentration of the first barrier layer located between the first well layers is higher than the n-type impurity concentration of the first barrier layer located between the second well layers. The difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer of the barrier layer located between the first well layers among the plurality of barrier layers is larger than the difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer of the barrier layer located between the second well layers among the plurality of barrier layers.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor light-emitting element and a method for manufacturing the same. Background Art

[0002] Patent Document 1 describes a semiconductor light-emitting element including an n-type semiconductor layer, an intermediate layer having an active layer, a p-type semiconductor layer, and barrier layers provided between a plurality of well layers.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: International Publication No. 2019 / 106931 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In the luminous efficiency of the above nitride light-emitting element, there is room for improving the luminous efficiency. Therefore, an object of the present disclosure is to provide a nitride semiconductor light-emitting element and a method for manufacturing the same that achieve an improvement in luminous efficiency.

[0008] Technical Solutions for Solving the Problems

[0009] To achieve the above object, the nitride semiconductor light-emitting element of the present disclosure includes an n-side nitride semiconductor layer, a p-side nitride semiconductor layer, and an active layer provided between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer, wherein

[0010] the active layer has a plurality of stacked portions including well layers and barrier layers,

[0011] the well layers include a plurality of first well layers and a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers,

[0012] at least one of the barrier layers located between the first well layers and at least one of the barrier layers located between the second well layers among the plurality of barrier layers include a first barrier layer containing an n-type impurity and a second barrier layer containing an n-type impurity having a lower n-type impurity concentration than the first barrier layer and located closer to the p-side nitride semiconductor layer than the first barrier layer,

[0013] the n-type impurity concentration of the first barrier layer located between the first well layers is higher than the n-type impurity concentration of the first barrier layer located between the second well layers,

[0014] The difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer in the barrier layers located between the first well layers among the multiple barrier layers is larger than the difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer in the barrier layers located between the second well layers among the multiple barrier layers.

[0015] In addition, the method for manufacturing a nitride semiconductor light-emitting device according to the present disclosure includes:

[0016] a step of forming an n-side nitride semiconductor layer;

[0017] a step of forming an active layer having a plurality of stacked portions including well layers and barrier layers after the step of forming the n-side nitride semiconductor layer;

[0018] a step of forming a p-side nitride semiconductor layer after the step of forming the active layer,

[0019] The step of forming the active layer includes a step of forming a plurality of the barrier layers and a step of forming a plurality of the well layers,

[0020] The step of forming a plurality of the barrier layers respectively includes a step of forming a first barrier layer containing an n-type impurity and a step of forming a second barrier layer, the second barrier layer contains an n-type impurity having an n-type impurity concentration lower than that of the first barrier layer, and is located closer to the p-side nitride semiconductor layer than the first barrier layer,

[0021] The step of forming a plurality of the well layers includes a step of forming a plurality of first well layers and a step of forming a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers,

[0022] In the step of forming a plurality of the barrier layers,

[0023] the n-type impurity concentration of the first barrier layer located between the first well layers is formed to be higher than the n-type impurity concentration of the first barrier layer located between the second well layers,

[0024] The difference between the n-type impurity concentration of the first barrier layer located between the first well layers and the n-type impurity concentration of the second barrier layer is formed to be larger than the difference between the n-type impurity concentration of the first barrier layer located between the second well layers and the n-type impurity concentration of the second barrier layer.

[0025] In addition, the method for manufacturing a nitride semiconductor light-emitting device according to the present disclosure includes:

[0026] a step of forming an n-side nitride semiconductor layer;

[0027] After the step of forming the n-side nitride semiconductor layer, a step of forming an active layer having a plurality of stacked portions including a well layer and a barrier layer;

[0028] After the step of forming the active layer, a step of forming a p-side nitride semiconductor layer,

[0029] The step of forming the active layer includes a step of forming a plurality of the barrier layers and a step of forming a plurality of the well layers,

[0030] The steps of forming a plurality of the barrier layers each have a step of forming a first barrier layer while supplying an n-type impurity gas and a step of forming a second barrier layer located closer to the p-side nitride semiconductor layer than the first barrier layer while supplying the n-type impurity gas at a flow rate smaller than that for the formation of the first barrier layer,

[0031] The steps of forming a plurality of the well layers have a step of forming a plurality of first well layers and a step of forming a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers,

[0032] In the steps of forming a plurality of the barrier layers, the flow rate of the n-type impurity gas when forming the first barrier layer between the first well layers is made larger than the flow rate of the n-type impurity gas when forming the first barrier layer between the second well layers.

[0033] Advantageous Effects of the Invention

[0034] According to the nitride semiconductor light-emitting device of the present disclosure configured as described above, an improvement in luminous efficiency can be achieved.

[0035] In addition, according to the method of manufacturing a nitride semiconductor light-emitting device of the present disclosure, a nitride semiconductor light-emitting device with high luminous efficiency can be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a cross-sectional view showing the structure of the nitride semiconductor light-emitting device of the present disclosure.

[0037] Figure 2 It is a schematic diagram showing the structure of the active layer of the nitride semiconductor light-emitting device according to the first embodiment of the present disclosure.

[0038] Figure 3 It is a schematic diagram showing the structure of the active layer of the nitride semiconductor light-emitting device according to the second embodiment of the present disclosure.

[0039] Figure 4 It is a process flow diagram showing the manufacturing process of the nitride semiconductor light-emitting device of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0040] It is considered that in a semiconductor light-emitting device having an active layer with a multi-quantum well structure in which well layers and barrier layers are alternately stacked, by doping n-type impurities in the barrier layers, the resistance of the light-emitting device can be reduced and the forward voltage can be lowered. However, when the n-type impurity concentration in the barrier layer increases, holes supplied from the p-side semiconductor layer are likely to be largely consumed in the well layer near the p-side semiconductor layer in the active layer. As a result, since it is difficult to supply holes to the well layer near the center in the active layer, there are problems such as difficulty in improving the light-emitting efficiency.

[0041] The invention of the present disclosure is the result of in-depth research based on the above insights, and is an invention that adjusts the n-type impurity concentration in the barrier layer to improve the light-emitting efficiency as a whole.

[0042] As a specific structure of the active layer that effectively exhibits this function, it has a plurality of stacked portions including well layers and barriers. The well layer includes a plurality of first well layers on the n-side nitride semiconductor layer side and a plurality of second well layers on the p-side nitride semiconductor layer side. The plurality of barrier layers each include a first barrier layer and a second barrier layer located on the p-side nitride semiconductor layer side with respect to the first barrier layer.

[0043] The first barrier layer contains n-type impurities. Regarding the n-type impurity concentration of the first barrier layer, the n-type impurity concentration of the first barrier layer between the first well layers is higher than the n-type impurity concentration of the first barrier layer between the second well layers. In addition, the second barrier layer contains a lower n-type impurity than the first barrier layer.

[0044] Regarding the relationship between the n-type impurity concentrations of these first barrier layer and second barrier layer, the difference between the n-type impurity concentration of the first barrier layer between the first well layers and the n-type impurity concentration of the second barrier layer is set to be larger than the difference between the n-type impurity concentration of the first barrier layer between the second well layers and the n-type impurity concentration of the second barrier layer. By setting the n-type impurity concentration in this way, holes can be easily supplied to the well layer near the center of the active layer. As a result, even in the well layer near the center of the active layer, electrons and holes can be efficiently recombined. Therefore, the number of well layers that are conducive to light emission can be increased, and thus the light-emitting efficiency can be improved. In addition, since the deterioration of the crystallinity of the semiconductor layer can be suppressed, the light-emitting efficiency can be improved.

[0045] Next, a more specific mode will be described in detail. In addition, in the nitride semiconductor light-emitting device of the present embodiment described later, as the nitride semiconductor, a III-V nitride semiconductor (In X Al Y Ga 1-X-YN (where 0 ≤ X, 0 ≤ Y, and X + Y ≤ 1)), B can also be used as part of the group III element, and it can also be a mixed crystal in which part of the group V element N is replaced by P, As, or Sb. These nitride semiconductor layers can be formed, for example, by metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), etc.

[0046] In addition, as the nitride semiconductor light-emitting device of the present embodiment, a nitride semiconductor light-emitting device having a peak emission wavelength of 500 nm or more and having an active layer including a well layer containing a large amount of In (for example, a green light-emitting device in which the ratio of In in the well layer composed of InGaN is about 20.0 to 28.0%) will be described as an example. In addition, the peak emission wavelength is not limited to the above wavelength. In addition, in this specification, when using characters and described as A to B, it includes the case where the character is A and the case where the character is B.

[0047] -Regarding nitride semiconductor light-emitting devices-

[0048] <<First Embodiment>>

[0049] Next, with reference to Figure 1 and Figure 2 the nitride semiconductor light-emitting device of the first embodiment of the present disclosure will be described. The nitride semiconductor light-emitting device 100 of the present embodiment includes a substrate 1, an n-side nitride semiconductor layer 10 provided on the substrate 1, a p-side nitride semiconductor layer 20, and an active layer 5 located between the n-side nitride semiconductor layer 10 and the p-side nitride semiconductor layer 20. The n-side nitride semiconductor layer 10 includes a base layer 2, an n-side contact layer 3, and an n-side superlattice layer 4. The p-side nitride semiconductor layer 20 includes a p-type barrier layer 6 and a p-side contact layer 7. First, the active layer 5 of the nitride semiconductor light-emitting device of the present disclosure will be described, and then the substrate 1, the n-side nitride semiconductor layer 10, and the p-side nitride semiconductor layer 20 will be described in sequence.

[0050] (Active layer 5)

[0051] The active layer 5 includes a plurality of stacked portions 5bw, and the plurality of stacked portions 5bw include a well layer and a barrier layer. In Figure 2 way, a stacked structure including four stacked portions 5bw in which a well layer is stacked on a barrier layer is exemplified.

[0052] As an example, the well layer can use a nitride semiconductor containing In, and by appropriately setting the In composition ratio, blue to green light can be emitted. For example, when using In X Al Y Ga 1-X-YWhen N(0≦X, 0≦Y, X + Y≦1), by setting the In composition ratio x to a desired amount, the emission peak wavelength of the nitride semiconductor light-emitting element can be set in the range of 430 nm to 570 nm, for example, in the range of 500 nm to 570 nm for emitting green light.

[0053] The well layer in the active layer 5 (refer to Figure 2 ) includes a plurality of first well layers 5w1 (two in the illustrated example) located on the n-side nitride semiconductor layer 10 side, and a plurality of second well layers 5w2 (two in the illustrated example) located on the p-side nitride semiconductor layer 20 side with respect to the plurality of first well layers 5w1. In addition, in order to suppress the decomposition of InGaN with respect to the first well layer 5w1 and the second well layer 5w2, an intermediate layer 5c may be stacked on each well layer.

[0054] The first well layer 5w1 may also be a layer that suppresses the contribution to light emission compared to the well layer on the p-side nitride semiconductor layer 20 side with respect to the first well layer 5w1. The film thickness of the first well layer 5w1 is set, for example, in the range of 0.5 to 4.0 nm, preferably in the range of 1.0 to 2.5 nm, and more preferably in the range of 1.2 to 1.9 nm. In the Figure 2 illustrated manner, it is set to 1.6 nm.

[0055] The second well layer 5w2 is a layer that enables the electrons supplied via the first well layer 5w1 and the holes supplied from the p-side nitride semiconductor layer 20 to recombine efficiently and emit light with a high output. The second well layer 5w2 may be thicker than the first well layer 5w1. By making the second well layer 5w2 thicker than the first well layer 5w1, many electrons and holes can recombine in the second well layer that is more conducive to light emission. The film thickness of the second well layer 5w2 is set, for example, in the range of 1.5 to 5.5 nm, preferably in the range of 2.0 to 4.0 nm, and more preferably in the range of 2.5 to 3.2 nm. In the Figure 2 illustrated manner, it is set to 3.0 nm.

[0056] The barrier layer in the active layer 5 is made of a material that confines carriers in the well layer. For example, it may be made of GaN, InGaN, or AlGaN having a wider bandgap than the well layer. The barrier layer exists in a manner of being sandwiched by the well layer, and includes a first barrier layer 5b1 located on the n-side nitride semiconductor layer 10 side and a second barrier layer 5b2 located on the p-side nitride semiconductor layer 20 side with respect to the first barrier layer 5b1.

[0057] The first barrier layer 5b1 contains n-type impurities. By containing n-type impurities, the first barrier layer 5b1 can reduce the forward voltage of the light-emitting element. The n-type impurities may include, for example, Si or Ge, and in this embodiment, Si is used. Regarding the n-type impurity concentration of the first barrier layer 5b1, the n-type impurity concentration of the first barrier layer 5b1 between the first well layers 5w1 is higher than the n-type impurity concentration of the first barrier layer 5b1 between the second well layers 5w2. The n-type impurity concentration of the first barrier layer 5b1 between the first well layers 5w1 can be set, for example, in the range of 1.0×10 17 to 1.0×10 19 / cm 3 The range is preferably 3.0×10 17 to 5.0×10 18 / cm 3 The range is more preferably 5.0×10 17 to 2.0×10 18 / cm 3 The n-type impurity concentration of the first barrier layer 5b1 between the second well layers 5w2 can be set, for example, in the range of 1.0×10 17 to 1.0×10 19 / cm 3 The range is preferably 3.0×10 17 to 5.0×10 18 / cm 3 The range is more preferably 4.0×10 17 to 1.0×10 18 / cm 3 In the method shown as an example Figure 2 The n-type impurity concentration of the first barrier layer 5b1 between the first well layers 5w1 is 1.3×10 18 / cm 3 The n-type impurity concentration of the first barrier layer 5b1 between the second well layers 5w2 is 8.8×10 17 / cm 3 .

[0058] Furthermore, the film thickness of the first barrier layer 5b1 between the first well layers 5w1 can be greater than the film thickness of the first barrier layer 5b1 between the second well layers 5w2. By making the film thickness of the first barrier layer 5b1 between the first well layers 5w1 greater than the film thickness of the first barrier layer 5b1 between the second well layers 5w2, holes can be easily supplied to the second well layer 5w2 that is conducive to light emission and the well layer near the center of the active layer. The film thickness of the first barrier layer 5b1 between the first well layers 5w1 can be set, for example, in the range of 5 to 30 nm, preferably in the range of 10 to 25 nm, more preferably in the range of 14 to 18 nm. The film thickness of the first barrier layer 5b1 between the second well layers 5w2 can be set, for example, in the range of 5 to 30 nm, preferably in the range of 6 to 16 nm, more preferably in the range of 8 to 11 nm. In the mode represented as an example Figure 2 , the film thickness of the first barrier layer 5b1 between the first well layers 5w1 is 15.8 nm, and the film thickness of the first barrier layer 5b1 between the second well layers 5w2 is 9.5 nm.

[0059] The second barrier layer 5b2 contains n-type impurities with a lower n-type impurity concentration than the first barrier layer 5b1. In addition, by making the second barrier layer 5b2 between the first well layers 5w1 an undoped semiconductor layer, the deterioration of the crystallinity of the second barrier layer 5b2 between the first well layers 5w1 and the semiconductor layers formed thereafter can be suppressed. On the other hand, the n-type impurity concentration of the second barrier layer 5b2 between the second well layers 5w2 can be set, for example, in the range of 1.0×10 17 ~1.0×10 19 / cm 3 , preferably in the range of 2.0×10 17 ~1.0×10 18 / cm 3 , more preferably in the range of 3.0×10 17 ~8.0×10 17 / cm 3 . In the mode represented as an example Figure 2 , the n-type impurity concentration of the second barrier layer 5b2 between the second well layers 5w2 is 6.3×10 17 / cm 3 . In addition, an undoped semiconductor layer refers to a semiconductor layer formed without supplying n-type impurity gas. Therefore, a semiconductor layer that can incorporate n-type impurities present in the atmosphere in the reaction furnace even without supplying n-type impurity gas during the formation of the semiconductor layer is also referred to as an undoped semiconductor layer. For example, an undoped semiconductor layer refers to a semiconductor layer with an n-type impurity concentration of 1.7×10 17 / cm 3 or less.

[0060] Further, the film thickness of the second barrier layer 5b2 between the first well layers 5w1 can be set, for example, in the range of 0.5 to 5.0 nm, preferably in the range of 0.5 to 1.5 nm, more preferably in the range of 0.5 to 0.8 nm. The film thickness of the second barrier layer 5b2 between the second well layers 5w2 can be set, for example, in the range of 0.5 to 5.0 nm, preferably in the range of 0.5 to 1.5 nm, more preferably in the range of 0.5 to 0.8 nm. In the example shown as Figure 2 mode, the film thicknesses of the second barrier layer 5b2 between the first well layers 5w1 and the second barrier layer 5b2 between the second well layers 5w2 are both 0.6 nm. In addition, regarding the film thickness, it is not limited to this example, and different film thicknesses can be set.

[0061] Regarding the relationship between the n-type impurity concentrations of the first barrier layer 5b1 and the second barrier layer 5b2, the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the first well layers 5w1 is set to be larger than the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the second well layers 5w2. In the example shown as Figure 2 mode, the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the first well layers 5w1 is 1.3×10 18 / cm 3 (first barrier layer: 1.3×10 18 / cm 3 , second barrier layer: undoped semiconductor layer), and the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the second well layers 5w2 is 2.5×10 17 / cm 3 (first barrier layer: 8.8×10 17 / cm 3 , second barrier layer: 6.3×10 17 / cm 3 ).

[0062] Here, regarding the reason for setting the above n-type impurity concentration, it is explained by considering the energy band of the valence electron band in the active layer. In the energy band of the valence electron band of the structure of the barrier layer including the undoped semiconductor layer as the barrier layer, since the energy level difference between the well layer and the barrier layer is large, holes are difficult to cross the barrier layer. As a result, it is difficult to supply holes in the well layer near the center of the active layer.

[0063] On the other hand, as a barrier layer located between the second well layers 5w2, the valence band energy levels of the structure including the first barrier layer 5b1 containing n-type impurities and the second barrier layer 5b2 containing n-type impurities with a lower concentration than the first barrier layer 5b1 decrease at the adjacent positions of the well layer and the barrier layer, enabling the energy level difference between the well layer and the barrier layer to be smaller than the case where the barrier layer is an undoped semiconductor layer. As a result, since holes can easily cross the barrier layer, electrons can be easily supplied even in the well layer near the center of the active layer, improving the light emission efficiency. Further, in the barrier layer located between the first well layers 5w1, by making the amount of n-type impurities doped into the second barrier layer 5b2 undoped or less than that of the second barrier layer 5b2 located between the second well layers 5w2, the deterioration of the crystallinity of the semiconductor layer caused by the doping of n-type impurities into the semiconductor layer is suppressed. As a result, the difference in the n-type impurity concentration between the first barrier layer and the second barrier layer located between the first well layers is larger than the difference in the n-type impurity concentration between the first barrier layer and the second barrier layer located between the second well layers.

[0064] Next, the structure other than the active layer 5 of the nitride semiconductor light-emitting device of the present disclosure will be described.

[0065] (Undoped semiconductor layer 5u)

[0066] An undoped semiconductor layer 5u may also be provided between the p-side nitride semiconductor layer 20 and the second well layer 5w2 closest to the p-side nitride semiconductor layer 20. By providing the undoped semiconductor layer 5u, diffusion of p-type impurities from the p-side nitride semiconductor layer 20 into the active layer 5 can be prevented, and deterioration of the reliability of the light-emitting device can be suppressed. The material of the undoped semiconductor layer 5u may be any material that appropriately suppresses the diffusion of p-type impurities. From the viewpoint of ease of layer formation, the same materials as those of the first barrier layer and the second barrier layer (such as GaN, InGaN, or AlGaN) may also be used. In addition, different materials may also be used. The film thickness of the undoped semiconductor layer 5u can be set, for example, in the range of 0.5 to 15 nm, preferably in the range of 2 to 10 nm, and more preferably in the range of 4 to 6 nm.

[0067] (Substrate 1)

[0068] Substrate 1 (refer to Figure 1 ) For example, an insulating substrate such as sapphire or spinel (MgAl2O4) having any one of the C-plane, R-plane, and A-plane as the main plane can be used. Among them, when the nitride semiconductor light-emitting device 100 uses a nitride semiconductor, a sapphire substrate having the C-plane as the main plane is preferably used. In addition, as the substrate 1, SiC (including 6H, 4H, 3C), ZnS, ZnO, GaAs, Si, etc. can also be used. It is also possible not to have the substrate 1 ultimately.

[0069] (n-side nitride semiconductor layer 10)

[0070] As Figure 1 shown, the n-side nitride semiconductor layer 10 sequentially includes a base layer 2, an n-side contact layer 3, and an n-side superlattice layer 4 from the substrate 1 side. The n-side nitride semiconductor layer 10 includes at least one n-type semiconductor layer containing an n-type impurity. As the n-type impurity, for example, Si or Ge can be used.

[0071] The base layer 2 is disposed between the substrate 1 and the n-side contact layer 3. By providing the base layer 2, an n-side contact layer 3 with high crystallinity can be formed on the upper surface of the base layer 2. The base layer 2 can be, for example, AlGaN or GaN. In addition, a buffer layer can be formed between the base layer 2 and the substrate 1. The buffer layer is a layer for suppressing the lattice mismatch between the substrate 1 and the base layer 2. For example, undoped AlGaN or GaN can be used.

[0072] The n-side contact layer 3 is disposed on the upper surface of the base layer 2 and at least a part thereof contains an n-type impurity. As Figure 1 shown, an n-electrode 8 is formed on the upper surface of the n-side contact layer 3. In order to supply electrons from the n-electrode 8 to the active layer 5, the n-side contact layer 3 is preferably doped with a relatively high concentration of n-type impurity. The n-type impurity concentration of the n-side contact layer 3 can be set, for example, to 6×10 18 / cm 3 ~1×10 19 / cm 3 . The n-side contact layer 3 is preferably composed of GaN, AlGaN, AlN, or InGaN. The n-side contact layer 3 can also have a stacked structure. For example, undoped GaN and GaN doped with an n-type impurity can be alternately stacked. The film thickness of the n-side contact layer 3 can be, for example, 5 μm to 20 μm.

[0073] The n-side superlattice layer 4 is disposed on the upper surface of the n-side contact layer 3. By providing the n-side superlattice layer 4, the lattice relaxation between the n-side contact layer 3 and the active layer 5 can be suppressed, and the crystallinity of the active layer 5 can be made good. The n-side superlattice layer 4 has a structure in which semiconductor layers with different lattice constants are alternately stacked. The n-side superlattice layer 4 includes, for example, n pairs of single pairs, and each single pair includes an undoped InGaN layer and an undoped GaN layer. The number of pairs n of the n-side superlattice layer 4 can be set, for example, in the range of 10 to 40, preferably in the range of 15 to 35, and more preferably in the range of 25 to 35.

[0074] (p-side nitride semiconductor layer 20)

[0075] As Figure 1As shown, the p-side nitride semiconductor layer 20 includes a p-type barrier layer 6 and a p-side contact layer 7 in this order from the active layer 5 side. The p-side nitride semiconductor layer 20 includes at least one p-type semiconductor layer containing a p-type impurity. As the p-type impurity, for example, Mg or the like can be used.

[0076] The p-type barrier layer 6 is located at the position closest to the active layer 5 in the p-side nitride semiconductor layer 20. The p-type barrier layer 6 is a layer provided to confine electrons. For example, it can be composed of GaN, AlGaN, etc. containing a p-type impurity such as Mg. The bandgap energy of the p-type barrier layer 6 is larger than the bandgap energy of the first barrier layer 5b1 of the active layer 5. As an example of the film thickness of the p-type barrier layer 6, for example, it can be set to 10 nm to 50 nm. The p-type impurity concentration of the p-type barrier layer 6 can be set to 2×10 20 / cm 3 ~6×10 20 / cm 3 .

[0077] The p-side contact layer 7 is a layer on which the p-electrode 9 is formed on the upper surface. The p-side contact layer 7 can be composed of GaN, AlGaN, etc. containing a p-type impurity such as Mg. As an example of the film thickness of the p-side contact layer 7, for example, it can be set to a thickness of 10 nm to 150 nm.

[0078] As described above, in the nitride semiconductor light-emitting element 100 according to the present embodiment, holes can be easily supplied to the potential well layer near the center of the active layer. As a result, even in the potential well layer near the center of the active layer, electrons and holes can be efficiently recombined, so that the light-emitting efficiency can be improved. In addition, deterioration of the crystallinity of the semiconductor layer can be suppressed.

[0079] <<Second Embodiment>>

[0080] Next, refer to Figure 3 to describe the second embodiment of the present disclosure. In addition, regarding the same structures as those in the first embodiment (substrate 1, base layer 2 provided on the substrate 1, n-side nitride semiconductor layer 10, and p-side nitride semiconductor layer 20), the description is omitted.

[0081] The potential well layer of the active layer in the second embodiment, for example Figure 3As shown, the number of the first potential well layers 5w1 can be two, and the number of the second potential well layers 5w2 can be three. That is, the number of the second potential well layers 5w2 is larger than that of the first potential well layers 5w1. In addition, if the number of the second potential well layers 5w2 that contribute to light emission is larger than that of the first potential well layers 5w1, the numbers of the first potential well layers 5w1 and the second potential well layers 5w2 are not limited to these numbers. For example, the number of the first potential well layers 5w1 can be five, and the number of the second potential well layers 5w2 can be eight. By adopting such a layer structure, since the number of the second potential well layers 5w2 that contribute to light emission is large, more light emission can be generated by the second potential well layers 5w2.

[0082] In addition, in the present embodiment, a third barrier layer 5b3 and a fourth barrier layer 5b4 located closer to the p-side nitride semiconductor layer 20 than the third barrier layer 5b3 can be included between the first potential well layer 5w1 closest to the p-side nitride semiconductor layer 20 and the second potential well layer 5w2 closest to the n-side nitride semiconductor layer 10 (see Figure 3 ).

[0083] The third barrier layer 5b3 contains an n-type impurity. The n-type impurity concentration of the third barrier layer 5b3 can be set, for example, in the range of 1.0×10 17 ~1.0×10 19 / cm 3 , preferably in the range of 2.0×10 17 ~1.0×10 18 / cm 3 , and more preferably in the range of 3.0×10 17 ~8.0×10 17 / cm 3 . In the mode shown as an example in Figure 3 , the n-type impurity concentration of the third barrier layer 5b3 is 6.3×10 17 / cm 3 . In addition, the film thickness of the third barrier layer 5b3 can be set, for example, in the range of 5 to 30 nm, preferably in the range of 10 to 20 nm, and more preferably in the range of 13 to 16 nm. In the mode shown as an example in Figure 3 , the film thickness of the third barrier layer 5b3 is 15.75 nm.

[0084] The fourth barrier layer 5b4 contains an n-type impurity. The n-type impurity concentration of the fourth barrier layer 5b4 can be set, for example, in the range of 1.0×10 17 ~1.0×10 19 / cm 3 , preferably in the range of 2.0×10 17 ~1.0×10 18 / cm 3 , and more preferably in the range of 3.0×1017 ~8.0×10 17 / cm 3 in the range of. In the Figure 3 mode shown as an example, the n-type impurity concentration of the fourth barrier layer 5b4 is 6.3×10 17 / cm 3 . In addition, the film thickness of the fourth barrier layer 5b4 can be set, for example, in the range of 0.5 to 5.0 nm, preferably in the range of 0.5 to 1.5 nm, and more preferably in the range of 0.5 to 0.8 nm. In the Figure 3 mode shown as an example, the film thickness of the fourth barrier layer 5b4 is 0.6 nm.

[0085] In the present embodiment, the film thickness of the third barrier layer 5b3 can be thicker than that of the first barrier layer 5b1 located between the second well layers 5w2. In the Figure 3 mode shown as an example, the film thickness of the third barrier layer 5b3 is 15.8 nm, while the film thickness of the first barrier layer 5b1 located between the second well layers 5w2 is 9.5 nm. By making the film thickness of the third barrier layer 5b3 thicker than that of the first barrier layer 5b1 located between the second well layers 5w2, the crystallinity can be improved with respect to the third barrier layer 5b3 and the layers after the third barrier layer 5b3. In addition, the evaluation of crystallinity can be analyzed, for example, according to an X-ray diffraction spectrum (XRD). The layer to be measured shows a sharp diffraction peak when the crystallinity is high, and a broad diffraction peak when the crystallinity is low.

[0086] Furthermore, in the present embodiment, the n-type impurity concentration of the third barrier layer 5b3 is lower than that of the first barrier layer 5b1 located between the first well layers 5w1. By making the n-type impurity concentration of the third barrier layer 5b3 lower than that of the first barrier layer 5b1 located between the first well layers 5w1, the crystallinity can be improved with respect to the third barrier layer 5b3 and the layers after the third barrier layer 5b3. In the Figure 3 mode shown as an example, the n-type impurity concentration of the third barrier layer 5b3 is 6.3×10 17 / cm 3 , while the n-type impurity concentration of the first barrier layer 5b1 located between the first well layers 5w1 is 1.3×10 18 / cm 3 . In addition, in order to easily supply holes to the second well layer 5w2 that is conducive to light emission and the well layer near the center of the active layer, the second barrier layer 5b2 located between the first well layers 5w1 is preferably an undoped semiconductor layer.

[0087] Further, similar to the first embodiment, an undoped semiconductor layer 5u may be provided between the p-side nitride semiconductor layer 20 and the second quantum well layer 5w2 closest to the p-side nitride semiconductor layer 20.

[0088] - Method for manufacturing a nitride semiconductor light-emitting device -

[0089] As Figure 4 shown, the method for manufacturing a nitride semiconductor light-emitting device of the present disclosure includes an n-side nitride semiconductor layer formation step, an active layer formation step, a p-side nitride semiconductor layer formation step, and an electrode formation step. The n-side nitride semiconductor layer formation step includes a base layer formation step, an n-side contact layer formation step, and an n-side superlattice layer formation step. The p-side nitride semiconductor layer formation step includes a p-type barrier layer formation step and a p-side contact layer formation step. Hereinafter, the steps of the method for manufacturing a nitride semiconductor light-emitting device of the present disclosure will be described in order. Specifically, it will be described according to the method of manufacturing Figure 3 in the manner of.

[0090] (n-side nitride semiconductor layer formation step)

[0091] · Base layer formation step

[0092] First, for example, by metalorganic chemical vapor deposition (MOCVD), a base layer 2 is formed on the C-plane of a substrate 1 made of sapphire. A buffer layer may be formed on the substrate 1 before forming the base layer 2, and the base layer 2 may be formed via the buffer layer. Here, the buffer layer is formed, for example, by growing AlGaN on the substrate 1 by setting the growth temperature to 600 °C or lower and using TMA (trimethylaluminum), TMG (trimethylgallium), ammonia, etc. as raw material gases. In addition, the base layer 2 is formed, for example, by growing a GaN layer on the buffer layer using TMG and ammonia as raw material gases.

[0093] · n-side contact layer formation step

[0094] In the n-side contact layer formation step, an n-side contact layer 3 is formed by laminating a GaN layer doped with an n-type impurity. When growing a GaN layer doped with an n-type impurity, TMG and ammonia can be used as raw material gases, and silane can be used as an n-type impurity gas. The growth temperature of the n-side contact layer 3 can be set to 1150 °C, for example.

[0095] · n-side superlattice layer formation step

[0096] In the n-side superlattice layer forming process, the n-side superlattice layer 4 is formed by alternately laminating an undoped GaN layer and an undoped InGaN layer. The growth temperature of the n-side superlattice layer 4 is preferably lower than that of the n-side contact layer 3. For example, the growth temperature can be set to about 910 °C. When growing the undoped GaN layer, TEG (triethylgallium), ammonia, etc. can be used as source gases. In addition, when growing the undoped InGaN layer, TEG, TMI (trimethylindium), ammonia, etc. can be used as source gases. Furthermore, when growing the undoped GaN layer, a gas containing H2 can also be used as a carrier gas. By using such a gas as a carrier gas, the V-shaped pits on the surface of the GaN layer can be reduced. Here, the V-shaped pits refer to concave pits generated on the surface of the semiconductor layer due to dislocations formed in the semiconductor layer.

[0097] (Active layer forming process)

[0098] ·Barrier layer forming process

[0099] The barrier layer forming process includes a process of forming a first barrier layer containing an n-type impurity and a process of forming a second barrier layer located on the nitride semiconductor layer side closer to the p side than the first barrier layer.

[0100] In the process of forming the first barrier layer, the formation temperature is set to be 910 °C or higher and 1010 °C or lower to form a first barrier layer containing an n-type impurity. To make the first barrier layer contain an n-type impurity, silane can be used as the n-type impurity gas to form GaN containing an n-type impurity. To set the n-type impurity concentration of the first barrier layer 5b1 between the first potential well layers 5w1 to be 5.0×10 17 / cm 3 or higher and 2.0×10 18 / cm 3 or lower, the gas flow rate can be set to about 7 sccm, and the pressure in the chamber can be set to about 600 Torr. In addition, to set the n-type impurity concentration of the first barrier layer 5b1 between the second potential well layers 5w2 to be 4.0×10 17 / cm 3 or higher and 1.0×10 18 / cm 3 or lower, the gas flow rate can be set to about 5 sccm, and the pressure in the chamber can be set to about 600 Torr. That is, in the process of forming the first barrier layer, the barrier layer is formed such that the n-type impurity concentration of the first barrier layer 5b1 between the first potential well layers 5w1 is higher than that of the first barrier layer 5b1 between the second potential well layers 5w2.

[0101] The process of forming the second barrier layer sets the formation temperature to 780 °C or higher and 830 °C or lower, and forms a second barrier layer containing an n-type impurity. That is, compared with the process of forming the first barrier layer, the process of forming the second barrier layer reduces the formation temperature of the barrier layer. In addition, in the formation of the second barrier layer, the flow rate of the n-type impurity gas can be made smaller than that in the formation of the first barrier layer. Here, when forming the second barrier layer 5b2 between the first potential well layers 5w1, an undoped semiconductor layer can be formed. On the other hand, when forming the second barrier layer 5b2 between the second potential well layers 5w2, in order to contain an n-type impurity, silane can be used to form GaN containing an n-type impurity. In order to set the n-type impurity concentration of the second barrier layer 5b2 between the second potential well layers 5w2 to 3.0×10 17 / cm 3 or higher and 8.0×10 17 / cm 3 or lower, the gas flow rate can be set to about 1 sccm, and the pressure in the chamber can be set to about 600 Torr.

[0102] In this way, in the barrier layer formation process, regarding the relationship between the n-type impurity concentrations of the first barrier layer 5b1 and the second barrier layer 5b2, the barrier layer is formed such that the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the first potential well layers 5w1 is larger than the difference between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 between the second potential well layers 5w2.

[0103] In addition, as another method of setting the relationship between the n-type impurity concentrations of the first barrier layer 5b1 and the second barrier layer 5b2, the flow rate of the n-type impurity gas when forming the first barrier layer between the first potential well layers can be made larger than the flow rate of the n-type impurity gas when forming the first barrier layer between the second potential well layers.

[0104] In addition, by stacking a second barrier layer 5b2 formed at a lower temperature (780°C or higher and 830°C or lower) on a first barrier layer 5b1 formed at a higher temperature (910°C or higher and 1010°C or lower), and forming a quantum well layer thereon, it is possible to suppress deterioration of the crystallinity of the quantum well layer. The reason for this will be described. For the barrier layer to suppress deterioration of crystallinity, it needs to be formed at a higher temperature. On the other hand, in the formation of the quantum well layer, in order to suppress the dissociation of group III elements, it needs to be grown at a temperature lower than that of the barrier layer. After the barrier layer is formed, when the formation of the semiconductor layer is interrupted and the temperature is lowered to a temperature suitable for the formation of the quantum well layer, crystal defects may be generated due to the interruption of the formation of the semiconductor layer. Therefore, it is considered that after the barrier layer is formed at a higher temperature, the crystal defects generated due to the interruption of the formation of the semiconductor layer are buried by the barrier layer formed at a lower temperature, thereby suppressing deterioration of crystallinity. As a result, it is possible to suppress a decrease in luminous efficiency caused by deterioration of crystallinity. Furthermore, as described above, by doping the barrier layer with an n-type impurity, the energy level difference between the quantum well layer and the barrier layer can be reduced. Even in the formation of the barrier layer formed at a lower temperature, the energy level difference between the quantum well layer and the barrier layer can be further reduced by doping with an n-type impurity. In addition, by doping with an n-type impurity at a concentration lower than that of the barrier layer formed at a higher temperature, the energy level difference between the quantum well layer and the barrier layer can be reduced, and deterioration of crystallinity caused by doping with an n-type impurity can be suppressed.

[0105] In addition, as a process for manufacturing the barrier layer formation process of the second embodiment described above, it may include a process of forming a third barrier layer 5b3 between a first quantum well layer 5w1 closest to the p-side nitride semiconductor layer side and a second quantum well layer 5w2 closest to the n-side nitride semiconductor layer side, and a fourth barrier layer 5b4 on the p-side nitride semiconductor layer side of the third barrier layer 5b3.

[0106] In the process of forming the third barrier layer 5b3, the formation temperature is set to 910°C or higher and 1010°C or lower, and a third barrier layer 5b3 containing an n-type impurity is formed. In order to make the third barrier layer 5b3 contain an n-type impurity, silane can be used as the n-type impurity gas to form GaN containing an n-type impurity. In order to set the n-type impurity concentration of the third barrier layer 5b3 to 5.0×10 17 / cm 3 or higher and 2.0×10 18 / cm 3 or lower, and making its film thickness 13 nm or higher and 16 nm or lower, the gas flow rate can be set to about 3 sccm, and the pressure in the chamber can be set to about 600 Torr.

[0107] The process of forming the fourth barrier layer 5b4 sets the formation temperature to 780 °C or higher and 830 °C or lower, and forms the fourth barrier layer 5b4 containing n-type impurities. To make the fourth barrier layer 5b4 contain n-type impurities, silane can be used as the n-type impurity gas to form GaN containing n-type impurities. To set the n-type impurity concentration of the fourth barrier layer 5b4 to 5.0×10 17 / cm 3 or higher and 2.0×10 18 / cm 3 or lower, and to make its film thickness 0.5 nm or more and 0.8 nm or less, the gas flow rate can be set to about 1 sccm, and the pressure in the chamber can be set to about 600 Torr.

[0108] In this way, the film thickness of the third barrier layer 5b3 is formed to be thicker than that of the first barrier layer 5b1 located between the second well layers 5w2, and the n-type impurity concentration of the third barrier layer 5b3 is formed to be lower than that of the first barrier layer located between the first well layers 5w1. Thereby, the crystallinity can be improved with respect to the third barrier layer 5b3 and the layers after the third barrier layer 5b3.

[0109] In addition, as the barrier layer formation process, an undoped semiconductor layer 5u can be formed between the p-side nitride semiconductor layer and the second well layer 5w2 closest to the p-side nitride semiconductor layer. By forming the undoped semiconductor layer 5u, the diffusion of p-type impurities into the active layer 5 can be suppressed.

[0110] The process of forming the undoped semiconductor layer 5u is a process of forming an undoped semiconductor layer without supplying an n-type impurity gas with respect to the process of forming the first barrier layer 5b1 closest to the p side. The formation temperature, the gas flow rate other than the n-type impurity gas, and the pressure in the chamber can be set substantially the same as those in the process of forming the first barrier layer 5b1.

[0111] · Well layer formation process

[0112] The well layer formation process includes a process of forming a plurality of first well layers and a process of forming a plurality of second well layers located on the p-side nitride semiconductor layer side with respect to the plurality of first well layers 5w1.

[0113] Regarding the process of forming the first quantum well layer, raw material gases such as TEG (triethylgallium), TMI, and ammonia are used, and the temperature is set to 780 - 830 °C to form InGaN. Additionally, regarding the process of forming the second quantum well layer, raw material gases such as TEG, TMI, and ammonia are used, and the temperature is set to 780 - 830 °C to form InGaN. The number of the second quantum well layers 5w2 is formed to be larger than the number of the first quantum well layers 5w1. Thus, since the quantum well layers are formed in such a way that the number of the second quantum well layers 5w2 that are more conducive to light emission increases, more light emission can be generated from the second quantum well layers 5w2.

[0114] (p-side nitride semiconductor layer formation process)

[0115] ·p-type barrier layer formation process

[0116] In the p-type barrier layer formation process, for example, TEG, TMA, and ammonia are used as raw material gases, and Cp2Mg (bis(cyclopentadienyl)magnesium) is used as a p-type impurity gas to form an AlGaN layer containing p-type impurities as the p-type barrier layer 6.

[0117] ·p-side contact layer formation process

[0118] In the p-side contact layer formation process, for example, TMG, TMA, and ammonia are used as raw material gases to grow a layer composed of undoped GaN. Then, by using TMG, TMA, and ammonia as raw material gases and Cp2Mg (bis(cyclopentadienyl)magnesium) as a p-type impurity gas, a GaN layer containing p-type impurities is grown, thereby forming a p-side contact layer 7 on the layer composed of this undoped GaN. The impurity concentration of the p-side contact layer 7 is preferably higher than that of the p-type barrier layer 6.

[0119] After growing each semiconductor layer through the above processes, the wafer is annealed in a nitrogen atmosphere in a reaction furnace at a temperature of about 700 °C, for example.

[0120] (Electrode formation process)

[0121] After annealing, a part of the p-side nitride semiconductor layer 20, the active layer 5, and a part of the n-side nitride semiconductor layer 10 are removed to expose a part of the surface of the n-side contact layer 3.

[0122] After that, a p electrode 9 is formed on a part of the surface of the p-side contact layer 7, and an n electrode 8 is formed on a part of the exposed surface of the n-side contact layer 3. Through the above-described processes, a nitride semiconductor light-emitting element 100 is fabricated.

[0123] As described above, according to the method for manufacturing a nitride semiconductor light-emitting element of the present embodiment, a nitride semiconductor light-emitting element with improved luminous efficiency can be manufactured.

[0124]

Embodiment

[0125] A nitride semiconductor light-emitting element representing a preferred embodiment of the present disclosure will be described. As the substrate 1, a sapphire substrate is used. An undoped AlGaN layer, i.e., a buffer layer, is formed on the upper surface of the substrate 1. A base layer 2 is formed on top of the buffer layer.

[0126] An n-side contact layer 3 is formed on the upper surface of the base layer 2. The n-side contact layer 3 is a GaN layer doped with Si as an n-type impurity. The thickness of the n-side contact layer 3 is made about 8 μm.

[0127] An n-side superlattice layer 4 is formed on the upper surface of the n-side contact layer 3. First, a GaN layer doped with Si having a thickness of about 80 nm is formed. Then, 27 pairs of an undoped GaN layer having a thickness of about 3 nm and an undoped InGaN layer having a thickness of about 1.5 nm are formed. Then, 3 pairs of an undoped GaN layer having a thickness of about 3 nm and an InGaN layer doped with Si having a thickness of about 1.5 nm are formed. Finally, 6 pairs of an AlGaN layer doped with Si having a thickness of about 10 nm and an InGaN layer doped with Si having a thickness of about 1 nm are formed. By forming these semiconductor layers, an n-side superlattice layer 4 including a plurality of semiconductor layers is formed.

[0128] An active layer 5 is formed on the upper surface of the n-side superlattice layer 4.

[0129] First, an InGaN layer doped with Si having a thickness of about 6 nm, an undoped GaN layer having a thickness of about 2.3 nm as a barrier layer, an undoped GaN layer having a thickness of about 0.6 nm as a barrier layer, an undoped InGaN layer having a thickness of about 1.6 nm as a quantum well layer, and an undoped GaN layer having a thickness of about 1.6 nm as an intermediate layer are formed.

[0130] Then, a GaN layer doped with Si (n-type impurity concentration: 7.0×10 17 / cm 3 ) having a thickness of about 15.8 nm as a barrier layer, an undoped GaN layer having a thickness of about 0.6 nm as a barrier layer, an undoped InGaN layer having a thickness of about 1.6 nm as a first quantum well layer 5w1, and an undoped GaN layer having a thickness of about 1.6 nm as an intermediate layer 5c are formed.

[0131] Next, a Si-doped GaN layer with a thickness of about 15.8 nm is formed as the first barrier layer 5b1, an undoped GaN layer with a thickness of about 0.6 nm is formed as the second barrier layer 5b2, an undoped InGaN layer with a thickness of about 1.6 nm is formed as the first well layer 5w1, and an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer 5c. The processes of forming these first barrier layer 5b1, second barrier layer 5b2, first well layer 5w1, and intermediate layer 5c are repeated three times. In this process, the n-type impurity concentration of the first barrier layer 5b1 is set to 7.0×10 17 / cm 3 .

[0132] Next, a GaN layer doped with Si (n-type impurity concentration: 7.0×10 17 / cm 3 ) with a thickness of about 15.8 nm is formed as the barrier layer, a GaN layer doped with Si (n-type impurity concentration: 3.5×10 17 / cm 3 ) with a thickness of about 0.6 nm is formed as the barrier layer, an undoped InGaN layer with a thickness of about 3.0 nm is formed as the well layer, and an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer.

[0133] Next, a GaN layer doped with Si (n-type impurity concentration: 3.5×10 17 / cm 3 ) with a thickness of about 15.8 nm is formed as the third barrier layer 5b3, a GaN layer doped with Si (n-type impurity concentration: 3.5×10 17 / cm 3 ) with a thickness of about 0.6 nm is formed as the fourth barrier layer 5b4, an undoped InGaN layer with a thickness of about 3.0 nm is formed as the well layer, and an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer.

[0134] Next, a GaN layer doped with Si (n-type impurity concentration: 3.5×10 17 / cm 3 ) with a thickness of about 15.8 nm is formed as the third barrier layer 5b3, a GaN layer doped with Si (n-type impurity concentration: 3.5×10 17 / cm 3 ) with a thickness of about 0.6 nm is formed as the fourth barrier layer 5b4, an undoped InGaN layer with a thickness of about 3.0 nm is formed as the second well layer 5w2, and an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer 5c.

[0135] Next, a Si-doped GaN layer with a thickness of about 9.5 nm is formed as the first barrier layer 5b1, a Si-doped GaN layer with a thickness of about 0.6 nm is formed as the second barrier layer 5b2, an undoped InGaN layer with a thickness of about 3.0 nm is formed as the second quantum well layer 5w2, and an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer 5c. The processes of forming these first barrier layer 5b1, second barrier layer 5b2, second quantum well layer 5w2, and intermediate layer 5c are repeated 4 times. In this process, the n-type impurity concentration of the first barrier layer 5b1 is set to 4.9×10 17 / cm 3 , and the n-type impurity concentration of the second barrier layer 5b2 is set to 3.5×10 17 / cm 3 .

[0136] Finally, a GaN layer with a thickness of about 9.5 nm doped with Si (n-type impurity concentration: 4.9×10 17 / cm 3 ) is formed as the barrier layer, an undoped GaN layer with a thickness of about 0.6 nm is formed as the barrier layer, an undoped InGaN layer with a thickness of about 3.4 nm is formed as the quantum well layer, an undoped GaN layer with a thickness of about 1.6 nm is formed as the intermediate layer, and an undoped GaN layer with a thickness of about 18.4 nm is formed as the undoped semiconductor layer 5u. By forming the above semiconductor layers, the active layer 5 containing multiple semiconductor layers is formed.

[0137] In the formation of the active layer 5, the formation temperature of the barrier layer (including the first barrier layer 5b1) adjacent to the intermediate layer is set to 910 °C or higher and 1010 °C or lower, and the formation temperature of the barrier layer (including the second barrier layer 5b2) directly below the quantum well layer is set to 780 °C or higher and 830 °C or lower.

[0138] A p-type barrier layer 6 with a thickness of about 11 nm is formed on the upper surface of the active layer 5. The p-type barrier layer 6 is an AlGaN layer containing Mg as a p-type impurity. In this p-type barrier layer 6, the ratio of Al is set to about 12.5%.

[0139] A p-side contact layer 7 is formed on the upper surface of the p-type barrier layer 6. First, an undoped GaN with a thickness of about 80 nm is formed, and then a GaN doped with Mg with a thickness of about 20 nm is formed.

[0140] As described above, after each semiconductor layer is grown, the wafer is heat-treated in a reaction furnace at about 700 °C in a nitrogen atmosphere.

[0141] After the heat treatment, a part of the p-side nitride semiconductor layer 20, the active layer 5, and a part of the n-side nitride semiconductor layer 10 are removed to expose a part of the surface of the n-side contact layer 3.

[0142] Thereafter, a p electrode 9 is formed on a part of the surface of the p-side contact layer 7, and an n electrode 8 is formed on a part of the surface of the exposed n-side contact layer 3.

[0143] In this embodiment, the n-type impurity concentration (7.0×10 17 / cm 3 ) of the first barrier layer 5b1 located between the first well layers 5w1 is higher than that of the first barrier layer 5b1 (4.9×10 17 / cm 3 ) located between the second well layers 5w2.

[0144] In addition, in this embodiment, the difference (7.0×10 17 / cm 3 ) between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 in the barrier layer located between the first well layers 5w1 is larger than the difference (1.4×10 17 / cm 3 ) between the n-type impurity concentration of the first barrier layer 5b1 and the n-type impurity concentration of the second barrier layer 5b2 in the barrier layer located between the second well layers 5w2.

[0145] In addition, in this embodiment, the film thickness (about 15.8 nm) of the first barrier layer 5b1 located between the first well layers 5w1 is thicker than the film thickness (about 9.5 nm) of the first barrier layer 5b1 located between the second well layers 5w2.

[0146] In addition, in this embodiment, an undoped semiconductor layer 5u is provided between the p-side nitride semiconductor layer and the second well layer 5w2 closest to the p-side nitride semiconductor layer among the plurality of second well layers 5w2.

[0147] In addition, in this embodiment, at least one of the barrier layers between the first well layer 5w1 closest to the p-side nitride semiconductor layer side and the second well layer 5w2 closest to the n-side nitride semiconductor layer side among the plurality of barrier layers includes a third barrier layer 5b3 containing an n-type impurity and a fourth barrier layer 5b4 containing an n-type impurity and located closer to the p-side nitride semiconductor layer side than the third barrier layer 5b3.

[0148] Moreover, the film thickness (about 15.8 nm) of the third barrier layer 5b3 is thicker than the film thickness (about 9.5 nm) of the first barrier layer 5b1 of the barrier layer located between the second well layers 5w2, and the n-type impurity concentration (3.5×10 17 / cm 3 ) of the third barrier layer 5b3 is lower than the n-type impurity concentration (7.0×10 17 / cm 3 ) Low.

[0149] In addition, in this embodiment, the number of the second well layer 5w2 (five) is larger than the number of the first well layer 5w1 (four).

[0150] In addition, in this embodiment, the second barrier layer 5b2 located between the first well layers 5w1 is an undoped semiconductor layer.

[0151] In addition, in this embodiment, the n-type impurity is Si.

[0152] In the embodiment described above, the luminous efficiency of the nitride semiconductor light-emitting element when a current of 100 mA flows is 43.9%.

[0153] Furthermore, the embodiments disclosed this time are examples in all aspects and are not used as a basis for restrictive interpretation. Therefore, the technical scope of the present invention is not defined only by the above-described embodiments, but is delimited based on the description in the claims. In addition, the technical scope of the present invention includes all changes within the meaning and scope equivalent to the claims.

[0154] Description of Reference Numerals

[0155] 1 Substrate

[0156] 2 Base layer

[0157] 3 n-side contact layer

[0158] 4 n-side superlattice layer

[0159] 5 Active layer

[0160] 5c Intermediate layer

[0161] 5u Undoped semiconductor layer

[0162] 5b1 First barrier layer

[0163] 5b2 Second barrier layer

[0164] 5b3 Third barrier layer

[0165] 5b4 Fourth barrier layer

[0166] 5bw Stacked portion

[0167] 5w1 First well layer

[0168] 5w2 Second well layer

[0169] 6 p-type barrier layer

[0170] 7 p-side contact layer

[0171] 8 n-electrode

[0172] 9 p-electrode

[0173] 10 n-side nitride semiconductor layer

[0174] 20 p-side nitride semiconductor layer

[0175] 100 nitride semiconductor light-emitting device

Claims

1. A nitride semiconductor light-emitting device, comprising an n-side nitride semiconductor layer, a p-side nitride semiconductor layer, and an active layer disposed between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer, wherein, the active layer has a plurality of stacked portions including well layers and barrier layers, the well layers include a plurality of first well layers and a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers, at least one of the barrier layers located between the first well layers among the plurality of barrier layers and at least one of the barrier layers located between the second well layers among the plurality of barrier layers include a first barrier layer containing an n-type impurity and a second barrier layer containing an n-type impurity having a lower n-type impurity concentration than the first barrier layer and located closer to the p-side nitride semiconductor layer than the first barrier layer, the n-type impurity concentration of the first barrier layer located between the first well layers is higher than the n-type impurity concentration of the first barrier layer located between the second well layers, the difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer in the barrier layers located between the first well layers among the plurality of barrier layers is larger than the difference between the n-type impurity concentration of the first barrier layer and the n-type impurity concentration of the second barrier layer in the barrier layers located between the second well layers among the plurality of barrier layers, the second barrier layer located between the second well layers contains an n-type impurity, and the concentration of the n-type impurity in the second barrier layer located between the first well layers is lower than the concentration of the n-type impurity in the second barrier layer located between the second well layers.

2. The nitride semiconductor light-emitting device according to claim 1, wherein, the film thickness of the first barrier layer located between the first well layers is thicker than the film thickness of the first barrier layer located between the second well layers.

3. The nitride semiconductor light-emitting device according to claim 1, wherein, an undoped semiconductor layer is provided between the p-side nitride semiconductor layer and the second well layer closest to the p-side nitride semiconductor layer among the plurality of second well layers.

4. The nitride semiconductor light-emitting device according to claim 1, wherein, at least one barrier layer located between the first well layer closest to the p-side nitride semiconductor layer side and the second well layer closest to the n-side nitride semiconductor layer side among the plurality of barrier layers includes a third barrier layer containing an n-type impurity and a fourth barrier layer containing an n-type impurity and located closer to the p-side nitride semiconductor layer than the third barrier layer, the film thickness of the third barrier layer is thicker than the film thickness of the first barrier layer in the barrier layers located between the second well layers among the plurality of barrier layers, the n-type impurity concentration of the third barrier layer is lower than the n-type impurity concentration of the first barrier layer in the barrier layers located between the first well layers among the plurality of barrier layers.

5. The nitride semiconductor light-emitting device according to claim 1, wherein, the number of the second well layers is larger than the number of the first well layers.

6. The nitride semiconductor light-emitting element according to claim 1, wherein the second barrier layer located between the first well layers is an undoped semiconductor layer.

7. The nitride semiconductor light-emitting element according to claim 1, wherein the n-type impurity is Si.

8. A method for manufacturing a nitride semiconductor light-emitting element, comprising: a step of forming an n-side nitride semiconductor layer; a step of forming an active layer having a plurality of stacked portions including well layers and barrier layers after the step of forming the n-side nitride semiconductor layer; a step of forming a p-side nitride semiconductor layer after the step of forming the active layer; the step of forming the active layer includes a step of forming a plurality of the barrier layers and a step of forming a plurality of the well layers, the step of forming a plurality of the barrier layers each has a step of forming a first barrier layer containing an n-type impurity and a step of forming a second barrier layer containing an n-type impurity having a lower n-type impurity concentration than the first barrier layer and located closer to the p-side nitride semiconductor layer than the first barrier layer, the step of forming a plurality of the well layers has a step of forming a plurality of first well layers and a step of forming a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers, in the step of forming a plurality of the barrier layers, the n-type impurity concentration of the first barrier layer located between the first well layers is formed to be higher than the n-type impurity concentration of the first barrier layer located between the second well layers, the difference between the n-type impurity concentration of the first barrier layer located between the first well layers and the n-type impurity concentration of the second barrier layer is formed to be larger than the difference between the n-type impurity concentration of the first barrier layer located between the second well layers and the n-type impurity concentration of the second barrier layer, the second barrier layer located between the second well layers contains an n-type impurity, and the concentration of the n-type impurity in the second barrier layer located between the first well layers is lower than the concentration of the n-type impurity in the second barrier layer located between the second well layers.

9. The method for manufacturing a nitride semiconductor light-emitting element according to claim 8, wherein in the step of forming the barrier layer, the film thickness of the first barrier layer located between the first well layers is formed to be thicker than the film thickness of the first barrier layer located between the second well layers.

10. The method for manufacturing a nitride semiconductor light-emitting element according to claim 8, wherein the step of forming the active layer further has a step of forming an undoped semiconductor layer between the p-side nitride semiconductor layer and the second well layer closest to the p-side nitride semiconductor layer among the plurality of second well layers.

11. The method for manufacturing a nitride semiconductor light-emitting element according to claim 8, wherein The step of forming the active layer further includes a step of forming a third barrier layer containing an n-type impurity and a fourth barrier layer containing an n-type impurity and located closer to the p-side nitride semiconductor layer than the third barrier layer between the first well layer closest to the p-side nitride semiconductor layer side and the second well layer closest to the n-side nitride semiconductor layer side. The film thickness of the third barrier layer is thicker than that of the first barrier layer among the barrier layers located between the second well layers in the plurality of barrier layers. The n-type impurity concentration of the third barrier layer is lower than that of the first barrier layer among the barrier layers located between the first well layers in the plurality of barrier layers.

12. The method of manufacturing a nitride semiconductor light-emitting device according to claim 8, wherein In the step of forming the well layer, the number of the second well layers is formed to be larger than the number of the first well layers.

13. The method of manufacturing a nitride semiconductor light-emitting device according to claim 8, wherein In the step of forming the barrier layer, an undoped semiconductor layer is formed as the second barrier layer located between the first well layers.

14. The method of manufacturing a nitride semiconductor light-emitting device according to claim 8, wherein In the step of forming the active layer, Si is doped as the n-type impurity.

15. The method of manufacturing a nitride semiconductor light-emitting device according to claim 8, wherein In the step of forming the barrier layer, the formation temperature of the first barrier layer is formed to be higher than that of the second barrier layer.

16. The method of manufacturing a nitride semiconductor light-emitting device according to claim 15, wherein The formation temperature of the first barrier layer is 910 °C or higher and 1010 °C or lower. The formation temperature of the second barrier layer is 780 °C or higher and 830 °C or lower.

17. A method of manufacturing a nitride semiconductor light-emitting device, comprising: A step of forming an n-side nitride semiconductor layer; A step of forming an active layer having a plurality of stacked portions including well layers and barrier layers after the step of forming the n-side nitride semiconductor layer; A step of forming a p-side nitride semiconductor layer after the step of forming the active layer, The step of forming the active layer includes a step of forming a plurality of the barrier layers and a step of forming a plurality of the well layers, The steps of forming a plurality of the barrier layers each have a step of forming a first barrier layer while supplying an n-type impurity gas and a step of forming a second barrier layer located closer to the p-side nitride semiconductor layer than the first barrier layer while supplying the n-type impurity gas at a flow rate smaller than that in the formation of the first barrier layer, The steps of forming a plurality of the well layers have a step of forming a plurality of first well layers and a step of forming a plurality of second well layers located closer to the p-side nitride semiconductor layer than the plurality of first well layers. In the process of forming the multiple barrier layers, the flow rate of the n-type impurity gas when forming the first barrier layer between the first well layers is made larger than the flow rate of the n-type impurity gas when forming the first barrier layer between the second well layers. The second barrier layer between the second well layers contains n-type impurities, and the concentration of the n-type impurities in the second barrier layer between the first well layers is lower than the concentration of the n-type impurities in the second barrier layer between the second well layers.

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