Memory Structure and Method for Manufacturing the Same

Abstract

The present application provides a memory structure and a manufacturing method thereof. The memory structure includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode. The present application can increase the number of conductive filaments, thereby improving data retention, without the need to increase the thickness of the resistive switching layer.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and more particularly to a memory structure and a method for manufacturing the same. Background Art

[0002] As the size of semiconductor devices is scaled down, the difficulty of manufacturing semiconductor devices has increased significantly. Unwanted defects may occur during the manufacturing process of semiconductor devices, and these defects may cause a reduction in device performance or damage. Therefore, semiconductor devices must be continuously improved to increase the yield rate and improve the process margin. Summary of the Invention

[0003] According to some embodiments of the present invention, a memory structure is provided. The memory structure includes a substrate; an electrical channel layer disposed on the substrate; a first electrode disposed on the substrate and extending into the electrical channel layer; a resistive switching layer disposed between the first electrode and the electrical channel layer; a second electrode disposed on the electrical channel layer; and a conductive structure connecting the electrical channel layer and the second electrode.

[0004] According to some embodiments of the present invention, a memory structure is provided. The memory structure includes a substrate; an electrical channel layer disposed on the substrate and extending along a first direction; a first electrode disposed on the substrate and extending into the electrical channel layer along a second direction different from the first direction; a resistive switching layer disposed between the first electrode and the electrical channel layer; a second electrode disposed on the electrical channel layer, wherein the substrate, the electrical channel layer, and the second electrode are stacked along the second direction; and a conductive structure connecting the electrical channel layer and the second electrode and extending along the second direction.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a memory structure is provided. The method includes forming an electrical channel layer on a substrate; forming a first electrode on the substrate and extending into the electrical channel layer; forming a resistive switching layer between the first electrode and the electrical channel layer; and forming a conductive structure on the electrical channel layer and connecting it to a second electrode. Brief Description of the Drawings

[0006] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0007] Figure 1 is a cross-sectional schematic diagram of a memory structure according to some embodiments.

[0008] Figures 2A to 2E is a cross-sectional schematic diagram showing various stages in the manufacture of a memory structure according to some embodiments.

[0009] Figure 3 is a cross-sectional schematic diagram showing a memory structure according to some embodiments.

[0010] Figure 4 is a top view schematic diagram showing a memory structure according to some embodiments.

[0011]

Description of Symbols

[0012] 100, 200: Memory structure;

[0013] 102, 110, 204: Contact;

[0014] 104, 212: First electrode;

[0015] 106, 210: Resistive switching layer;

[0016] 108, 222: Second electrode;

[0017] 202: Substrate;

[0018] 205: Dielectric layer;

[0019] 206: High-k dielectric layer;

[0020] 208: Electrical channel layer;

[0021] 209: Trench;

[0022] 214A, 214B: Via;

[0023] 216A, 216B, 220: Barrier layer;

[0024] 218A, 218B: Conductive structure;

[0025] 224: Current;

[0026] 226: Conductive filament;

[0027] D1: First direction;

[0028] D2: Second direction;

[0029] D3: Third direction. Detailed Embodiments

[0030] The following outlines some embodiments to make it easier for those skilled in the art to understand the present invention. However, these embodiments are merely examples and are not intended to limit the present invention. It is understood that those skilled in the art can adjust the embodiments described below according to requirements, such as changing the process sequence and / or including more or fewer steps than those described herein, and such adjustments are within the scope of the present invention.

[0031] In addition, other elements may be added based on the embodiments described below. For example, the description of "forming a second element on a first element" may include embodiments where the first element and the second element are in direct contact, or may include embodiments where there are other elements between the first element and the second element such that the first element and the second element are not in direct contact, and the vertical relationship between the first element and the second element may change as the device operates or is used in different orientations.

[0032] In the following description, the description of "a first element passing through a second element" may include the first element being within the second element and extending from a first side of the second element to an opposite second side, where a surface of the first element may be flush with a surface of the second element, or a surface of the first element may also be outside a surface of the second element. Additionally, the present invention may repeat reference numerals and / or letters in different embodiments, and this repetition is for simplicity and clarity and not to indicate a relationship between the different embodiments being discussed.

[0033] According to some embodiments of the present invention, a memory structure and a method for manufacturing the same are described, and are particularly applicable to non-volatile memory (NVM), such as resistive random-access memory (RRAM). The present invention arranges a resistive switching layer to extend into an electrical channel layer, which can increase the number of filaments without increasing the forming voltage and improve data retention.

[0034] Figure 1 is a cross-sectional schematic diagram of a memory structure 100 shown according to some embodiments. As Figure 1 shown, the memory structure 100 includes contacts 102 and 110, which are respectively connected to a first electrode 104 and a second electrode 108, and the memory structure 100 includes a resistive switching layer 106 disposed between the first electrode 104 and the second electrode 108.

[0035] When a positive voltage is applied to the memory device 100, oxygen ions in the resistive switching layer 106 migrate to the electrode above it and form oxygen vacancy filaments (not shown) in the resistive switching layer 106, causing the resistive switching layer 106 to be converted to a low-resistance state. Conversely, when a reverse voltage is applied to the memory device 100, the oxygen ions return to the resistive switching layer 106 and combine with the oxygen vacancies in the resistive switching layer 106, resulting in the disappearance of the oxygen vacancy filaments and causing the resistive switching layer 106 to be converted to a high-resistance state. The memory device 100 stores or reads data by converting the resistance value in the above manner to achieve the storage function.

[0036] In some embodiments, the high temperature used in the manufacturing process of the memory structure reduces the current in the low resistance state, deteriorating data retention. Since the conductive filament current is related to the oxygen vacancy concentration, some methods provide more oxygen vacancies by increasing the thickness of the resistive switching layer 106 to increase the current in the low resistance state, thereby improving data retention. However, such methods also introduce some problems. For example, since the material of the resistive switching layer 106 is less easy to etch, increasing the thickness of the resistive switching layer 106 also increases the difficulty of the etching process, such as making it difficult to form the desired shape of the resistive switching layer 106. In addition, increasing the thickness of the resistive switching layer 106 also increases the formation voltage of the memory structure 100, which is not conducive to the mass production of the memory structure 100. Therefore, the present invention further provides the following embodiments to improve the above problems.

[0037] Figures 2A to 2E is a cross-sectional schematic view of a memory structure 200 shown according to some other embodiments. As Figure 2A shown, the memory structure 200 includes a substrate 202. The substrate 202 can use any substrate material suitable for the memory structure 200. For example, the substrate 202 can include an oxide.

[0038] In some embodiments, the memory structure 200 includes a contact 204 disposed in the substrate 202. The contact 204 can include a conductive material, such as doped or undoped polysilicon, metal, similar materials, or a combination of the foregoing. For example, the metal includes gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, tantalum, hafnium, similar materials, alloys of the foregoing, multi-layer structures of the foregoing, or a combination of the foregoing. According to some embodiments, the deposition process includes a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, an evaporation process, an electroplating process, similar processes, or a combination of the foregoing.

[0039] Then, according to some embodiments, a dielectric layer 205 is formed on the contact 204 to cover the contact 204. In some embodiments, the dielectric layer 205 and the substrate 202 include the same material, so the interface between the dielectric layer 205 and the substrate 202 is not shown. In other embodiments, the dielectric layer 205 and the substrate 202 include different materials, and there will be an interface between the dielectric layer 205 and the substrate 202. The formation method of the dielectric layer 205 can include chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing.

[0040] Then, according to some embodiments, a pair of high-k layers 206 and an electrical channel layer 208 between the high-k layers 206 are formed on the dielectric layer 205. The high-k layers 206 and the electrical channel layer 208 may extend along a first direction D1. The high-k layer 206 may comprise a material having a dielectric constant greater than 3.9, such as tantalum oxide, hafnium oxide, aluminum oxide, similar materials, or a combination of the foregoing. The electrical channel layer 208 may comprise titanium, titanium nitride, tantalum, tantalum nitride, hafnium, hafnium nitride, similar materials, or a combination of the foregoing. The method of forming the high-k layer 206 and the electrical channel layer 208 may be similar to the method of forming the dielectric layer 205, and thus will not be described in detail.

[0041] The number of the electrical channel layers 208 is related to the number of currents. Two electrical channel layers 208 are illustrated herein, but the present invention is not limited thereto. More or fewer electrical channel layers 208 may be used according to the number of currents, and dielectric layers 205 are disposed between these electrical channel layers 208. Then, a dielectric layer 205 is deposited on the uppermost electrical channel layer 208.

[0042] Then, according to some embodiments, trenches 209 are etched in the memory structure 200. As Figure 2A shown, the trenches 209 pass through the dielectric layer 205, the high-k layers 206, and the electrical channel layer 208 and expose the contacts 204. The trenches 209 may extend along a second direction D2, and the second direction D2 is different from the first direction D1. The first direction D1 and the second direction D2 may be substantially perpendicular or orthogonal to each other. Alternatively, the angle between the first direction D1 and the second direction D2 may be about 80 degrees to about 90 degrees.

[0043] In some embodiments, the formation of the trenches 209 may be performed by disposing a mask layer (not shown) on the dielectric layer 205, and then using the mask layer as an etching mask to perform an etching process. In some embodiments, the mask layer may comprise a hard mask and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or a combination of the foregoing. The mask layer may be a single-layer structure or a multi-layer structure. The formation of the mask layer 104 may comprise a deposition process, a photolithography process, other suitable processes, or a combination of the foregoing. In some embodiments, the deposition process comprises spin coating, chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing. In some embodiments, the photolithography process may comprise photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, development, rinsing, drying (e.g., hard baking), other suitable processes, or a combination of the foregoing.

[0044] In some embodiments, the etching process of the trench 209 may include a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process may include reactive ion etch (RIE), inductively-coupled plasma (ICP) etching, neutral beam etch (NBE), electron cyclotron resonance (ECR) etching, similar etching processes, or a combination of the foregoing. For example, the wet etching process may use, for example, hydrofluoric acid, ammonium hydroxide, or any suitable etchant.

[0045] Then, according to some embodiments, as Figure 2B shown, a resistive switching layer 210 is formed on the sidewall of the trench 209. The resistive switching layer 210 may extend substantially along the second direction D2. In some embodiments, the material of the resistive switching layer 210 may include transition metal oxides, such as nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, aluminum oxide, tantalum oxide, molybdenum oxide, copper oxide, similar materials, or a combination of the foregoing. The forming method of the resistive switching layer 210 may include atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process, similar deposition processes, or a combination of the foregoing.

[0046] Then, according to some embodiments, a first electrode 212 is formed in the remaining portion of the trench 209. The first electrode 212 may extend substantially along the second direction D2. The material of the first electrode 212 may include a metal or a metal nitride, such as platinum, titanium nitride, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, copper, similar materials, or a combination of the foregoing. In some embodiments, the material of the first electrode 212 includes copper. The forming method of the first electrode 212 may include atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process, similar deposition processes, or a combination of the foregoing.

[0047] As Figure 2B shown, the resistive switching layer 210 is adjacent to the first electrode 212, the resistive switching layer 210 is located on the sidewall of the first electrode 212 and exposes the top surface of the first electrode 212. In some embodiments, the resistive switching layer 210 and the first electrode 212 extend through the electrical channel layer 208 towards the substrate 202 and contact the contact 204. According to some embodiments, as Figure 2B shown, the resistive switching layer 210 and the first electrode 212 are substantially perpendicular to the top surface of the substrate 202, but the present invention is not limited thereto, and the resistive switching layer 210 and the first electrode 212 may have any suitable angle with the top surface of the substrate 202. Then, a planarization process, such as chemical mechanical polishing process, may be performed to remove the excess material and provide a flat surface.

[0048] Although in Figure 2B the embodiment, the first electrode 212 passes through the electrical channel layer 208, that is, the top surface of the first electrode 212 is above the electrical channel layer 208, and the bottom surface of the first electrode 212 is below the electrical channel layer 208, but the present invention is not limited thereto. For example, the first electrode 212 may partially extend into the electrical channel layer 208 such that the top surface of the first electrode 212 is in the electrical channel layer 208.

[0049] Then, according to some embodiments, such as Figure 2C shown, a dielectric layer 205 is formed on the first electrode 212 to cover the first electrode 212 and the resistive switching layer 210. Then, vias 214A and 214B are etched in the memory structure 200. The vias 214A and 214B pass through the dielectric layer 205, the high-k layer 206, and the electrical channel layer 208 and are located on both sides of the first electrode 212. The method of forming the vias 214A and 214B may be similar to the method of forming the trench 209, so it will not be described in detail.

[0050] Although in Figure 2C the embodiment, the vias 214A and 214B pass through the electrical channel layer 208, and the bottom surfaces of the vias 214A and 214B are below the electrical channel layer 208, but the present invention is not limited thereto. For example, the vias 214A and 214B may partially extend into the electrical channel layer 208 such that the bottom surfaces of the vias 214A and 214B are in the electrical channel layer 208. Alternatively, according to some other embodiments, the vias 214A and 214B may not extend into the electrical channel layer 208, and the bottom surfaces of the vias 214A and 214B are flush with the top surface of the electrical channel layer 208. In addition, the vias 214A and 214B may each have different depths, and the number of vias may be more or less than two.

[0051] Then, according to some embodiments, such as Figure 2DAs shown, barrier layers 216A and 216B are respectively formed on the sidewalls of vias 214A and 214B, and conductive structures 218A and 218B are respectively formed on the remaining portions of vias 214A and 214B. The conductive structures 218A and 218B can extend substantially along the second direction D2. In some embodiments, the barrier layers 216A and 216B are respectively located between the conductive structures 218A and 218B and the electrical channel layer 208. The materials of the barrier layers 216A and 216B can include alumina, and the formation methods of the barrier layers 216A and 216B can include atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process, similar deposition processes or combinations of the foregoing. The conductive structures 218A and 218B can include conductive materials, such as metals or metal nitrides. In some embodiments, the materials of the conductive structures 218A and 218B include copper.

[0052] As Figure 2E shown, the conductive structures 218A and 218B extend to the electrical channel layer 208, and the resistive switching layer 210 is located between the first electrode 212 and the conductive structures 218A and 218B. In some embodiments, the top surfaces of the conductive structures 218A and 218B are higher than the top surface of the first electrode 212. According to some embodiments, as Figure 2D shown, the conductive structures 218A and 218B are substantially perpendicular to the top surface of the substrate 202, but the present invention is not limited thereto, and the conductive structures 218A and 218B can have any suitable angle with respect to the top surface of the substrate 202. Then, a planarization process, such as chemical mechanical polishing process, can be performed to remove the excess material and provide a flat surface.

[0053] The depth of the conductive structures 218A and 218B depends on the depth of the vias 214A and 214B. Therefore, as previously discussed regarding the vias 214A and 218B, the conductive structures 218A and 218B can pass through or not pass through the electrical channel layer 208. Specifically, the bottom surfaces of the conductive structures 218A and 218B can be flush with the top surface of the electrical channel layer 208, or the bottom surfaces of the conductive structures 218A and 218B can be within or below the electrical channel layer 208.

[0054] Then, according to some embodiments, as Figure 2EAs shown, a barrier layer 220 and a second electrode 222 are formed on the electrical channel layer 208. The substrate 202, the electrical channel layer 208, and the second electrode 222 can be stacked substantially in a second direction D2. The material of the barrier layer 220 can include titanium, titanium nitride, tungsten nitride, tantalum, tantalum nitride, similar materials, or a combination of the foregoing. The material of the second electrode 222 can include a conductive material, such as a metal or a metal nitride. The methods of forming the barrier layer 220 and the second electrode 222 can each independently include an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, similar deposition processes, or a combination of the foregoing.

[0055] As Figure 2E shown, the second electrode 222 covers the conductive structures 218A and 218B and is electrically connected to the conductive structures 218A and 218B, enabling the current 224 to flow from the first electrode 212 through the electrical channel layer 208, the conductive structures 218A and 218B to the second electrode 222. Although in Figure 2E the second electrode 222 is electrically connected to both the conductive structures 218A and 218B simultaneously, two second electrodes 222 can also be provided to be electrically connected to the conductive structures 218A and 218B respectively.

[0056] Please refer to Figure 3 to describe the formation of the conductive filament 226 to form a path for the current 224. Figure 3 is a cross-sectional schematic diagram of the memory structure 200 illustrated according to some embodiments. For ease of illustration, in Figure 3 only the first electrode 212, the resistive switching layer 210, and the electrical channel layer 208 are illustrated, and not all components in Figure 2E are shown.

[0057] As Figure 3 shown, the resistive switching layer 210 is located between the first electrode 212 and the electrical channel layer 208. When a positive voltage is applied to the memory structure 200, the resistive switching layer 210 forms conductive filaments 226 on both sides adjacent to the electrical channel layer 208 respectively, and four conductive filaments 226 can be generated in the two electrical channel layers 208. These conductive filaments 226 connect the first electrode 212 and the electrical channel layer 208 and form a path for the current 224 as Figure 2E shown. Therefore, in the embodiments of the present invention, by providing the resistive switching layer 210 extending into the electrical channel layer 208, the number of conductive filaments can be increased without increasing the thickness of the resistive switching layer 210, thereby improving data retention.

[0058] Refer to Figure 2E, the memory structure 200 includes conductive structures 218A and 218B and two layers of electrical channel layers 208. Since the number of electrical channel layers 208, conductive structures 218A and 218B is related to the number of currents 224, the memory structure 200 can generate currents 224 as shown by the four arrows. The number of conductive structures and electrical channel layers can be adjusted according to requirements. For example, the conductive structure 218A can be disposed only on one side of the first electrode 212, and more layers of electrical channel layers 208 can be provided, so that multiple currents can be achieved on a smaller area.

[0059] Figure 4 is a top view schematic diagram of the memory structure 200 according to some embodiments. As Figure 4 shown, in the first direction D1, the conductive structures 218A and 218B are disposed on both sides of the first electrode 212. Two memory structures 200 can be disposed along the third direction D3, but one or more memory structures 200 can also be provided. The third direction D3 is different from the first direction D1. The first direction D1 and the third direction D3 can be substantially perpendicular or orthogonal to each other. Alternatively, the angle between the first direction D1 and the third direction D3 can be about 80 degrees to about 90 degrees.

[0060] In the top view, the first electrode 212, conductive structures 218A and 218B are circular, but they can also be, for example, oval or other shapes. The barrier layers 216A and 216B can be respectively disposed on the sidewalls of the conductive structures 218A and 218B and surround the conductive structures 218A and 218B. The resistive switching layer 210 can be disposed on the sidewall of the first electrode 210 and surround the first electrode 210. By surrounding the first electrode 210 with the resistive switching layer 210, embodiments of the present invention can form multiple memory cells with the same layer of resistive switching layer 210, without the need to separately form multiple resistive switching layers 210 for multiple memory cells, so that the cost can be reduced and the volume of the memory structure 200 can be reduced.

[0061] In some embodiments, the area of the top surface of the second electrode 222 can be larger than the area of the top surface of the electrical channel layer 208. The edges of the resistive switching layer 210, barrier layers 216A and 216B can be located outside the two sidewalls of the electrical channel layer 208 and inside the two sidewalls of the second electrode 222. In addition, multiple memory structures 200 can be disposed in parallel, and these memory structures 200 can respectively include different numbers of components, such as different numbers of electrical channel layers 208 or conductive structures 218A, 218B. Therefore, embodiments of the present invention can have good design flexibility.

[0062] In summary, the memory structure provided by the present invention can increase the number of conductive filaments by setting the resistive switching layer to extend into the electrical channel layer, thereby improving data retention, without the need to increase the thickness of the resistive switching layer. Therefore, problems associated with increasing the thickness, such as increasing the difficulty of the etching process and increasing the formation voltage of the memory structure, can be avoided.

[0063] In addition, in some embodiments, the number of electrical channel layers and / or conductive structures can be adjusted to generate the desired number of conductive filaments, thus having good design flexibility. Additionally, according to some embodiments, by increasing the number of electrical channel layers, multiple memory cells can be formed without increasing the resistive switching layer, thereby reducing costs and shrinking the volume.

[0064] Although the embodiments of the present invention have been described above with multiple embodiments, these embodiments are not intended to limit the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same objectives and / or advantages as those described in the multiple embodiments herein. Those skilled in the art to which the present invention pertains should also understand that such modifications or designs do not depart from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A memory structure, characterized in that, it comprises: a substrate; an electrical channel layer disposed on the substrate; a first electrode disposed on the substrate and extending into the electrical channel layer; a resistive switching layer disposed between the first electrode and the electrical channel layer; a second electrode disposed on the electrical channel layer; and a conductive structure connecting the electrical channel layer and the second electrode, wherein, in a top view of the memory structure, an extending direction of the electrical channel layer and an extending direction of the second electrode are parallel to each other, and a positive projection of the second electrode on the substrate completely covers a positive projection of the electrical channel layer on the substrate.

2. The memory structure according to claim 1, characterized in that, it further comprises a plurality of conductive structures connecting the electrical channel layer and the second electrode, wherein the conductive structures are disposed on both sides of the first electrode.

3. The memory structure according to claim 1, characterized in that, it further comprises a plurality of electrical channel layers disposed between the substrate and the second electrode, and the first electrode passes through the electrical channel layers.

4. The memory structure according to claim 1, characterized in that, wherein the resistive switching layer is disposed on a sidewall of the first electrode.

5. The memory structure according to claim 1, characterized in that, it further comprises a dielectric layer disposed between the first electrode and the second electrode, wherein the conductive structure passes through the dielectric layer.

6. A memory structure, characterized in that, it comprises: a substrate; an electrical channel layer disposed on the substrate and extending along a first direction; a first electrode disposed on the substrate and extending into the electrical channel layer along a second direction, the second direction being different from the first direction; a resistive switching layer disposed between the first electrode and the electrical channel layer; a second electrode disposed on the electrical channel layer, wherein the substrate, the electrical channel layer and the second electrode are stacked along the second direction; and a conductive structure connecting the electrical channel layer and the second electrode and extending along the second direction, wherein, in a top view of the memory structure, an extending direction of the electrical channel layer and an extending direction of the second electrode are parallel to each other, and a positive projection of the second electrode on the substrate completely covers a positive projection of the electrical channel layer on the substrate.

7. A method for manufacturing a memory structure, characterized in that, it comprises: forming an electrical channel layer on a substrate; forming a first electrode on the substrate and extending into the electrical channel layer; forming a resistive switching layer between the first electrode and the electrical channel layer; and forming a conductive structure on the electrical channel layer and connecting it to a second electrode, wherein, in a top view of the memory structure, an extending direction of the electrical channel layer and an extending direction of the second electrode are parallel to each other, and a positive projection of the second electrode on the substrate completely covers a positive projection of the electrical channel layer on the substrate.

8. The method for manufacturing a memory structure according to claim 7, It is characterized in that forming the first electrode and the resistive switching layer includes: forming a trench in the electrical channel layer; forming the resistive switching layer on the sidewall of the trench; and forming the first electrode in the remaining part of the trench.

9. The method for manufacturing a memory structure according to claim 8, it is characterized in that the trench exposes a contact in the substrate.

10. The method for manufacturing a memory structure according to claim 7, it is characterized in that forming the conductive structure includes: forming a via hole extending to the electrical channel layer; forming a barrier layer on the sidewall of the via hole; and forming the conductive structure in the remaining part of the via hole.

11. The method for manufacturing a memory structure according to claim 7, it is characterized in that further comprising: forming a plurality of conductive structures on both sides of the first electrode and extending to the electrical channel layer; and forming the second electrode on the electrical channel layer, wherein the second electrode is electrically connected to the conductive structure.

12. The method for manufacturing a memory structure according to claim 7, it is characterized in that further comprising forming a plurality of electrical channel layers on the substrate, wherein the first electrode extends into the electrical channel layers.

13. The method for manufacturing a memory structure according to claim 7, it is characterized in that further comprising forming a dielectric layer covering the first electrode before forming the conductive structure, wherein forming the conductive structure includes passing through the dielectric layer.

14. The method for manufacturing a memory structure according to claim 7, it is characterized in that the resistive switching layer surrounds the first electrode and exposes the top surface of the first electrode.

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