Flexible multi-gate electrode synaptic transistor and preparation method and application thereof

Abstract

This invention discloses a flexible multi-gate electrode synaptic transistor, its fabrication method, and its applications, belonging to the fields of semiconductor devices and neuromorphic computing. The flexible multi-gate electrode synaptic transistor of this invention includes an insulating substrate, a channel layer, an electrolyte, a source electrode, a drain electrode, gate electrode I, and gate electrode II. The channel layer, source electrode, drain electrode, gate electrode I, and gate electrode II are located on the insulating substrate, and the electrolyte covers the channel layer, gate electrode I, and gate electrode II. The insulating substrate is flexible, allowing the transistor to operate stably under bending conditions. Gate electrode I and gate electrode II synchronously receive electrical pulse stimulation. The flexible multi-gate electrode synaptic transistor of this invention has a simple structure and is easy to fabricate. The flexible multi-gate electrode transistor has multiple input terminals, and the synchronously input electrical pulses at multiple ports can lead to superlinear summation of the device current, which helps to form accurate and stable memory, thereby performing coincidence detection calculations and memory operations.

Description

Technical Field

[0001] This invention relates to a flexible multi-gate electrode synaptic transistor, its fabrication method, and its application, belonging to the fields of semiconductor devices and neuromorphic computing. Background Technology

[0002] With the advent of the information and intelligent era, the amount of data in society has increased dramatically. However, relying on the traditional von Neumann architecture, which separates storage and computation, severely limits the computer's data processing capabilities. Therefore, to meet the ever-growing demands for data storage and information processing, it is necessary to develop ultra-high-performance computing technologies with ultra-high speed, large capacity, high density, low power consumption, and low cost. This places higher demands on the functionality of computers.

[0003] The human brain is composed of ~10 11 10 neurons and ~10 15 Synapses together form a highly intelligent and complex information processing system. The high degree of integration between computation and storage makes it highly efficient in performing various complex cognitive tasks, such as learning, memory, and decision-making, outperforming even the most advanced digital computers. As one of the basic units of the biological brain, synapses enable neurons to communicate with each other and are responsible for learning and memory. Therefore, simulating synapses is of great significance for promoting the development of bio-inspired neuromorphic systems. Traditional electronic synapse designs based on complementary metal-oxide-semiconductor (CMOS) analog circuits use a large number of transistors and capacitors, encountering severe challenges in practical applications, such as high complexity, high cost, and high power consumption. In recent years, synaptic electronic devices have been proposed for use in synaptic bionics and neuromorphic computing, such as two-terminal devices like memristors and resistive switching memories; and three-terminal devices like ferroelectric synaptic transistors, electrolyte-gated transistors, and interface-controlled transistors.

[0004] Electrolyte-gate transistors (ETTs) are a typical type of ion-controlled transistor that uses an electrolyte material as the gate dielectric layer and a semiconductor as the channel layer. Voltage pulses applied to the gate electrode can regulate the concentration of mobile ions around the channel layer, modulating the channel conductance through electrostatic and chemical doping effects. Extensive research has demonstrated the feasibility of ETTs in simulating biological synaptic memory formation, such as short-term and long-term memory effects, exhibiting good operational stability, low period-to-period variation, and high energy efficiency. Previous research has primarily focused on using single-gate transistors to simulate simple memory functions of homologous synapses, where the memory effect depends entirely on electrical pulses applied to a single gate. In contrast, biological heterosynapses with complex morphologies can effectively integrate information transmitted from multiple synaptic fronts during memory formation, with memory behavior determined by the spatiotemporal correlation between stimuli. Although multi-terminal memristors have experimentally demonstrated heterosynaptic functions, the inputs applied to the additional ports mainly modulate homologous synaptic devices rather than being used for information processing. However, artificial heterosynapses that replicate spatiotemporal information processing functions remain largely unexplored. Summary of the Invention

[0005] In view of the above-mentioned technical status, the present invention aims to provide a flexible multi-gate electrode synaptic transistor, including an insulating substrate, a channel layer material on the substrate, a source electrode, a drain electrode and a gate electrode, and an electrolyte covering the channel and the gate electrode, which together constitute a three-terminal synaptic transistor with a planar gate electrode structure, and the flexible multi-gate electrode synaptic transistor also has good working stability on a flexible substrate.

[0006] The present invention discloses a flexible multi-gate electrode synaptic transistor, comprising an insulating substrate 1, a channel layer 2, an electrolyte 3, a source electrode 4, a drain electrode 5, a gate electrode I 6, and a gate electrode II 7. The channel layer 2, source electrode 4, drain electrode 5, gate electrode I 6, and gate electrode II 7 are located on the insulating substrate 1, and the electrolyte 3 covers the channel layer 2, gate electrode I 6, and gate electrode II 7. The insulating substrate 1 is flexible, allowing the transistor to operate stably under bending conditions. Gate electrode I 6 and gate electrode II 7 synchronously receive electrical pulse stimulation. When applied synchronously, non-volatile conductance can be formed. The synchronous reception of pulses by the dual gate electrodes can lead to superlinear summation of the device current and the formation of non-volatile conductance.

[0007] Preferably, the insulating substrate 1 of the present invention is a flexible substrate, including but not limited to one of polyethylene terephthalate (PET) and polyimide (PI).

[0008] Preferably, the channel layer 2 material of the present invention is an organic semiconductor, including but not limited to one of poly(3-hexylthiophene) and poly(3-alkylthiophene).

[0009] Preferably, the preparation process of the source electrode 4, drain electrode 5, gate electrode I 6, and gate electrode II 7 of the present invention is as follows: Cr or Ti is in contact with an insulating substrate as an adhesive layer, Au, Pt, or W is deposited on Ti, the thickness of the adhesive layer is 1 to 10 nm, and the thickness of Au, Pt, or W is 40 to 100 nm.

[0010] Preferably, the electrolyte 3 of the present invention is an ion gel electrolyte, comprising an electronically insulating polymer and an ionic liquid, wherein the ionic liquid provides mobile ions in the electrolyte to regulate the channel conductivity.

[0011] The ionic liquid is composed of organic cations and inorganic anions;

[0012] The organic cations include, but are not limited to, one of imidazole cations, pyridine cations, and quaternary ammonium cations;

[0013] The organic anions include, but are not limited to, one of tetrafluoroborate anion, hexafluorophosphate anion, difluorosulfonamide anion, and bis(trifluoromethyl)sulfonamide anion.

[0014] The polymer is an organic carrier that is electrically insulating, and preferably includes, but is not limited to, one of poly(vinylidene fluoride) (PVDF), poly(vinylidene fluoride-hexafluoropropylene) (PVDF-HFP), polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), and polyethylene oxide (PEO).

[0015] In some embodiments of the present invention, the ratio of the polymer to the ionic liquid is not limited. Preferably, the content of the ionic liquid in the ionic gel is 60% to 80%.

[0016] The second objective of this invention is to provide a method for fabricating the aforementioned flexible multi-gate electrode synaptic transistor, specifically comprising the following steps:

[0017] (1) Inert metals are deposited as source, drain, and gate electrodes using electron beam evaporation, magnetron sputtering, or thermal evaporation, and the electrode pattern is obtained through a mask.

[0018] (2) Prepare a channel organic semiconductor thin film at the channel formed by the source and drain electrodes.

[0019] (3) After step (2) is completed, the grid electrode and the channel on the sample are covered with electrolyte.

[0020] A third objective of this invention is to propose the application of the aforementioned flexible multi-gate electrode synaptic transistor in flexible wearable devices.

[0021] The beneficial effects of this invention are:

[0022] (1) The flexible multi-gate electrode synaptic transistor of the present invention has a simple structure and is easy to manufacture; the gate dielectric layer of the flexible multi-gate electrode transistor is an electrolyte, which facilitates ion doping and dedoping, and successfully simulates the short-term plasticity and long-term plasticity of biological synapses.

[0023] (2) The flexible multi-gate electrode transistor of the present invention has multiple input terminals. The electrical pulses synchronously input at multiple ports can lead to superlinear summation of device current, which helps to form accurate and stable memory, thereby performing coincidence detection calculation and memory operation.

[0024] (3) The flexible multi-gate electrode transistor described in this invention can work stably on a flexible substrate and under bending conditions, and has excellent bendability, and has broad application prospects in flexible wearable devices. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the planar structure of the flexible multi-gate electrode synaptic transistor in an embodiment of the present invention.

[0026] Figure 2 This refers to the postsynaptic current response of the flexible multi-gate electrode synaptic transistor in this embodiment of the invention, triggered by a single gate electrode.

[0027] Figure 3 This is a simulation of the short-term plasticity of a biological synapse obtained on a single gate electrode by the flexible multi-gate electrode synaptic transistor in this embodiment of the invention.

[0028] Figure 4 This is a simulation of the long-term plasticity of biological synapses obtained by the flexible multi-gate electrode synaptic transistor in the embodiment of the present invention under synchronous input of dual gate electrodes.

[0029] Figure 5 This is a test of the operational stability of the flexible multi-gate electrode synaptic transistor under bending conditions in an embodiment of the present invention.

[0030] Figure 1 1-Insulating substrate; 2-Channel layer; 3-Electrolyte; 4-Source electrode; 5-Drain electrode; 6-Gate electrode I; 7-Gate electrode II. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the scope of protection of the present invention is not limited to the content described.

[0032] Example 1

[0033] In this embodiment, the device structure is as follows: Figure 1As shown, the transistor includes an insulating substrate 1, a channel layer 2, an electrolyte 3, a source electrode 4, a drain electrode 5, a gate electrode I 6, and a gate electrode II 7. The channel layer 2, source electrode 4, drain electrode 5, gate electrode I 6, and gate electrode II 7 are located on the insulating substrate 1, and the electrolyte 3 covers the channel layer 2, gate electrode I 6, and gate electrode II 7. The insulating substrate 1 is flexible, allowing the transistor to operate stably under bending conditions. The gate electrode I 6 and gate electrode II 7 synchronously receive electrical pulse stimulation. The electrolyte contains an organic carrier ionic liquid that is insulating to electrons.

[0034] In this embodiment, the flexible insulating substrate is a PET flexible insulating substrate, the channel layer material is poly(3-hexylthiophene) (P3HT), the source / drain / gate electrode material is Ti / Au, the ionic liquid is [EMI][TFSA], and the organic carrier is poly(vinylidene fluoride-hexafluoropropylene) (P(VDF-HFP)).

[0035] The fabrication method of this flexible multi-gate electrode synaptic transistor includes the following steps:

[0036] (1) The active drain gate electrode pattern is directly covered on the substrate by a mechanical mask, and electron beam evaporation is used as the electrode deposition method to prepare the source drain gate electrode. The schematic diagram of the resulting electrode pattern is shown in the figure. Figure 1 The electrode materials shown are Ti (titanium) and Au (gold), with thicknesses of 10 nm and 80 nm, respectively. Ti serves as the bonding layer between Au and the substrate.

[0037] (2) P3HT (poly(3-hexylthiophene-2,5-dimethyl (stereoregular)) powder was fully dissolved in o-dichlorobenzene solution at a concentration ratio of 10 mg / ml. The sample obtained in step (1) was placed in a plasma cleaner and the adsorption of the substrate surface was modified by plasma cleaning process (process parameters: O2-200 W-10 min) so that P3HT could be more easily combined with the electrode and the substrate. Then, it was placed on the spin coater tray and P3HT solution was dropped on the source and drain channel. The P3HT was spin coated at a speed of 2000 rpm / min for 30 s so that P3HT was evenly coated and covered in the source and drain channel. Then, it was placed on the annealing table and cured at 70 ℃ for 2 h to obtain P3HT film.

[0038] (3) The ionic liquid [EMI][TFSA] (1-ethyl-3-methylimidazoline bis(trifluoromethanesulfonyl)imide), polymer P(VDF-HFP) (poly(vinylidene fluoride-co-hexafluoropropylene)), and acetone were dissolved in acetone at a mass ratio of 1:4:7. The mixture was stirred at 500 rpm / min for 4 h at 50 °C using a magnetic stirrer. At this point, the ionic liquid was in a gel state under the action of the polymer. The semi-solid ionic gel was spin-coated onto a glass substrate at 200 rpm / min for 90 s to obtain an ionic gel film. The spin-coated ionic gel film was then placed in a vacuum oven and dried at 70 °C for 24 h to remove residual solvent and moisture. The dried ionic gel was removed from the vacuum oven and cut into the required shape according to the device structure. Then, the ionic gel was transferred onto the device using tweezers to cover the gate electrode and source / drain channels, resulting in a flexible multi-gate electrode synaptic transistor.

[0039] Example 2

[0040] This embodiment is similar to Embodiment 1, except that the PET insulating substrate 1 is replaced with a PI flexible substrate, and finally a flexible multi-gate electrode synaptic transistor is fabricated.

[0041] Example 3

[0042] This embodiment is similar to Embodiment 1, except that in this embodiment, the gate electrode I6 and gate electrode II7 are changed from being equally distributed on both sides to being distributed in a ring on the same side of the source and drain channels.

[0043] The following performance tests were performed on the device using the Keithley 4200 semiconductor parameter measurement system.

[0044] like Figure 2 The figure shows a typical postsynaptic current response triggered when an electrical pulse with an amplitude of -1.2 V and a duration of 100 ms is applied to a single gate electrode of the device, with a read voltage of -0.1 V. The test results indicate that the device generates an excitatory postsynaptic current when stimulated by an electrical pulse. This is because [TFSA]- in the ionogel electrolyte migrates and accumulates at the ionogel / P3HT interface under the stimulation of the gate voltage, increasing the channel conductivity. After the pulse stimulation ends, the excitatory postsynaptic current of the device returns to its initial state within 5 s. This is because, without gate electrode voltage driving, the [TFSA]- accumulated at the interface spontaneously diffuses and redistributes uniformly within the ionogel; this phenomenon is similar to the short-term plasticity of biological synapses.

[0045] like Figure 3As shown, when a high-frequency electrical pulse (-1.2V, 50 ms) with a frequency of 5.0 Hz is applied to a single gate electrode of the device, the excitatory postsynaptic current increases with the application of the pulse. However, after the pulse ends, the excitatory postsynaptic current decays back to its initial state in a short time. Therefore, when a high-frequency electrical pulse is applied to a single gate electrode, the device exhibits short-term plasticity, indicating that long-term plasticity is not easily obtained on a single gate electrode.

[0046] like Figure 4 The diagram shows the excitatory postsynaptic currents elicited by an electrical pulse (-1.2V, 100ms) applied to two gate electrodes. First, a presynaptic pulse was applied to gate electrodes I6 and II7, respectively, and then simultaneously applied to both gate electrodes I6 and II7. Three excitatory postsynaptic currents were observed. Specifically, when the electrical pulse was applied to gate electrodes I6 or II7 at different times, each stimulation event elicited an excitatory postsynaptic current of approximately 0.3μA. Conversely, for an electrical pulse applied simultaneously to gate electrodes I6 and II7, a higher excitatory postsynaptic current (approximately 1.1μA) was detected. Furthermore, it was observed that when the electrical pulse was applied to gate electrodes I6 or II7 at different times, the current decayed back to its initial value within a short time after the pulse stimulation ended, exhibiting a short-term memory effect. However, after simultaneous electrical pulse stimulation to both gate electrodes, the neuromorphic transistor exhibited a non-volatile conductance modulation effect, demonstrating a long-term memory effect. This result is likely due to the accumulation of a large number of ions near the channel, which penetrate the P3HT film to induce electrochemical doping effects. The strong chemical bonds between the ions and the channel layer prevent backdiffusion of the ions to the gate electrode dielectric after the applied pulse is removed, which improves retention performance and enables the formation of long-term memory. This process mimics the spatiotemporal integration of heterogeneous synaptic spike inputs during memory formation, promoting accurate and stable memory formation.

[0047] like Figure 5 The figure shows the operational stability test results of the device on a flexible substrate under different bending states. The device exhibits an enhancement effect under 40 pulses of stimulation at -3 V for 50 ms, and an inhibition effect under 40 pulses of stimulation at 2.5 V for 50 ms. The figure shows the enhancement and inhibition effects of the device under three conditions: no bending, bending radius of 1 cm, and bending radius of 0.5 cm. The test results show that the device exhibits a consistent variation under all three bending conditions, and the change in conductivity under different bending conditions is negligible, indicating its great potential for application in flexible wearable devices.

Claims

1. A flexible multi-gate electrode synapse transistor, characterized by: The flexible multi-gate electrode synapse transistor comprises an insulating substrate (1), a channel layer (2), an electrolyte (3), a source electrode (4), a drain electrode (5), a gate electrode I (6) and a gate electrode II (7), the channel layer (2), the source electrode (4), the drain electrode (5), the gate electrode I (6) and the gate electrode II (7) are located on the insulating substrate (1), the electrolyte (3) covers the channel layer (2), the gate electrode I (6) and the gate electrode II (7), the insulating substrate (1) is flexible, the transistor can work stably under bending conditions, and the gate electrode I (6) and the gate electrode II (7) synchronously receive electric pulse stimulation. The insulating substrate (1) is one of polyethylene terephthalate and polyimide. The channel layer (2) is one of poly-3-alkylthiophene. The source electrode (4), the drain electrode (5), the gate electrode I (6) and the gate electrode II (7) are prepared by the following process: Cr or Ti is contacted with the insulating substrate to serve as an adhesive layer, Au, Pt or W is deposited on the Ti, the thickness of the adhesive layer is 1-10 nm, and the thickness of the Au, Pt or W is 40-100 nm. The electrolyte (3) is an ionic gel electrolyte, which comprises an electron-insulating polymer and an ionic liquid, wherein the ionic liquid provides movable ions in the electrolyte and controls the channel conductance.

2. The flexible multi-gate electrode synaptic transistor of claim 1, wherein: The ionic liquid is composed of an organic cation and an inorganic anion. The organic cation is one of imidazole cation, pyridine cation and quaternary ammonium cation. The inorganic anion is one of tetrafluoroborate anion, hexafluorophosphate anion and difluorosulfonylimide anion.

3. The flexible multi-gate electrode synaptic transistor of claim 1, wherein: The polymer is an electron-insulating organic carrier, which is one of poly(vinylidene fluoride), poly(vinylidene fluoride-co-hexafluoropropylene), polymethyl methacrylate, polyacrylonitrile and polyethylene oxide.

4. The flexible multi-gate electrode synaptic transistor of claim 1, wherein: The content of the ionic liquid in the ionic gel electrolyte is 60%-80%.

5. The method of claim 1 to 4, wherein the flexible multi-gate electrode synaptic transistor is prepared by the steps of: The method comprises the following steps: (1) inert metal is deposited by electron beam evaporation, magnetron sputtering or thermal evaporation as the source-drain-gate electrode, and the electrode pattern is obtained by a mask plate; (2) an organic semiconductor thin film is prepared at the channel formed by the source-drain electrodes; (3) the gate electrode on the sample after step (2) and the channel are covered with the electrolyte.

6. Application of the flexible multi-gate electrode synapse transistor in claim 1-4 to a flexible wearable device.

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