A weak current signal amplification circuit and extraction circuit

Abstract

The present invention provides a weak current signal amplification circuit, which includes a first to Nth amplification current mirror connected in series, a first to N-1th reference current branch respectively connected in parallel to the input ends of the second to Nth amplification current mirrors, and an Nth reference current branch connected in parallel to the output end of the amplification circuit. When a small effective current signal superimposed on a large reference current is input, it can achieve step-by-step amplification of the small effective current by reducing the reference current, and amplify the small effective current signal when the change in the reference current is not significant.

Description

Technical Field

[0001] The present invention belongs to the field of weak current signal amplification circuits, and more specifically, relates to an amplification circuit for a small effective current superimposed on a large reference current. Background Art

[0002] There are two common methods for weak current detection technology: one is to use an operational amplifier with low noise and low drift current, and connect it into the structure of a transimpedance amplifier to convert the current signal into a voltage signal. The formula for I / V conversion can be recorded as Vout = I * Rf. The other method is as described in Patent 201710533994.7. In order to facilitate the integration of the feedback resistor in the transimpedance amplifier, the current is first amplified by a current mirror, and then the transimpedance amplifier is used for I / V conversion.

[0003] For a signal with a small signal superimposed on a large current reference, the current reference can be considered as a common-mode signal. The usual method is to directly remove the current reference with a subtractor and then perform signal amplification processing.

[0004] However, in the field of sensors, if the effective signal is in the pA level and the current reference is in the μA level, and the difference between the effective signal and the DC reference is 10^6, there are the following problems with the existing technology: Problem 1, when a pA-level signal is superimposed on a μA-level current reference, in order to amplify the pA-level signal, a high amplification factor must be used. When directly using a transimpedance amplifier circuit, the current reference will directly saturate the operational amplifier, and the weak current cannot be extracted; Problem 2, after removing the μA-level current with a subtractor, if directly using I / V conversion, there are problems of difficult integration and noise caused by an overly large Rf resistor. If using a current mirror for amplification, the pA-level current will cause the current mirror to operate in the subthreshold region, and the current will increase exponentially, unable to achieve the purpose of amplifying the current.

[0005] Therefore, it is necessary to solve the problem of amplifying a pA-level weak current signal of a sensor superimposed on a large current reference. Summary of the Invention

[0006] In order to extract a small effective current signal superimposed on a large reference current, the present invention proposes a small effective current amplification circuit that reduces the reference current step by step, which can amplify the small effective current signal when the reference current changes little. Specifically, the present invention relates to an amplification circuit for a small effective current signal superimposed on a large reference current.

[0007] One embodiment of the present invention relates to a weak current signal amplification circuit, which includes: a power supply terminal, the 1st - N + 1 electrical nodes, the 1st - N amplification current mirrors connected in series, the 1st - N - 1 reference current branches respectively connected in parallel with the input ends of the 2nd - N amplification current mirrors, the Nth reference current branch connected in parallel at the output end of the amplification circuit, and a ground terminal; the odd - level amplification current mirrors in the 1st - N amplification current mirrors are connected between the power supply terminal and the electrical nodes, and the even - level amplification current mirrors are connected between the electrical nodes and the ground terminal; the magnitude of the reference current flowing through the reference current branch is related to the amplification factor of the current mirror in parallel therewith, and shunts the current flowing through the current mirror branch in parallel therewith.

[0008] Another embodiment of the present invention relates to a weak current signal extraction circuit, which includes the effective circuit and the reference circuit of the foregoing N - stage current mirror amplification circuit. The input signal of the effective circuit is a small effective current signal superimposed on a large reference current, and the input signal of the reference circuit is the large reference current part in the input signal of the reference circuit; the output signals of the effective circuit and the reference circuit are input into a subtractor circuit for differential amplification of the output signals of the effective circuit and the reference circuit, and a current signal is output.

[0009] The weak current signal extraction circuit further includes an I / V conversion circuit for performing current / voltage conversion on the output current signal after differential amplification and generating an output voltage signal.

[0010] Through the solution of the present invention, it is possible to amplify the sensor output signal in which a small effective current signal is superimposed on a large reference current signal, and at the same time reduce the noise caused by the feedback resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0012] Figure 1 The circuit diagram of an embodiment of a multi - stage current mirror amplification circuit is shown;

[0013] Figure 2 Shows the use of Figure 1 An embodiment of the effective circuit and the reference circuit of the multi - stage current mirror amplification circuit shown;

[0014] Figure 3 Shows for Figure 2 An embodiment of a subtractor circuit for differential amplification of the outputs of the effective circuit and the reference circuit shown;

[0015] Figure 4 shows an Figure 3 embodiment of an I / V conversion circuit for performing current / voltage conversion on the shown subtractor circuit. Detailed implementation manners

[0016] The technical solutions in the specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] The embodiment relates to a weak current signal amplification circuit and a weak current signal extraction circuit. Specifically, the weak current signal is a small effective current signal superimposed on a large reference current signal. For example, the large reference current signal is a common-mode signal, and the small effective current signal is a differential-mode signal. In one embodiment, the large reference current signal is in the microampere level, and the small effective current signal is in the picoampere level. At this time, the magnitude difference between the large current signal and the small current signal is 10^6. Sensor output signals with other exponentially different reference currents and effective current signals can also be provided.

[0018] In one embodiment, a first current mirror amplification circuit is provided to amplify a first input current. The first input current is a sensor output signal with a small effective current signal i1 superimposed on a large reference current signal I0. In one embodiment, the first current mirror amplification circuit includes N amplification current mirrors connected in series. The N amplification current mirrors are used to amplify their respective input currents. The first current mirror amplification circuit further includes N reference current branches. The N reference current branches are connected in parallel on the input side of the 2-Nth amplification current mirror and the output side of the first current mirror amplification circuit. The N reference current branches are used to shunt their respective parallel branches. The magnitude of the reference current flowing through the reference current branch is related to the amplification factor of the current mirror. In one embodiment, the amplification factor of the Nth stage current mirror is α N , and the reference current is (α N -1)*I0. It is also possible to set other reference currents related to the amplification factors of each stage of the current mirror.

[0019] In one embodiment, a second current mirror amplifier circuit is provided for amplifying a second input current and outputting a second current output signal. The second input current is set with reference to the first input current. In one embodiment, the second input current is the reference current signal I0 in the sensor output signal. The second current mirror amplifier circuit has a similar structure to the first current mirror amplifier circuit. For example, the second current mirror amplifier circuit includes N amplifying current mirrors for amplifying their respective input currents. The second current mirror amplifier circuit further includes N reference current branches. The N reference current branches are connected in parallel on the input side of the (2 - N)th amplifying current mirror and on the output side of the second current mirror amplifier circuit. The N reference current branches are used to shunt their respective parallel branches. The magnitude of the reference current flowing through the N reference current branches is related to the amplification factor of the amplifying current mirror. In one embodiment, the amplification factor of each stage of the current mirror is β N , and the reference current is (β N - 1)*I0. It is also possible to set other reference currents related to the amplification factor of each stage of the current mirror.

[0020] In one embodiment, a subtractor circuit is provided to differentially amplify the output signals of the first and second current mirror amplifier circuits. The subtractor circuit eliminates the common - mode current of the sensor output signal and amplifies the differential - mode current. The subtractor circuit, in one embodiment, is a current mirror subtractor. For example, the subtractor circuit is a multi - stage current mirror subtractor.

[0021] In one embodiment, an I / V conversion circuit is provided to perform current - to - voltage conversion on the output signal of the subtractor circuit. In one embodiment, the I / V conversion circuit is a transimpedance amplifier.

[0022] Figure 1 An embodiment of a multi - stage current mirror amplifier circuit for amplifying a sensor output signal in which a small effective current signal is superimposed on a large reference current signal is shown. The multi - stage current mirror amplifier circuit includes a plurality of amplifying current mirrors and a plurality of reference current branches. As Figure 1 , the multi - stage current mirror amplifier circuit is a three - stage current mirror amplifier circuit. The multi - stage current mirror amplifier circuit can also adopt current mirror amplifier circuits with other numbers of stages.

[0023] In one embodiment, the three - stage current mirror amplifier circuit includes a power supply terminal, a ground terminal, an input signal terminal, an output signal terminal, and four electrical nodes. In one embodiment, the input signal is realized by an input signal equivalent current source connected between the ground terminal and the first electrical node, and the output signal is realized by an output signal equivalent current source connected between the ground terminal and the fourth electrical node.

[0024] In one embodiment, the three-stage current mirror amplifier circuit includes three amplified current mirrors. For example, the three amplified current mirrors include: a first amplified current mirror composed of MOS transistors M1 and M2, a second amplified current mirror composed of MOS transistors M3 and M4, and a third amplified current mirror composed of MOS transistors M5 and M6. The first amplified current mirror is connected between a power supply terminal and first and second electrical nodes, the second amplified current mirror is connected between the second and third electrical nodes and a ground terminal, and the third amplified current mirror is connected between the power supply terminal and the third and fourth electrical nodes.

[0025] In one embodiment, the three-stage current mirror amplifier circuit further includes three reference current branches. The three reference current branches include a first reference current branch, a second reference current branch, and a third reference current branch. In one embodiment, the reference current branch includes first, second, and third reference current sources for generating reference currents. The first reference current source is connected between the second electrical node and the ground terminal, the second reference current source is connected between the power supply terminal and the third electrical node, and the third reference current source is connected between the fourth electrical node and the ground terminal.

[0026] During operation, a first current I1 generated by an input signal equivalent current source is provided as an input current signal to the first amplified current mirror composed of MOS transistors M1 and M2. The MOS transistor M1 is connected between the first electrical node and the power supply terminal, and its gate is connected to the first electrical node and further connected to the gate of the MOS transistor M2. The MOS transistor M2 is connected between the power supply terminal and the second electrical node. Therefore, the gates and sources of the MOS transistor M1 and the MOS transistor M2 are respectively connected, and the gate of the MOS transistor M1 is connected to its drain. The first amplified current mirror amplifies and generates a second current I2 according to the first current I1. For example, if the amplification factor of the first amplified current mirror is α1, then the second current I2 = α1 * I1, where α is any positive number. In one embodiment, α1 is an integer for circuit matching.

[0027] The second current I2 is supplied to a second amplified current mirror composed of MOS transistors M3 and M4 and a first reference current branch. The transistor M3 is connected between a second electrical node and a ground terminal, and the gate of the transistor M3 is connected to the second electrical node and further connected to the gate of the transistor M4. The transistor M4 is connected between a third electrical node and the ground terminal. Thus, the gates and drains of the transistors M3 and M4 are connected respectively, and the gate of the transistor M3 is connected to its source. The first reference current branch is connected between the second electrical node and the ground terminal. Thus, the first reference current branch is connected in parallel with the second amplified current mirror. The first reference current branch, for example, provides a first reference current Iref1 through an equivalent current source. At this time, the current flowing into the second amplified current mirror is I2 - Iref1 = α1*I1 - Iref1. The second amplified current mirror amplifies and generates a third current I3 according to the input current. For example, if the amplification factor of the second amplified current mirror is α2, then the third current I3 is α2*I2, where α2 can be a positive number of any magnitude. In one embodiment, α2 is an integer for circuit matching convenience.

[0028] The third current I3 is supplied to a third amplified current mirror composed of MOS transistors M5 and M6 and a second reference current branch. The transistor M5 is connected between a power supply terminal and the third electrical node, and the gate of the transistor M5 is connected to the third electrical node and further connected to the gate of the transistor M6. The transistor M6 is connected between the power supply terminal and a fourth electrical node. Thus, the gates and sources of the transistors M5 and M6 are connected respectively, and the gate of the transistor M5 is connected to its drain. The second reference current branch is connected between the power supply terminal and the third electrical node. Thus, the second reference current branch is connected in parallel with the third amplified current mirror. The second reference current branch, for example, provides a second reference current Iref2 through an equivalent current source. In one embodiment, the current supplied to the third amplified current mirror is I3 - Iref2 = α2*I2 - Iref2. The third amplified current mirror amplifies and generates a fourth current I4 according to the input current. For example, if the amplification factor of the third amplified current mirror is α3, then the fourth current I4 is α3*I3, where α3 can be a positive number of any magnitude. In one embodiment, α3 is an integer for circuit matching convenience.

[0029] The fourth current I4 is provided to the output signal branch and the third reference current branch. The output signal branch is connected between the fourth electrical node and the ground terminal. The output signal branch, for example, provides an output signal Io1 through an equivalent current source. The third reference current branch is connected between the fourth electrical node and the ground terminal. Therefore, the third reference current branch is connected in parallel with the output signal branch. The third reference current branch, for example, provides a third reference current Iref3 through an equivalent current source. In one embodiment, the output signal Io1 = I4 - Iref3 = α3 * I3 - Iref3.

[0030] In one embodiment, the input current I1 of the amplifier circuit is set to the sensor output signal to be measured, for example, a small effective current signal i1 superimposed on a large reference current I0.

[0031] A first current I1 = I0 + i1 generated by the input signal equivalent current source is provided as an input current signal to a first amplified current mirror composed of MOS transistors M1 and M2. The MOS transistor M1 is connected between the first electrical node and the power supply terminal, and its gate is connected to the first electrical node and further connected to the gate of the MOS transistor M2. The MOS transistor M2 is connected between the power supply terminal and the second electrical node. The gates and sources of the MOS transistor M1 and the MOS transistor M2 are respectively connected, and the gate of the MOS transistor M1 is connected to its drain. Therefore, the first amplified current mirror amplifies and generates a second current I2 according to the first current I1. For example, if the amplification factor of the first amplified current mirror is α1, then the second current I2 = α1 * I1 = α1 * (I0 + i1), where α1 is any positive number. In one embodiment, α1 is any integer for easy circuit matching.

[0032] The second current I2 is supplied to a second amplifying current mirror composed of MOS transistors M3 and M4 and a first reference current branch. The transistor M3 is connected between a second electrical node and a ground terminal, and the gate of the transistor M3 is connected to the second electrical node and further connected to the gate of the transistor M4. The transistor M4 is connected between a third electrical node and the ground terminal. Thus, the gates and drains of the transistors M3 and M4 are connected respectively, and the gate of the transistor M3 is connected to its source. The first reference current branch is connected between the second electrical node and the ground terminal. Thus, the first reference current branch is connected in parallel with the second amplifying current mirror. The first reference current branch, for example, provides a first reference current Iref1 through an equivalent current source. At this time, the current flowing into the second amplifying current mirror is I2 - Iref1 = α1 * I1 - Iref1. In one embodiment, it is set that Iref1 = (α1 - 1) * I0, then the current flowing into the second amplifying current mirror is α1 * I1 - Iref1 = I0 + α1 * i1. The second amplifying current mirror amplifies according to the input current and generates a third current I3. For example, the amplification factor of the second amplifying current mirror is α2, then the third current I3 is α2 * I0 + α2 * α1 * i1, where α2 is any positive number. In one embodiment, α2 is any integer for facilitating circuit matching. It is also possible to set other appropriately sized first reference currents.

[0033] The third current I3 is supplied to a third amplifying current mirror composed of MOS transistors M5 and M6 and a second reference current branch. The transistor M5 is connected between a power supply terminal and the third electrical node, and the gate of the transistor M5 is connected to the third electrical node and further connected to the gate of the transistor M6. The transistor M6 is connected between the power supply terminal and a fourth electrical node. Thus, the gates and sources of the transistors M5 and M6 are connected respectively, and the gate of the transistor M5 is connected to its drain. The second reference current branch is connected between the power supply terminal and the third electrical node. Thus, the second reference current branch is connected in parallel with the third amplifying current mirror. The second reference current branch, for example, provides a second reference current Iref2 through an equivalent current source. In one embodiment, it is set that Iref2 = (α2 - 1) * I0, then the current supplied to the third amplifying current mirror is I3 - Iref2 = α2 * I0 + α2 * α1 * i1 - Iref2 = I0 + α2 * α1 * i1. The third amplifying current mirror amplifies according to the input current and generates a fourth current I4. For example, the amplification factor of the third amplifying current mirror is α3, then the fourth current I4 is α3 * I0 + α3 * α2 * α1 * i1, where α3 is any positive number. In one embodiment, α3 is any integer for facilitating circuit matching. It is also possible to set other sized second reference currents.

[0034] The fourth current I4 is provided to an output signal branch and a third reference current branch. The output signal branch is connected between a fourth electrical node and a ground terminal. The output signal branch provides an output signal Io1, for example, through an equivalent current source. The third reference current branch is connected between the fourth electrical node and the ground terminal. Therefore, the third reference current branch is connected in parallel with the output signal branch. The third reference current branch provides a third reference current Iref3, for example, through an equivalent current source. In one embodiment, Iref3 = (a3 - 1)*I0 is set, then the output signal Io1 = I4 - Iref3 = α3*I0 + α3*α2*α1*i1 - (a3 - 1)*I0 = I0 + α3*α2*α1*i1. Other appropriately sized third reference currents can also be set.

[0035] Figure 2 illustrates the use of Figure 1 An embodiment of an active circuit and a reference circuit of the three-stage current mirror amplifier circuit shown. For example, the circuit structures of the active circuit and the reference circuit are the same as or similar to Figure 1 the structure of the three-stage current mirror amplifier circuit shown therein. Similar elements or components will not be described or described in detail. In one embodiment, the input current of the active circuit is set to the sensor output signal I1 to be measured, for example, a small active current signal i1 superimposed on a large reference current I0. After passing through the three-stage current mirror amplifier circuit, an output current Io1 is obtained. The input current I5 of the reference circuit is set to the reference current signal I0 in the sensor output signal. After passing through the three-stage current mirror amplifier circuit, an output current Io2 is obtained.

[0036] Referring to Figure 2 the active circuit shown in FIG. a, a first current I1 = I0 + i1 generated by an input signal equivalent current source is provided as an input current signal to a first amplifying current mirror composed of MOS transistors M1 and M2. The MOS transistor M1 is connected between a first electrical node and a power supply terminal, and its gate is connected to the first electrical node and further connected to the gate of the MOS transistor M2. The MOS transistor M2 is connected between the power supply terminal and a second electrical node. The gates and sources of the MOS transistor M1 and the MOS transistor M2 are respectively connected, and the gate of the MOS transistor M1 is connected to its drain. Therefore, the first amplifying current mirror amplifies and generates a second current I2 according to the first current I1. For example, if the amplification factor of the first amplifying current mirror is α1, then the second current I2 = α1*I1 = α1*(I0 + i1), where α1 is any positive number. In one embodiment, α1 is any integer for facilitating circuit matching.

[0037] The second current I2 is supplied to a second amplified current mirror composed of MOS transistors M3 and M4 and a first reference current branch. The transistor M3 is connected between a second electrical node and a ground terminal, and the gate of the transistor M3 is connected to the second electrical node and further connected to the gate of the transistor M4. The transistor M4 is connected between a third electrical node and the ground terminal. Therefore, the gates and drains of the transistor M3 and the transistor M4 are respectively connected, and the gate of the transistor M3 is connected to its source. The first reference current branch is connected between the second electrical node and the ground terminal. Therefore, the first reference current branch is connected in parallel with the second amplified current mirror. The first reference current branch provides a first reference current Iref1, for example, through an equivalent current source. At this time, the current flowing into the second amplified current mirror is I2 - Iref1 = α1*I1 - Iref1. In one embodiment, it is set that Iref1 = (a1 - 1)*I0, then the current flowing into the second amplified current mirror is α1*I1 - Iref1 = I0 + α1*i1. The second amplified current mirror amplifies according to the input current and generates a third current I3. For example, the amplification factor of the second amplified current mirror is α2, then the third current I3 is α2*I0 + α2*α1*i1, where α2 is any positive number. In one embodiment, α2 is any integer for circuit matching. It is also possible to set other appropriately sized first reference currents.

[0038] The third current I3 is supplied to a third amplified current mirror composed of MOS transistors M5 and M6 and a second reference current branch. The transistor M5 is connected between a power supply terminal and the third electrical node, and the gate of the transistor M5 is connected to the third electrical node and further connected to the gate of the transistor M6. The transistor M6 is connected between the power supply terminal and a fourth electrical node. Therefore, the gates and sources of the transistor M5 and the transistor M6 are respectively connected, and the gate of the transistor M5 is connected to its drain. The second reference current branch is connected between the power supply terminal and the third electrical node. Therefore, the second reference current branch is connected in parallel with the third amplified current mirror. The second reference current branch provides a second reference current Iref2, for example, through an equivalent current source. In one embodiment, it is set that Iref2 = (a2 - 1)*I0, then the current supplied to the third amplified current mirror is I3 - Iref2 = α2*I0 + α2*α1*i1 - Iref2 = I0 + α2*α1*i1. The third amplified current mirror amplifies according to the input current and generates a fourth current I4. For example, the amplification factor of the third amplified current mirror is α3, then the fourth current I4 is α3*I0 + α3*α2*α1*i1, where α3 is any positive number. In one embodiment, α3 is any integer for circuit matching. It is also possible to set other appropriately sized second reference currents.

[0039] The fourth current I4 is supplied to the output signal branch and the third reference current branch. The output signal branch is connected between the fourth electrical node and the ground terminal. The output signal branch provides an output signal Io1, for example, through an equivalent current source. The third reference current branch is connected between the fourth electrical node and the ground terminal. Therefore, the third reference current branch is connected in parallel with the output signal branch. The third reference current branch provides a third reference current Iref3, for example, through an equivalent current source. In one embodiment, if Iref3 = (a3 - 1)*I0, then the output signal Io1 = I4 - Iref3 = α3*I0 + α3 *α2*α1*i1 - (a3 - 1)*I0 = I0 + α3 *α2*α1*i1. Other appropriately sized third reference currents can also be set.

[0040] Referring to Figure 2 the reference circuit shown in FIG. b, a fifth current I5 = I0 generated by the input signal equivalent current source is provided as an input current signal to a fourth amplified current mirror composed of MOS transistors M7 and M8. The MOS transistor M7 is connected between the fifth electrical node and the power supply terminal, and its gate is connected to the fifth electrical node and further connected to the gate of the MOS transistor M8. The MOS transistor M8 is connected between the power supply terminal and the fifth electrical node. Therefore, the gates and sources of the MOS transistor M7 and the MOS transistor M8 are respectively connected, and the gate of the MOS transistor M7 is connected to its drain. Therefore, the fourth amplified current mirror amplifies and generates a sixth current I6 according to the fifth current I5. For example, if the amplification factor of the fourth amplified current mirror is α4, then the sixth current I6 = α4*I5 = α4*I0, where α4 is any positive number. In one embodiment, α4 is any integer for circuit matching.

[0041] The sixth current I6 is supplied to a fifth current amplification mirror composed of MOS transistors M9 and M10 and a fourth reference current branch. The transistor M9 is connected between a sixth electrical node and a ground terminal, and the gate of the transistor M9 is connected to the sixth electrical node and further connected to the gate of the transistor M10. The transistor M9 is connected between a seventh electrical node and the ground terminal. Therefore, the gates and drains of the transistor M9 and the transistor M10 are respectively connected, and the gate of the transistor M9 is connected to its source. The fourth reference current branch is connected between the sixth electrical node and the ground terminal. Therefore, the fourth reference current branch is connected in parallel with the fifth current amplification mirror. The fourth reference current branch provides a fourth reference current Iref4, for example, through an equivalent current source. At this time, the current flowing into the fifth current amplification mirror is I6 - Iref4 = α4 * I0 - Iref4. In one embodiment, Iref4 is set to (a4 - 1) * I0, then the current flowing into the fifth current amplification mirror is α4 * I0 - Iref4 = I0. The fifth current amplification mirror amplifies according to the input current and generates a seventh current I7. For example, if the amplification factor of the fifth current amplification mirror is α5, then the seventh current I7 is α5 * I0, where α5 is any positive number. In one embodiment, α5 is any integer for facilitating circuit matching. Other magnitudes of the fourth reference current can also be set.

[0042] The seventh current I7 is supplied to a sixth current amplification mirror composed of MOS transistors M11 and M12 and a fifth reference current branch. The transistor M11 is connected between a power supply terminal and the seventh electrical node, and the gate of the transistor M11 is connected to the seventh electrical node and further connected to the gate of the transistor M12. The transistor M12 is connected between the power supply terminal and an eighth electrical node. Therefore, the gates and sources of the transistor M11 and the transistor M12 are respectively connected, and the gate of the transistor M11 is connected to its drain. The fifth reference current branch is connected between the power supply terminal and the seventh electrical node. Therefore, the fifth reference current branch is connected in parallel with the sixth current amplification mirror. The fifth reference current branch provides a fifth reference current Iref5, for example, through an equivalent current source. In one embodiment, Iref5 is set to (a5 - 1) * I0, then the current supplied to the sixth current amplification mirror is I7 - Iref5 = α5 * I0 - Iref5 = I0. The sixth current amplification mirror amplifies according to the input current and generates an eighth current I8. For example, if the amplification factor of the sixth current amplification mirror is α6, then the eighth current I8 is α6 * I0, where α6 is any positive number. In one embodiment, α6 is any integer for facilitating circuit matching. Other appropriate magnitudes of the fifth reference current can also be set.

[0043] The eighth current I8 is provided to the output signal branch and the sixth reference current branch. The output signal branch is connected between the eighth electrical node and the ground terminal. The output signal branch, for example, provides an output signal Io2 through an equivalent current source. The sixth reference current branch is connected between the eighth electrical node and the ground terminal. Therefore, the sixth reference current branch is connected in parallel with the output signal branch. The sixth reference current branch, for example, provides a sixth reference current Iref6 through an equivalent current source. In one embodiment, if Iref6 = (a6 - 1)*I0, then the output signal Io2 = I8 - Iref6 = α6*I0 - (a6 - 1)*I0 = I0. Other appropriately sized sixth reference currents can also be set.

[0044] Referring to Figure 3 , the subtractor circuit differentially amplifies the output signals of the valid circuit and the reference circuit. For example, the subtractor circuit differentially amplifies Figure 1 the output signal Io1 of the valid circuit shown in Figure 2 and the output signal Io2 of the reference circuit shown in. The subtractor circuit, for example, includes a multi-stage amplified current mirror connected in series to perform multi-stage amplification on the differential signal of Io1 and Io2. In one embodiment, the multi-stage amplified current mirror has a two-stage structure. If the current amplification is insufficient, additional current mirrors can be added to amplify the current. Other suitable amplification structures or subtractor circuits can also be used.

[0045] As Figure 3 shown, the two-stage current mirror subtractor circuit includes a power supply terminal, a ground terminal, electrical nodes VA, VB, and VC. The output current Io1 of the valid circuit and the output current Io2 of the reference circuit are provided to the electrical node VB for differential operation to eliminate the reference and noise currents, and then the output current IB = Io1 - Io2 = α3*α2*α1*i1 is further provided to the two-stage current mirror for amplification to obtain the output current IC. In one embodiment, the output current Io1 of the valid circuit is implemented by an equivalent current source connected between the power supply terminal and the electrical node VB. The output current Io2 of the reference circuit is implemented by an equivalent current source connected between the electrical node VB and the ground node.

[0046] The two-stage amplified current mirror includes a seventh amplified current mirror composed of MOS transistors M13 and M14, and an eighth amplified current mirror composed of MOS transistors M15 and M16. The transistor M14 of the seventh amplified current mirror and the transistor M15 of the eighth amplified current mirror are connected in series through the electrical node VA.

[0047] The transistor M13 in the seventh current mirror is connected between the electrical node VB and the ground terminal. The gate of the transistor M13 is connected to the electrical node VB and further connected to the gate of M14. The transistor M14 is connected between the electrical node VA and the ground node. Therefore, the gates and drains of the transistor M13 and the transistor M14 are connected respectively, and the gate and source of the transistor M13 are connected. The seventh current mirror generates the current IA according to the current IB. For example, if the amplification factor of the seventh current mirror is d, the output current IA = d * IB = d * α3 * i1. Other amplification factors are also possible.

[0048] The transistor M15 in the eighth current mirror is connected between the power supply terminal and the electrical node VA. The gate of the transistor M15 is connected to the electrical node VA and further connected to the gate of M16. The transistor M16 is connected between the power supply terminal and the electrical node VC. Therefore, the gates and sources of the transistor M15 and the transistor M16 are connected respectively, and the gate and drain of the transistor M15 are connected. The eighth current mirror generates the current IC according to the current IA. For example, if the amplification factor of the eighth current mirror is d, the output current IC = d * IA = d2 * α4 * i1. Other amplification factors are also possible.

[0049] In one embodiment, to reduce the channel length modulation effect of M14, feedback can be used to ensure that the voltage at point VA is the same as VB. For example, two potentials are made close by an operational amplifier.

[0050] Refer to Figure 4 , an I / V conversion circuit is provided to perform I / V conversion on the output current signal of Figure 3 the subtractor circuit. For example, the I / V conversion circuit performs I / V conversion on the current IC and outputs the voltage Vout. In one embodiment, the I / V conversion circuit is a transimpedance amplifier.

[0051] The transimpedance amplifier includes a feedback resistor Rf and an operational amplifier A. The feedback resistor Rf is connected between the inverting input terminal and the output terminal of the operational amplifier A, and the non-inverting input terminal of the operational amplifier is connected to the ground terminal. During operation, the output current of the subtractor is provided to the inverting input terminal of the operational amplifier, and after I / V conversion, the output voltage Vout = IC * Rf.

[0052] Among them, since the current IC has been amplified through multiple stages, the selection of Rf is based on the optimal noise parameters. For example, a relatively small resistor can be selected for Rf.

[0053] After being converted into a voltage signal, according to the input range of the ADC, etc., multiple-stage voltage amplification can be connected at the backend, and then enter the ADC and the processor, where signal processing and the like are implemented in the processor.

[0054] The above has introduced in detail the weak current signal amplification circuit and extraction circuit provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A weak current signal amplification circuit, the amplification circuit comprising: A power supply terminal, a first to an N+1 electrical node, a first to an N amplifying current mirror connected in series, a first to an N-1 reference current branch respectively connected in parallel with the input ends of the second to an N amplifying current mirror, an Nth reference current branch connected in parallel at the output end of the amplifying circuit, and a ground terminal; the odd-stage amplifying current mirrors in the first to an N amplifying current mirror are connected between the power supply terminal and the electrical node, and the even-stage amplifying current mirrors are connected between the electrical node and the ground terminal; The magnitude of the reference current flowing through the reference current branch is related to the amplification factor of the current mirror in parallel therewith, and shunts the current flowing through the current mirror branch in parallel therewith. Wherein, the input signal of the amplification circuit is a small effective current signal i1 superimposed on a large reference current I0, and the amplification factor of the current mirror is α N , α N is an arbitrary integer, and the current in the reference current branch is (α N -1)×I0.

2. The weak current signal amplifying circuit according to claim 1, wherein the amplifying current mirror comprises a first transistor and a second transistor.

3. The weak current signal amplifying circuit according to claim 2, wherein the first transistor in the odd-stage amplifying current mirror is connected between the electrical node and the power supply terminal, its gate is connected to the electrical node and further connected to the gate of the second transistor, the second transistor is connected between the power supply terminal and the electrical node, the gates and sources of the first transistor and the second transistor are respectively connected, and the gate of the first transistor is connected to its drain.

4. The weak current signal amplifying circuit according to claim 2, wherein the first transistor in the even-stage amplifying current mirror is connected between the electrical node and the ground terminal, the gate of the second transistor is connected to the electrical node and further connected to the gate of the second transistor, the second transistor is connected between the electrical node and the ground terminal, the gates and drains of the first transistor and the second transistor are respectively connected, and the gate of the first transistor is connected to its source.

5. A weak current signal extraction circuit, including an effective circuit and a reference circuit both implemented by using the N-stage current mirror amplifier circuit of claim 1. The input signal of the effective circuit is a small effective current signal i1 superimposed on a large reference current I0, and the input signal of the reference circuit is the large reference current part I0 in the input signal of the reference circuit. The output signals of the effective circuit and the reference circuit are input into a subtractor circuit for differential amplification of the output signals of the effective circuit and the reference circuit and outputting a current signal; wherein, The magnitude of the reference current flowing through the reference current branch of the effective circuit is related to the amplification factor of the current mirror, and the amplification factor of the current mirror is α N , α N is an arbitrary integer, and the reference current is (α N -1)×I0; The magnitude of the reference current flowing through the reference current branch of the reference circuit is related to the amplification factor of the current mirror, and the amplification factor of the current mirror is β N , β N is an arbitrary integer, and the reference current is (β N - 1) × I0.

6. The weak current signal extraction circuit according to claim 5, wherein the subtractor circuit is a current mirror subtractor.

7. The weak current signal extraction circuit according to claim 6, wherein the current mirror subtractor is a multi-stage current mirror connected in series.

8. The weak current signal extraction circuit according to claim 5, further comprising an I / V conversion circuit for performing current / voltage conversion on the output current signal and generating an output voltage signal.

9. The weak current signal extraction circuit according to claim 8, wherein the I / V conversion circuit is a transimpedance amplifier.

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