General purpose compressor architecture for testing circuits

Abstract

A circuit includes scan gating devices interposed between outputs of scan chains and inputs of a test response compressor. The scan gating devices divide the scan chains into groups of scan chains. Each scan gating device operates in an enable mode or in a disable mode based on a first signal. Scan gating devices operating in the enable mode block, block only at some clock cycles, or do not block a portion of test responses of test patterns captured by and output from the scan chains in the associated group of scan chains based on a second signal. Scan gating devices operating in the disable mode do not block, or block or do not block a portion of test responses captured by and output from all scan chains in each of the associated groups of scan chains based on a third signal.

Description

TECHNICAL FIELD

[0001] The presently disclosed technology relates to circuit testing. Various implementations of the disclosed technology are particularly useful for suppressing X-states in circuit test responses. BACKGROUND

[0002] Test data compression is widely recognized as instrumental in reducing the overall cost of scan-based semiconductor device testing. With aggressive technology scaling, test response compression working in tandem with test stimulus compression plays a key role in handling the test data volume growth. The development of compression schemes reflects the ever-changing needs of many applications and addresses the never-satisfied demand of consumers for higher performance at lower cost. Logic built-in self-test (LBIST) with on-chip test compression has recently re-emerged as a viable in-system test alternative. In many cases, this hybrid technique is considered a safe mechanism that can be applied periodically during the run-time of a device to detect faults in automotive integrated circuits and other safety-critical applications. The hybrid technique provides high test coverage that is achievable in very short time periods, including in-field test procedures. As the architectural differences between test compression and LBIST gradually blur, design for test (DFT) implementations can effectively share test logic between the two approaches, including test response compressors. Therefore, an important requirement for a reliable compressor is to maintain observability of scan cells while (1) maintaining very high compression rates, (2) providing the ability to detect a variety of faults found in actual silicon, and (3) ensuring design simplicity.

[0003] Test response compaction is susceptible to unknown (X) states, which can render a test useless. X values can occur in complex designs due to uninitialized memory elements, unscanned flip-flops, bus contention, floating buses, unwrapped analog blocks, internal tri-state logic, cross-clock domain signals, timing anomalies, or multi-cycle and false paths when generating speed tests. These states, once captured in scan cells, can subsequently be injected into a test response compaction, where they can severely impact test results. In particular, X states can proliferate due to the feedback deployed by time compaction (e.g., multiple-input signature register (MISR)). While modular time compaction prevents a large increase in unknown states by looping registers, looping registers can only partially reduce the negative impact of X states. Combinational compaction remains relatively immune to X states, but in order to avoid masking, they need to observe each scan chain on two or more outputs. Finite memory compaction empties X states from its registers over multiple scan shift cycles. However, even if test compaction is designed to tolerate a certain amount of X states, these X states can quickly get the upper hand, impeding the observability of many scan cells and causing a drop in fault coverage. Therefore, compaction needs protection mechanisms that can effectively mask X states by, for example, deploying scan chain selection schemes.

[0004] The ability to selectively observe scan chains has been extensively studied for many years. Proposed solutions provide various trade-offs between on-chip logic complexity, collateral damage (representing unintentional masking of non-X values) and test data required to control X-masking. For example, a solution known as OPMISR endows the circuit with the feature of masking selected offload values such that X states do not reach the compressor. In another solution, selective compressors are used as a component part of an embedded deterministic test (EDT) technique. It masks a given number of scan chains by deploying register files to encode the targeted scan chains. In yet another solution, LFSR (linear-feedback shift register) replay is used to gate the scan chains per cycle. The masking signal obtained in this way can be further formed by "AND" phase shifter outputs to reduce the probability of blocking non-X responses. In yet another solution, each input is connected to two outputs and each two outputs share a separate input in a two-level selector of an X-tolerant deterministic BIST. It allows observing a small fraction of scan chains. In yet another solution, X-masking logic allows a certain amount of over-masking while it is obtained as an instance of irrelevant logic synthesis where inputs are provided by any LBIST or test compression solution. In yet another solution, a channel masking either disables all scan chains or selects scan chains belonging to one of two groups at the expense of possible over-masking. In yet another solution, a two-level scan selection mechanism and sequential overdrive sections are employed. These modules are connected together using a scan chain ordering algorithm for handling a wide range of X state profiles and directing X state suppression. In yet another solution, a BIST-like selective masking of scan chains is performed to block X states per cycle. It relies on a finding that many test responses in scan-based designs have identical or similar X state patterns that occur in consecutive and adjacent regions of scan chains.

[0005] Different classes of solutions attempt to make the test response compactor X-tolerant. For example, a weighted pseudorandom pattern generator (PRPG) can be used to implement an X-tolerant multiple-input signature register. In this scheme, the absence of data transfer between storage elements and the high probability of X masking are the basis of X-tolerance. In another scheme, an X filter removes the effect of X states from the test response compressed by error-correcting codes while preserving their essential functionality. Similarly, MISR-based schemes are able to handle a given number of X states. This scheme periodically applies X filtering to counteract multiple Xs and restore all bits of the original signature, which is then unloaded. A convolutional compactor that tolerates a certain number of X values in a single time frame can also be designed by exploiting a Steniner system as a particular kind of systolic block design process. However, despite best efforts, X-tolerant compressors can still need to resort to masking of scan chains. In fact, in many applications, X-tolerance is not sufficient to prevent damage to test results unless expensive and complex test logic is deployed to effectively cope with large bursts of unknown values. Thus, scan chain selection remains the mainstream technology in the field of X-masking.

[0006] X-masking schemes for convergent applications of test compression and logic BIST must respond to multiple challenges and stringent requirements of field and in-system testing. First, controlling scan selection is critical for a wide range of X state profiles, and the amount of additional information is minimal so that this data does not jeopardize effective test compression rates. Moreover, since X-masking hardware still occupies a non-negligible space in many scan selection schemes, this overhead must be reduced, especially in designs with hundreds (or even thousands) of scan chains that can require programmable and very flexible selection algorithms. Thus, there is a need to develop new scan chain selection schemes that include simple and modular scan selection logic that allows X states to be masked within a redefinable scan chain group and a specified scan shift cycle. SUMMARY

[0007] Various aspects of the disclosed technology relate to scan selection based X-masking for testing response compression. In one aspect, there is a circuit comprising: a scan chain comprising scan cells, the scan chain configured to shift into a test mode, apply the test mode to the circuit, capture a test response of the circuit, and shift out the test response; a test response compressor configured to compress the test response; and scan gating devices interposed between outputs of the scan chain and inputs of the test response compressor, the scan gating devices dividing the scan chain into scan chain groups, each of the scan gating devices receiving a signal from an output of one of the scan chain groups and operating in an enable mode or a disable mode based on a first signal, wherein a scan gating device operating in the enable mode blocks, blocks only at one or more clock cycles, or does not block, based on a second signal, a portion of a test response of the test mode captured by and output from a scan chain in a scan chain group from reaching the test response compressor, wherein the scan chain in the scan chain group is coupled to the scan gating device operating in the enable mode, and wherein a scan gating device operating in the disable mode does not block, or blocks or does not block, based on a third signal, a portion of a test response of the test mode captured by and output from all scan chains in each of the scan chain groups from reaching the test response compressor, wherein the all scan chains in each of the scan chain groups are coupled to the scan gating device operating in the disable mode.

[0008] The circuit can further comprise: address translation and decoding circuitry configured to generate the first signal based on an address signal, or a combination of the address signal and a fourth signal, or a combination of the address signal, a fourth signal, and a fifth signal, wherein bits of the fourth signal can override bits of the address signal to increase a number of scan gating devices being enabled, and wherein the fifth signal allows for enabling of directly adjacent scan gating devices. Alternatively, the circuit can further comprise: a configuration register configured to store and provide the first signal to each of the scan gating devices.

[0009] The circuit can further comprise: a selector configured to generate the second signal based on a selection signal and a block on signal and a block off signal, wherein the selection signal defines clock cycles to be blocked, and wherein a combination of the block on signal and the block off signal determines which scan chain output is to be blocked, is not to be blocked, or is to be blocked based on the selection signal.

[0010] The circuit can further include a pseudo-random pattern generator configured to generate a test pattern and a decompressor configured to provide a signal based on which the first signal and the second signal are generated.

[0011] The circuit can further include a comparison device configured to compare an output signal from the test response compressor with a reference signal.

[0012] The circuit can further include a decompressor configured to decompress the compressed test pattern into a test pattern. The decompressor can include a ring generator and a phase shifter.

[0013] Each scan-gating device can include a plurality of sub-units, each of the sub-units including a multiplexer and an AND gate for coupling to each scan chain in the scan chain group of each of the scan-gating devices.

[0014] The test response compressor can include an XOR gate network or an inverter network.

[0015] In another aspect, there is one or more computer-readable media having stored thereon computer-executable instructions for causing one or more processors to perform a method that includes creating a circuit in a circuit design for testing a chip manufactured according to the circuit design.

[0016] Certain inventive aspects are set forth in the appended independent claims and dependent claims. Features from the dependent claims can be combined with those of the independent claims and other dependent claims as appropriate and not just in the specific combinations explicitly set out in the claims.

[0017] Certain objects and advantages of various aspects of the disclosed technology have been described above. Of course, it will be understood that not necessarily all objects or advantages can be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the technology disclosed can be practiced with BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 Programmable computer systems in which various embodiments of the disclosed technology can be implemented are illustrated.

[0019] Figure 2 Examples of test response compression systems in accordance with various embodiments of the disclosed technology are illustrated.

[0020] Figure 3 Examples of scan-gating devices enabled by a first signal are illustrated.

[0021] Figure 4A An example of a scan gating device disabled by a first signal is illustrated that allows passage of test responses captured by scan chains in a group of scan chains based on a third signal.

[0022] Figure 4B An example of a scan gating device disabled by a first signal is illustrated that blocks passage of test responses captured by scan chains in a group of scan chains based on a third signal.

[0023] Figure 5 An example of a block diagram of a scan gating device having circuitry to provide control signals (first signal, second signal, and third signal) according to various embodiments of the disclosed technology is illustrated.

[0024] Figure 6 An example of a configuration insertion bit circuit to control access to a configuration register is illustrated.

[0025] Figure 7 Another example of a block diagram of a scan gating device having circuitry to provide control signals (first signal, second signal, and third signal) according to various embodiments of the disclosed technology is illustrated.

[0026] Figure 8 An example of an address translator according to various embodiments of the disclosed technology is illustrated.

[0027] Figure 9 An example of an address decoder to facilitate simultaneous selection of adjacent scan gating devices is illustrated.

[0028] Figure 10 An example of an address decoder for scan gating devices G k and G k+1 , or G k+1 and G k+2 , or G k+1 , G k+2 and G k+3 using two additional control lines to enable is illustrated.

[0029] Figure 11 An example of a detailed architecture of an address decoder including logic for scan gating devices from G3 to G9 is illustrated.

[0030] Figure 12 An example of a selector configured to generate a second signal according to various embodiments of the disclosed technology is illustrated.

[0031] Figure 13 An example of test compression logic employing a configuration register to provide a first signal to a scan gating device according to various embodiments of the disclosed technology is illustrated.

[0032] Figure 14 Examples of test compression logic employing an address translator to provide a first signal to a scan gating device are illustrated in accordance with various embodiments of the disclosed technology.

[0033] Figure 15 Examples of logic BIST schemes implemented with the disclosed technology are illustrated.

[0034] Figure 16 Examples of architectures for small decompressors to provide signals used to help generate control signals are illustrated. DETAILED DESCRIPTION

[0035] OVERALL CONSIDERATIONS

[0036] Various aspects of the disclosed technology relate to scan selection based X-masking for testing response compression. In the following description, for purposes of explanation, numerous details are set forth. However, one of ordinary skill in the art will realize that the technology disclosed can be practiced without using these particular details. In other instances, well-known features are not described in detail so as not to obscure the technology disclosed.

[0037] Some of the techniques described herein can be implemented in software stored on computer readable media, in software executed on a computer, or in some combination of the two. For example, some of the disclosed techniques can be implemented as a part of an electronic design automation (EDA) tool. These methods can be executed on a single computer or on networked computers.

[0038] Although the operations of the disclosed methods are described in a particular, sequential order for simplicity, it should be understood that the ordering of operations can be modified to suit particular situations, unless specifically stated otherwise. For example, in some situations, multitasking can be used to perform the operations described in a sequential manner. Also, techniques that are described as sequential processes in other processes can be modified to be performed in parallel or in some other manner.

[0039] Detailed descriptions of methods or apparatuses sometimes use terminology that is specific to a single feature of the disclosed methods or apparatuses. This terminology is used to describe a particular feature as opposed to a general feature that can exist in other methods or apparatuses. The terminology used should be understood in a general context and should not be unnecessarily limited to a specific application. The actual operations or features that correspond to this terminology will vary depending on the particular implementation and would be readily recognized by one of ordinary skill in the art.

[0040] Also, as used herein, the term "design" is intended to encompass data that describes an entire integrated circuit device. The term is also intended to encompass smaller sets of data that describe one or more components of an entire device, such as a portion of an integrated circuit device.

[0041] Illustrative operating environment

[0042] Various examples of the disclosed technology can be implemented by the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Figure 1 An illustrative example of a computing device 101 is shown. As shown in this figure, the computing device 101 includes a computing unit 103 having a processing unit 105 and a system memory 107. The processing unit 105 can be any type of programmable electronic device for executing software instructions, but it is typically a microprocessor. The system memory 107 can include read only memory (ROM) 109 and random access memory (RAM) 111. As understood by those of ordinary skill in the art, both the read only memory (ROM) 109 and the random access memory (RAM) 111 can store software instructions for execution by the processing unit 105.

[0043] The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternative communication structure, to one or more peripheral devices. For instance, the processing unit 105 or the system memory 107 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" disk drive 115, a removable disk drive 117, an optical disk drive 119, or a flash memory card 121. The processing unit 105 and the system memory 107 can also be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 can include, for instance, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output devices 125 can include, for instance, a monitor display, a printer, and a speaker. In various examples of the computer 101, one or more of the peripheral devices 115-125 can be housed together with the computing unit 103, inside an internal housing. Alternatively, one or more of the peripheral devices 115-125 can be external to the housing of the computing unit 103 and connected with the bus 113, such as through a universal serial bus (USB) connection.

[0044] In some embodiments, computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices constituting the network. Network interface 127 converts data and control signals from computing unit 103 into network messages according to one or more communication protocols (e.g., Transmission Control Protocol (TCP) and Internet Protocol (IP)). Furthermore, interface 127 may employ any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are known in the art and will not be discussed in detail here.

[0045] It should be understood that computer 101 is merely illustrative and is not intended to be limiting. It may include... Figure 1 The illustrated computer 101 comprises one or more computing devices to implement various embodiments of the disclosed technology, wherein the one or more computing devices include only Figure 1 A subset of the illustrated components, or including those not listed Figure 1 Alternative combinations of the components shown are possible. For example, various embodiments of the disclosed technology may be implemented using a multiprocessor computer, multiple single-processor and / or multiprocessor computers arranged in a network, or some combination of both.

[0046] Used for test design, test pattern generation, and testing.

[0047] The reduction in feature size increases the likelihood of manufacturing defects in integrated circuits leading to faulty chips. Very small defects can result in faulty transistors or faulty interconnects. Even a single faulty transistor or wire can cause the entire chip to malfunction. However, manufacturing defects are unavoidable, whether the manufacturing process is in the prototyping or mass production stage. Therefore, chip testing is essential during manufacturing. Faulty chips also need to be diagnosed to improve throughput and maintain manufacturing yield.

[0048] Testing typically involves applying a set of test stimuli (test patterns) to the circuit under test, and then analyzing the responses generated by the circuit under test. Functional testing attempts to verify that the circuit under test is operating according to its functional specification, while structural testing attempts to determine whether the circuit under test has been correctly assembled from some low-level building blocks as specified in a structural netlist, and that these low-level building blocks and their wiring connections have been manufactured without defects. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should work correctly. Structural testing is widely adopted at least in part because it enables test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements, without having to deal with the exponential explosion of functional states and the multiplicity of state transitions.

[0049] To make it easier to develop and apply test patterns, certain testability features are added to the circuit design, which is referred to as the design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of the internal sequential state elements (latches, flip-flops, etc.) are made controllable and observable in the circuit design through serial interfaces. These functional state elements are often replaced by dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers - for shifting in test patterns and shifting out test responses. Scan cells can operate as originally intended for functional purposes (functional / task mode) and as cells in a scan chain for scanning (scan mode). One widely used type of scan cell includes an edge-triggered flip-flop with a bidirectional multiplexer for data input. The bidirectional multiplexer is typically controlled by a single control signal called scan enable, which selects the input signal for the scan cell from either a scan signal input port or a system signal input port. The scan signal input port is usually connected to the output of another scan cell, while the system signal input port is connected to functional logic. Scan cells can be used as control points and observation points. The control points can be used to set certain logic values at certain locations in the circuit under test to excite (activate) faults and propagate error values to the observation points. Scan testing allows the test equipment to access gates embedded deep through primary inputs / outputs and / or certain physical test points, and can eliminate the need for complex state transition sequences when trying to control or observe what is happening at certain internal circuit elements.

[0050] Test patterns for scan testing are typically generated by an automatic test pattern generation (ATPG) process. ATPG often focuses on a set of faults derived from a gate-level fault model. Defects are defects or physical imperfections introduced in a device during the manufacturing process. A fault model (or simply a fault) is a description of how a defect changes the behavior of a design. For a given target fault, ATPG includes two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site that is opposite to the signal value that results from the fault. Fault propagation propagates the fault effect forward by sensitizing the path from the fault site to a scan cell or primary output. If the test response value captured by a scan cell or primary output is different from the expected value, the fault at the site is said to be detected by the test pattern. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables the tester to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more specific faults. The effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of vectors generated (test pattern count, which should be proportional to the test application time). Here, fault coverage is defined as the ratio of the number of faults detected to the total number of faults.

[0051] The most popular fault model used in practice is the single stuck-at fault model. In this model, it is assumed that one of the signal lines in the circuit is stuck at a fixed logic value, regardless of the inputs provided to the circuit. This stuck-at fault model is a logic fault model, as no delay information is associated with the fault definition. Delay faults cause errors in the operation of a circuit based on their timing. They are caused by the finite rise and fall time periods of signals in gates and the propagation delays of interconnections between gates. Transition faults are used for modeling point defects that affect the delay at the gate input or output due to their simplicity. In scan-based testing, transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Gate-level circuit simulation (analog simulation) can be used to derive intra-cell fault models. This approach can precisely determine the defect location within a cell for various intra-cell defects.

[0052] During the circuit design and manufacturing process, manufacturing test screens out defective chips (dies). However, this test itself does not identify the cause of the observable unacceptably low or fluctuating yield. Physical failure analysis (PFA) can examine the failed chip to locate one or more defect locations and discover the underlying cause. This process typically involves etching away certain layers and then imaging the silicon surface through a scanning electron microscope or focused ion beam system. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnostic (also known as scan diagnostic) is often employed to narrow down the possible location of one or more defects based on analyzing the failure log (fault file, failure file). The failure log typically contains information about when (e.g., tester cycle), where (e.g., on which tester channel), how (e.g., with what logic values) the test failed, and which test patterns generated the expected test responses. Layout information of the circuit design can also be employed to further reduce the number of suspected defects.

[0053] Test application in chip manufacturing test is typically performed by an automatic test equipment (ATE), a tester. Scan-based test consumes a large amount of memory and test time on the ATE. The amount of data increases with the number of logic gates on the chip and also with the number of scan cells. However, practical considerations and ATE specifications often limit the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that needs to be loaded into the ATE and ultimately into the circuit under test. Fortunately, test patterns are compressible, mainly because only 1% to 5% of the test pattern bits are usually specified bits (care bits), while the rest are unspecified bits (don't care bits). The unspecified bits can take any value without affecting the fault coverage. Test compression can also exploit the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern where the don't care bits are not filled in by ATPG. This correlation exists because the faults in the circuit are structurally correlated.

[0054] Various test compression techniques have been developed. Typically, additional on-chip hardware is interposed before and after the scan chains. The hardware added before the scan chains (decompressors) is configured to decompress the test stimuli from the ATE, while the hardware added after the scan chains (compressors) is configured to compress the test responses captured by the scan chains. The decompressors expand the data from n tester channels to fill more than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles required to shift in each test pattern. Thus, test compression not only reduces the amount of data stored in the tester, but also reduces the test time for a given test data bandwidth.

[0055] Embedded deterministic test (EDT) is one example of a test compression technique. EDT-based compression consists of two complementary parts: hardware embedded on the chip, and deterministic ATPG software that generates the compressed patterns that exploit the embedded hardware. The EDT hardware has a continuous stream decompressor. EDT compression of the test cube is performed by processing the external test data as Boolean variables. The scan cells are conceptually filled with symbolic expressions that are linear functions of the input variables injected into the decompressor. In the case where the decompressor includes a ring generator and associated phase shifters, a set of linear equations corresponding to the scan cells whose values are specified can be used. The compressed pattern can be determined by solving the set of equations. If the determined compressed pattern is subsequently scanned in through the decompressor, the bits specified by the ATPG will be generated accordingly. Unspecified bits are set to pseudo-random values based on the decompressor architecture. Further details regarding EDT-based compression and decompression can be found in J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, "Embedded deterministic test," IEEE Trans. CAD, vol. 23, pp. 776-792, May 2004, and in U.S. Patent Nos. 6,327,687; 6,353,842; 6,539,409; 6,543,020; 6,557,129; 6,684,358; 6,708,192; 6,829,740; 6,874,109; 7,093,175; 7,111,209; 7,260,591; 7,263,641; 7,478,296; 7,493,540; 7,500,163; 7,506,232; 7,509,546; 7,523,372; 7,653,851, the entire contents of which are incorporated herein by reference.

[0056] Logic built-in self-test (logic BIST) is a DFT technique that allows a circuit to test itself using embedded test logic without the need for an external tester. Classic logic BIST applications include detecting early-life defectiveness during burn-in testing, enabling the use of low-cost and / or low-speed testers that provide only power and clock signals, and using in-system self-testing to improve system reliability in the aerospace / defense, automotive, telecommunications, and healthcare industries. A typical logic BIST system includes a test pattern generator for automatically generating test patterns, a test response analyzer (compressor) for compressing test responses into signatures, and a logic BIST controller for coordinating BIST operations and for providing pass / fail indications. Pseudo-random pattern generators (PRPGs), i.e., commonly used test pattern generators, can be constructed from linear feedback shift registers (LFSRs) or cellular automata. To improve fault coverage, weighted LFSRs can be employed. Another approach is to combine random test patterns with deterministic patterns in some manner, as BIST logic can be used to process the compressed test patterns that are deterministically generated and stored in the chip.

[0057] All of the above processes, design insertion for testing, test pattern generation, and logic diagnosis are typically performed by various electronic design automation tools such as those in the Tessent family of software tools available from Mentor Graphics Corporation of Wilsonville, Oregon.

[0058] X-masking through low-cost, fine-grained scan selection

[0059] Figure 2An example of a test response compression system 200 according to various embodiments of the disclosed technology is illustrated. The system 200 includes scan chains 210, a test response compressor 230, and scan gating devices 220. The scan chains 210, which include scan cells, are configured to test patterns to shift in test patterns, apply the test patterns to the circuit, capture the test responses of the circuit, and shift out the test responses. The test response compressor 230 is configured to compress the test responses. The test response compressor 230 can be a temporal compressor such as a multiple-input signature register (MISR), a combinational compressor such as an XOR gate network, or a combination of the two. The scan gating devices 220, also referred to as scan strobes, are interposed between the outputs of the scan chains 210 and the inputs of the test response compressor 230. The scan gating devices 220 divide the scan chains 210 into scan chain groups. These scan chain groups can have equal or nearly equal sizes. Each scan gating device 220 receives a signal from the output of one of the scan chain groups and operates in either an enabled mode or a disabled mode based on a first signal 221. In some implementations of the disclosed technology, only one of the scan gating devices 220 operates in the enabled mode. In some other implementations of the disclosed technology, more than one of the scan gating devices 220 can operate in the enabled mode. The scan gating device operating in the enabled mode blocks, blocks only at one or more clock cycles, or does not block a portion of the test responses of the test patterns captured by and output from the scan chains in the scan chain group coupled to the scan gating device operating in the enabled mode based on a second signal 222. The scan gating devices operating in the disabled mode can be configured to not block a portion of the test responses of the test patterns captured by and output from all the scan chains in each of the scan chain groups coupled to the scan gating device operating in the disabled mode. A third signal 223 can be used in conjunction with the first signal 221 to allow the disabled scan gating devices to block or not block the test responses as will be described in detail below. Figure 2

[0060] Figure 3 The scan gating device 340 enabled by the first signal 321 is shown. Based on the second signal 322, the scan gating device 340 passes through the test responses captured by the scan chain 331, blocks the test responses captured by the scan chain 333, and blocks the test responses captured by the scan chain 332 only at certain clock cycles. Thus, the scan chains in the scan chain group 330 coupled to the enabled scan gating device 340 can be divided into three categories: blocked, periodically selectively blocked, and not blocked.

[0061] Also in Figure 3 ​Illustrated is a scan gating device 320 disabled by a first signal 321. Test responses captured by each scan chain in a scan chain group 310 coupled to the scan gating device 320 are allowed to pass through the scan gating device 320. A third signal can be used to allow the disabled scan gating device to either block or not block test responses captured by the associated scan chain group. Figure 4A Illustrated is an example of a scan gating device 410 disabled by a first signal 421 that allows test responses captured by scan chains in a scan chain group 420 to pass based on a third signal 423. Figure 4B Illustrated is an example of the same scan gating device 410 disabled by a first signal 421 that blocks test responses captured by scan chains in a scan chain group 420 from passing based on a third signal 423. This arrangement can enable only scan chains in one group to feed a test response compressor while the remaining scan chains are blocked. This functionality allows very aggressive masking of scan chains, including the scenario of only a single chain being observed.

[0062] As the first signal, second signal, and third signal Figure 2 221-223 in 420-422, Figure 3 321-322 in 310-312) can vary with test patterns, different scan gating devices can be selected as enabled / disabled, and different scan chains in a scan chain group associated with an enabled scan gating device can be blocked or partially blocked for different test patterns. This enables masking of X states within redefinable scan chain groups and specified scan shift cycles.

[0063] It should be noted that scan chains in a scan chain group coupled to an enabled scan gating device need not always be divided into three categories. They can be divided into two categories (e.g., periodically selective blocking + blocked), or based on the second signal all belong to one category (e.g., periodically selective blocking) in some cases.

[0064] Figure 5An example of a block diagram of a scan gating device 500 with a circuit providing control signals (first signal, second signal, and third signal) according to various embodiments of the disclosed technology is illustrated. The scan gating device 500 has a plurality of sub-units. The number of sub-units is equal to the number of scan chains in a scan chain group 530 coupled to the scan gating device 500. Each sub-unit includes an AND gate 510 and a multiplexer 520. One input of the AND gate 510 is coupled to an output of a scan chain in the scan chain group 530. The other input of the AND gate 510 is coupled to an output of the multiplexer 520. A first signal 540 for enabling / disabling the scan gating device 500 provided by a flip-flop 580 of a register is coupled to a select input of the multiplexer 520. Two inputs of the multiplexer 520 are coupled to a second signal 560 and a third signal 550, respectively. The second signal 560 is generated by a selector 570 and has different signal lines for different scan chains in the scan chain group 530. When the first signal 540 is asserted (“1”), the scan gating device 500 is enabled, and the output of each scan chain in the scan chain group 530 is controlled by one of the signal lines of the second signal 560. The output of a scan chain can be blocked, unblocked, blocked at selective clock cycles according to a particular signal line. When the first signal 540 is not asserted (“0”), the scan gating device 500 is disabled, and all scan chains in the scan chain group 530 are controlled by the third signal 550. Depending on whether the third signal 550 is asserted or not, the outputs of all scan chains are blocked or unblocked.

[0065] The register (also referred to as a configuration register) including the flip-flop 630 can be occasionally reloaded, as the same content can typically be used for several test patterns in a row. It can be isolated behind a configuration insertion bit (CIB) 610, as Figure 6The configuration insertion bit 610 is deployed to allow on-demand access to the configuration register 620 and to interface the same register with a single ATE input channel. If the flip-flop 630 outputs a 0, the CBI 610 is set to bypass the configuration register 620 and only allow the other registers connected in a daisy chain to be updated. In this mode, the configuration register 620 is not affected by any data transfers due to the clock gating 640. Once in effect, the flip-flop 630 routes the additional test data to the configuration register while enabling the clock signal to facilitate the shift register functionality of the configuration register. A shift path is then established from the ATE input channel through some registers, if any, to the configuration register and then through some other registers, if any, back to the decompressor. All changes in the state of the flip-flop 630 are accomplished by the CIB enable input that captures the first control bit of the input sequence. This bit indicates whether the following sequence is to update the X-mask logic configuration or is just the new contents of another register.

[0066] Figure 7 Another example of a block diagram of a scan gating device 700 having circuitry to provide control signals (first signal, second signal, and third signal) is illustrated in accordance with various embodiments of the disclosed technology. Similar to the scan gating device 500 in Figure 5 Figure 5 Figure 5 Figure 7 The difference between the setup in and is that the first signal 750 is not provided from a flip-flop but from an address decoder 740. Here, the address decoder 740 is essentially a AND gate that takes the outputs of the address translator 720 as its inputs and translates the inputs into the first signal 750. The address decoder 740 for the scan gating device 700 typically uses a combination of the outputs of the address translator 720 that is different from the outputs used by the address decoder for another scan gating device.

[0067] If the address bit A* (set 770 of outputs of the address translator 720) is considered the inverse of the address bit A (set 780 of other outputs of the address translator 720), the address decoder (like the address decoder 740) ensures that only one scan gating device can be enabled at a time. To enable two or more scan gating devices at the same time, the address translator can use another signal, like Figure 8 ​​​The illustrated address translator 800 receives a regular binary encoded address A (810) and stores it in an address register 830. In addition, the address translator 800 receives the same amount of dominance bits D (820) and stores them at a dominance bit register 840. The dominance bits D (820) indicate which address bits and their inverses should be replaced by a logical value of 1. In other words, the content of the dominance bit register 840 can override any address bit if needed. For example, if at the input of the address translator 800 A i = 1 and D i = 0, then at the output of the address translator 800 A i = 1 and A i * = 0. However, the active (1) level of D i will set both bits A i and A i * to 1 at the output of the address translator 800. As a result, as long as two scan gate devices decode two addresses that only differ on bit i (set to 0 and 1, respectively), both scan gate devices will be enabled at the same time. Using the address translator 800, each group of scan gate devices can be enabled by activating the corresponding bit of the dominance bit register 840. The number of enabled scan gate devices will be equal to a power of 2. Setting all dominance bits to 1 enables all scan gate devices. In this case, it now depends on the second signal output from a selector (e.g., selector 730) to decide which scan chains to mask.

[0068] Figure 8 The illustrated address translator 800 facilitates the simultaneous selection of several scan gate devices with a granularity determined by the dominance control bits 820. However, certain combinations of scan gate devices and their associated groups of scan chains cannot be enabled at the same time. For example, the address bits A = 00001 and the dominance bits D = 00010 allow the selection of scan gate devices G1 and G3, but it is not possible to enable scan gate device G2 at the same time as G1 and G3 unless by selecting A = 00000 and setting the two least significant dominance bits (i.e., D = 00011) such that scan gate device G0 is also included.

[0069] Figure 9 An example of an address decoder G A (940) is illustrated that overcomes the above-mentioned drawbacks and makes the selection of scan gate devices more flexible. In addition to an address AND gate 930 that generates unique signals 920 based on the address variables and their inverses (as described above Figure 7 ), the address decoder G A (940) has three additional control lines N 3-1(950) driven two-input AND gates 931, 932 and 933, and the outputs of the address AND gates from the three address decoders coupled to the three preceding scan gating devices G A-1 , G A-2 and G A-3 (assuming the scan gating devices are connected in series). Thus, G A-1 is enabled as long as the corresponding control line N1 is asserted. A G A-2 or G A-3 may be enabled if line N2 or line N3, respectively, is set to 1. A .

[0070] Figure 8 The address translator 800 shown can be redesigned in such a way that the lines N3N2N1 can only assume one of the following combinations: 000, 001, 011 or 111. Figure 10 An example of such an address decoder 1000 is illustrated. Here, two additional control lines 1010 are used to generate the signals N3, N2 and N1. Thus, a given scan gating device G k may be enabled in parallel with G k+1 , or G k+1 and G k+2 , or G k+1 , G k+2 and G k+3 .

[0071] For example, to enable G0, G1 and G2, G0 can be selected and the two control lines 1010 used to enable the adjacent scan gating devices are set to the value 10. This results in the control signals N3N2N1 = 011 that enable both G1 and G2. The detailed architecture of the address decoder is illustrated in Figure 11 , which includes the address decoding logic for the scan gating devices from G3 to G9 (the remaining part of the decoder, not shown in the figure, can be designed in a similar way). It can be seen that the main address decoding AND gate drivers are located in the corresponding two-input AND gates (indicated by the same symbol) in the subsequent three scan gating devices. The disclosed technology can easily cover any neighborhood of a given scan gating device in terms of blocking its adjacent modules at the cost of additional two-input AND gates and control data.

[0072] Figure 12 An example of a selector configured to generate a second signal according to various embodiments of the disclosed technology is illustrated. The second signal determines which scan chains in a group of scan chains coupled to the enabled scan gating device should be masked. Figure 12The illustrated selector architecture assumes that each group consists of eight scan chains. There are two groups of selector inputs. The inputs denoted S* (1210) are used to individually gate the respective scan chains in each period mode, unless the contents of the configuration registers B-off (1220) and B-on (1230) dictate otherwise. These registers are typically reloaded once per mode or mode group, with the exception of the blocking inputs B (here 16 inputs) (1240). As can be seen, each scan chain is assigned a pair of configuration control bits that determine the masking state of that scan chain, as follows. If the bits b k of register 1220 and register 1230 are both set to 0, then scan chain k is unconditionally blocked throughout the scan unload period (selector output k is set to 0). Setting the bits b k of register B-on (1230) to 1 and the corresponding bits of register B-off (1220) to 0 makes scan chain k fully observable. Finally, the bits b k of B-on (1230) are set to 0 and the corresponding bits of B-off (1220) are set to 1, as required by the current state of input S* k to allow masked scan chain k. The above is summarized in table 1250 in Figure 12

[0073] Figure 13 An example of test compression logic employing configuration registers to provide a first signal to a scan gating device is illustrated in accordance with various embodiments of the disclosed technology. Scan gating device 1310 is located between the scan chain outputs and test response compactor 1320 and divides the scan chains into almost equal sized groups of scan chains 1350. Based on control signals (first signal, second signal, and third signal), scan gating device 1310 selectively blocks test results from the chains within each group from entering test response compactor 1320 before the test results can enter test response compactor 1320. The first signal is provided by configuration register 1330. Similar to configuration insertion bit device 1380 shown in Figure 6 , control of whether to load / update configuration register 1330. The second signal is provided by selector 1340. Similar to selector 1340 shown in Figure 12 , selector 1340 generates the second signal based on B-on and B-off signals provided by B register 1390 and a select signal from test data decompressor 1360. The third signal is provided by two auxiliary buffers 1373 and 1375. One of the auxiliary buffers 1375 is used as a shadow register that allows saving the particular control while being reloaded with its new value in parallel with the shift-in of the next test mode. Similar buffering techniques can be applied to the select data. The shadow register for selector 1340 can be as in Figure 12 ​Part of the selector shown. The main input registers 1373, 1380, and 1390 are daisy-chained, allowing them to be updated via the regular ATE channel used to pass data to the decompressor 1360.

[0074] Figure 14 Examples of test compression logic according to various embodiments of the disclosed technology are illustrated, which employs an address converter to provide a first signal to the scanning gating device. Apart from two differences, Figure 14 The test compression logic shown is Figure 13 The test compression logic shown is similar. The first difference is... Figure 14 The test compression logic shown employs an address converter 1420 and a series of address decoders (not shown), instead of configuration registers, to provide a first signal to the scan gating device 1410. The address converter 1420 is similar to... Figure 8 The address converter shown generates address output bits based on the address bits provided by address register 1440 and the dominance bit provided by dominance bit register 1430. Similarly, the main input registers including 1430 and 1440 are daisy-chained, allowing the main input registers including 1430 and 1440 to be updated via the standard ATE channel used to pass data to the decompressor. It should be noted that other types of address converters can also be used, such as... Figure 10 The address converter shown.

[0075] Figure 13 and Figure 14 The second difference is Figure 14 The test compression logic includes a comparison device 1450 and a paste bit device 1460. The disclosed technique, instead of scanning the output test results and processing them with an external tester, allows for easy on-chip comparison of the actual test response with the expected test response. Therefore, it is possible to use... Figure 14 The comparison device 1450 shown is used instead of the output ATE channel. Here, the additional stream R of reference data is compared (XORed) with the output stream leaving the test response compressor, and if any difference is detected, it is latched as a value 1 by the paste bit device 1460.

[0076] Figure 15 An example of a logical BIST scheme implemented using the disclosed technique is illustrated. Since the scan chain 1510 is fed with a pseudo-random pattern generated by the pseudo-random pattern generator (PRPG) 1520, the selector 1540 cannot select from the test pattern (such as...). Figure 14The source of each cycle of data is received by the small decompressor 1530 (in this case, the test mode) in addition to the data comprising the contents of the address (A), dominance (D), block (B), and E registers. Thus, in addition to the data comprising the contents of the address (A), dominance (D), block (B), and E registers, the seed (S) of the small decompressor 1530 is provided by the same input used to seed the PRPG 1520, which produces the actual selector inputs on a per-cycle basis. The compressor in this example comprises combinational logic (e.g., an XOR network) 1560 and a MISR 1550.

[0077] Figure 16 An example of the architecture of the small decompressor 1530 is illustrated. In addition to the ring generator 1610 and the phase shifter 1630 that drives the selector inputs, a holding register 1620 is provided between these two devices. This holding register 1620 captures certain states of the ring generator 1610 while the generator 1610 continues to the next state required to decode another set of selection bits. As a result, a given small decompressor state can be repeated and passed to the selector 1540 for multiple consecutive scan shift cycles. The small decompressor 1530 also accommodates a small ring template register 1640 that provides control bits to the holding register on each scan shift cycle to indicate whether the register should be reloaded with the current contents of the ring generator 1610. Because of the very same short template size, the very same short template is typically used multiple times within the duration of the same test mode.

[0078] The small decompressor 1530 is able to decode selection patterns (multi-dimensional cubes) with additional reload points (which appear as 1's in the template register 1640) and indicate the appropriate time with respect to when to update the holding register. Notably, similar to EDT-based compression, the selection solver assumes that the same equation is associated with all selection bits covered by a given holding period. As a result, if there is at least one designated bit within a period, the first selection bit of the period becomes the subject of encoding. As experimental results show, (on average) up to 50% of designated bits are typically handled by a constant value of the holding period rather than by direct encoding, thereby ensuring high encoding efficiency.

[0079] CONCLUSION

[0080] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from the principles of the technology. Because many possible modifications can be made to the principles of the technology described herein, many such further implementations will be apparent to those skilled in the art in light of this disclosure. Therefore, it will be appreciated that the scope of the technology disclosed herein is not limited to the specific embodiments described and that modifications and / or substitutions can be made without departing from the scope and spirit of the technology. Accordingly, we intend that the technology disclosed herein be limited only by the claims and their equivalents.

Claims

1. A circuit comprising: a scan chain comprising scan cells, the scan chain configured to shift in a test pattern, apply the test pattern to the circuit, capture a test response of the circuit, and shift out the test response; a test response compactor configured to compress the test response; and a scan gating device interposed between an output of the scan chain and an input of the test response compactor, the scan gating device dividing the scan chain into a group of scan chains, each of the scan gating device receiving a signal from an output of one of the group of scan chains and operating in an enable mode or a disable mode based on a first signal, wherein a portion of the test response of a test pattern output from each of the scan chains coupled to the scan gating device operating in the enable mode is blocked from reaching the test response compactor based on a particular bit of a second signal, blocked from reaching the test response compactor at one or more clock cycles only, or not blocked from reaching the test response compactor, at least a portion of the second signal being passed continuously bit by bit when the test pattern is shifted out, and wherein another portion of the test response of the test pattern output from all of the scan chains in each of the group of scan chains coupled to the scan gating device operating in the disable mode is blocked or not blocked from reaching the test response compactor based on a third signal.

2. The circuit of claim 1, further comprising: an address translation and decoding circuit configured to generate the first signal based on an address signal, or a combination of the address signal and a fourth signal, or a combination of the address signal, a fourth signal, and a fifth signal, wherein bits of the fourth signal can override bits of the address signal to increase a number of scan gating devices being enabled, and wherein the fifth signal allows for enabling of a direct neighbor scan gating device.

3. The circuit of claim 1, further comprising: a configuration register configured to store the first signal and provide the first signal to each of the scan gating devices.

4. The circuit of claim 1, further comprising: a selector configured to generate the second signal based on a select signal and a block enable signal and a block disable signal, wherein the select signal defines a clock cycle to be blocked, and wherein a combination of the block enable signal and the block disable signal determines which scan chain output is to be blocked, not to be blocked, or to be blocked based on the select signal.

5. The circuit of claim 1, further comprising: a pseudo-random pattern generator configured to generate a test pattern; and a decompressor configured to provide a signal based on which the first signal and the second signal are generated.

6. The circuit of claim 1, further comprising: a comparison device configured to compare an output signal from the test response compactor to a reference signal.

7. The circuit of claim 1, further comprising: a decompressor configured to decompress a compressed test pattern into the test pattern. ​ ​ 8. The circuit of claim 7, wherein, The decompressor includes ring generators and phase shifters.

9. The circuit of claim 1, wherein, a plurality of sub-units, each of the sub-units including a multiplexer for coupling to each scan chain of the scan chain group of each of the scan gating devices and an AND gate.

10. The circuit of claim 1, wherein, The test response compressor includes an XOR gate network or an inverter network.

11. One or more computer-readable media having stored thereon computer- executable instructions for causing a computer to perform a method comprising: creating a circuit in a circuit design for testing a chip manufactured according to the circuit design, the circuit including: a scan chain including scan cells, the scan chain configured to shift into a test mode, apply the test mode to the circuit, capture a test response of the circuit, and shift out the test response; a test response compressor configured to compress the test response; and scan gating devices interposed between an output of the scan chain and an input of the test response compressor, the scan gating devices dividing the scan chain into scan chain groups, each of the scan gating devices receiving a signal from an output of one of the scan chain groups and operating in an enable mode or a disable mode based on a first signal, wherein a portion of the test response of a test mode output from each of the scan chains coupled to the scan gating devices operating in the enable mode is blocked from reaching the test response compressor based on a particular bit of a second signal, is blocked only at one or more clock cycles, or is not blocked, at least a portion of the second signal being continuously passed bit by bit when the test mode is shifted out, and wherein another portion of the test response of the test mode output from all of the scan chains in each of the scan chain groups coupled to the scan gating devices operating in the disable mode is blocked or not blocked from reaching the test response compressor based on a third signal.

12. The one or more computer-readable media of claim 11, wherein, The circuit further includes: address translation and decoding circuitry configured to generate the first signal based on an address signal, or a combination of the address signal and a fourth signal, or a combination of the address signal, a fourth signal, and a fifth signal, wherein bits of the fourth signal can override bits of the address signal to increase a number of scan gating devices being enabled, and wherein the fifth signal allows for enabling of a direct neighbor scan gating device of a scan gating device.

13. The one or more computer-readable media of claim 11, wherein, The circuit further includes: configuration registers configured to store the first signal and provide the first signal to each of the scan gating devices.

14. The one or more computer-readable media of claim 11, wherein, The circuit further includes: a selector configured to generate the second signal based on a select signal and a block enable signal and a block disable signal, wherein the select signal defines a clock cycle to be blocked, and wherein a combination of the block enable signal and the block disable signal determines which scan chain output is to be blocked, is to not be blocked, or is to be blocked based on the select signal.

15. The one or more computer-readable media of claim 11, wherein, The circuit further includes: a pseudo-random pattern generator configured to generate a test mode; and a selector configured to generate the second signal based on a select signal and a block enable signal and a block disable signal, wherein the select signal defines a clock cycle to be blocked, and wherein a combination of the block enable signal and the block disable signal determines which scan chain output is to be blocked, is to not be blocked, or is to be blocked based on the select signal. a decompressor configured to provide a signal, the first signal and the second signal being generated based at least on the provided signal.

16. The one or more computer-readable media of claim 11, wherein, The circuit further comprises: a comparison device configured to compare an output signal from the test response compressor with a reference signal.

17. The one or more computer-readable media of claim 11, wherein, The circuit further comprises: a decompressor configured to decompress the compressed test pattern into the test pattern.

18. The one or more computer-readable media of claim 17, wherein, The decompressor comprises a ring generator and a phase shifter.

19. The one or more computer-readable media of claim 11, wherein, a plurality of sub-units, each of the sub-units comprising a multiplexer for coupling to each scan chain of the scan chain group of each of the scan gated devices and an AND gate.

20. The one or more computer-readable media of claim 11, wherein, The test response compressor comprises an XOR gate network or an inverter network.

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