A FPGA circuit fault injection method and IP core

Abstract

This invention relates to the fields of aerospace technology and FPGA circuit single-event effect evaluation technology, and particularly to an FPGA circuit fault injection method and its IP core. The IP core includes: a serial data transceiver module and a data protocol parsing module, a register module, a fault set storage module, a single-frame reconstruction instruction storage module, a load set storage module, a read-back set storage module, a FLASH interface control module, a JTAG interface control module, and a DUT interface control module. The FPGA circuit fault injection method and its IP core provided by this invention have strong compatibility, are applicable to fault injection of various types of FPGA chips, support bit-by-bit injection mode and cumulative injection mode, support multiple fault types, and have a flexible and convenient DUT interface.

Description

Technical Field

[0001] The present invention relates to the field of aerospace technology and FPGA circuit single particle effect evaluation technology, and in particular to an FPGA circuit fault injection method and an IP core thereof. Background Art

[0002] FPGA (Field Programmable Gate Array) is the core signal processing device of aerospace electronic systems and is widely used in various payloads and platform units in spacecraft. Since FPGA contains a large number of information storage units, it is extremely susceptible to the space radiation environment, and single-particle flipping occurs, which is one of the main causes of satellite system failures. At present, the single-particle irradiation test relies solely on ground-based heavy ion accelerators, which is limited by the serious shortage of irradiation test time, resulting in "bottleneck" problems such as long FPGA circuit reliability evaluation cycle and high cost. Therefore, it is necessary to study the simulation evaluation test method and device of the single-particle flip effect of FPGA circuit system in space, and provide a means to quickly and effectively analyze its space reliability.

[0003] Fault injection is a means of simulating single-particle effects. Without damaging the device, it can quickly simulate the impact of different radiation test environments on the reliability of FPGA circuit systems, replacing ground-based single-particle irradiation tests. The single-particle effect simulation evaluation method based on fault injection is suitable for reliability analysis in the design stage. It can be used to evaluate the effectiveness of circuit reinforcement effects at the design site and estimate the system's on-orbit functional interruption rate. This evaluation method does not damage the system hardware, and can reduce the cost of irradiation testing and improve system design efficiency.

[0004] The existing fault injection technology solution is roughly as follows: the PC completes the injection mode selection, fault type selection, and generates the corresponding fault code stream file, downloads the configuration file and injection command to the main control FPGA through the communication interface, and collects the commands and data returned by the main control FPGA. That is, the PC controls the entire fault injection process and is the control core of the entire fault injection system.

[0005] At present, the existing fault injection algorithm modules have three main shortcomings: first, the fault injection algorithm modules are not universal and cannot be compatible with different series of FPGA chips; second, the injection mode and fault type of the fault injection algorithm modules are single, which cannot meet the rapid evaluation under different radiation environments and evaluation requirements; third, the fault injection algorithm modules are designed for specific DUTs and cannot be compatible with complex and changeable DUT interface protocols. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing FPGA circuit fault injection method, such as lack of versatility, single injection mode and fault type, and incompatibility with complex and changeable DUT interface protocols, thereby proposing an FPGA circuit fault injection method and an IP core thereof; the present invention, through an improved fault injection algorithm and the selection of a suitable hardware structure, only needs to perform parameterized configuration, can achieve compatibility with different series of FPGA chips, support multiple injection modes and fault types, and be compatible with complex and changeable DUT interface protocols, and is an FPGA circuit fault injection IP core for aerospace payload engineering applications.

[0007] In order to solve the above technical problems, the FPGA circuit fault injection method provided by the technical solution of the present invention comprises the following steps:

[0008] Step 1) determining the fault injection mode stored in the fault set storage module through the JTAG interface control module, and if the fault injection mode is a bit-by-bit injection mode, executing step 2), and if the fault injection mode is a cumulative injection mode, executing step 3); wherein the bit-by-bit injection mode indicates a fault that needs to be repaired, and the cumulative injection mode indicates a fault that does not need to be repaired;

[0009] Step 2) repairing the fault of the FPGA to be tested by reconfiguring the FPGA through the JTAG interface control module to ensure the authenticity of the fault injection effect, and then executing step 3);

[0010] Step 3) injecting faults into the FPGA to be tested by the JTAG interface control module in a single frame reconstruction mode, and then proceeding to step 4);

[0011] Step 4) determining whether the fault grouping in the current fault point information is a fault of a different group through the JTAG interface control module; if the fault grouping in the current fault point information is a fault of a different group, executing step 5); otherwise, executing step 3), wherein the fault of a different group is that the current fault point and the next fault point are not faults of the same group;

[0012] Step 5) through the JTAG interface control module, control the DUT interface control module to read M data from the load set storage module as DUT input stimulus; sequentially load the DUT input stimulus to the DUT, and start counting, when the count value reaches N, the DUT interface control module automatically stores and uploads X monitoring output data of the DUT to the read back set storage module for storage; wherein M is the value in the DUT operation cycle register of the register module, N is the value in the DUT monitoring start register of the register module, and X is the value in the DUT monitoring cycle register of the register module;

[0013] Step 6) determining, through the JTAG interface control module, whether the fault point in the current fault point information is the last fault point in the known fault set, if yes, executing step 7), otherwise, executing step 1);

[0014] Step 7) Fault injection is completed.

[0015] As an improvement of the above method, the step 2) specifically includes:

[0016] Step 2-1) Control the JTAG interface timing through the JTAG interface control module, so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state;

[0017] Step 2-2) sequentially loading JPROG_B and CFG_IN instructions through the JTAG interface control module to make the TAP controller enter the Shift-DR state;

[0018] Step 2-3) Controlling the FLASH interface control module through the JTAG interface control module, so that the FLASH interface control module reads the configuration code stream data from the external FLASH device, and writes the configuration code stream data into the FPGA in the Shift-DR state to perform FPGA reconfiguration;

[0019] Step 2-4) Loading the JSTART instruction through the JTAG interface control module to start the FPGA function operation;

[0020] Step 2-5) Control the JTAG interface timing through the JTAG interface control module to make the TAP controller enter the Test-Logic-Reset state.

[0021] As an improvement of the above method, the step 3) specifically includes:

[0022] Step 3-1) reading a fault point information from the fault set storage module through the JTAG interface control module; wherein the fault point information includes: fault frame address, fault word, fault bit, fault group and Flash read address;

[0023] Step 3-2) Controlling the JTAG interface timing by the JTAG interface control module, so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state;

[0024] Step 3-3) Loading the CFG_IN instruction through the JTAG interface control module to make the TAP controller enter the Shift-DR state;

[0025] Step 3-4) reading the header command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module through the JTAG interface control module; and replacing the frame address in the header command with the fault frame address in the fault point information; the JTAG interface control module writes the replaced header command into the FPGA in the Shift-DR state;

[0026] Step 3-5) Controlling the FLASH interface control module through the JTAG interface control module, taking the Flash read address in the fault point information as the starting address, and reading the fault frame data from the external FLASH device, wherein the fault frame data includes G bytes, and each byte of the fault frame data is represented by FLASH[i]; i represents the i-th byte, and the value range is 0 to G-1;

[0027] If the i-th byte of fault frame data FLASH[i] is the fault word in the fault point information, the i-th byte of fault frame data FLASH[i] is XORed with the fault bit in the fault point information by using the JTAG interface control module and then written into the FPGA;

[0028] Otherwise, the fault frame data FLASH[i] of the i-th byte is directly written into the FPGA;

[0029] Step 3-6) reading the tail command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module through the JTAG interface control module, and writing it into the FPGA in the Shift-DR state through the JTAG interface control module to perform FPGA single-frame fault injection;

[0030] Step 3-7) Control the JTAG interface timing through the JTAG interface control module to make the TAP controller enter the Test-Logic-Reset state.

[0031] To achieve another object of the present invention, the present invention provides an IP core for FPGA circuit fault injection, which executes the above method, and the IP core includes: a serial data transceiver module, a data protocol parsing module, a register module, a single frame reconstruction instruction storage module, a fault set storage module, a load set storage module, a readback set storage module, a FLASH interface control module, a JTAG interface control module and a DUT interface control module; wherein,

[0032] The register module is used to store register information;

[0033] The single frame reconstruction instruction storage module is used to store a single frame reconstruction data packet;

[0034] The fault set storage module is used to store fault point information; wherein the fault point information includes: fault frame address, fault word, fault bit, fault group and Flash read address;

[0035] The load set storage module is used to store DUT input stimulus;

[0036] The read-back set storage module is used to store DUT monitoring output data;

[0037] The FLASH interface control module is used to write and read the FLASH memory based on the control of the JTAG interface control module;

[0038] The JTAG interface control module is used to determine the fault injection mode stored in the fault set storage module; to repair the fault of the FPGA to be tested by using the FPGA reconfiguration method; to inject faults into the FPGA to be tested by using a single frame reconstruction method; to determine whether the fault group in the current fault point information is a non-same group fault; to determine whether the fault point in the current fault point information is the last fault point in the known fault set;

[0039] The DUT interface control module, based on the control of the JTAG interface control module, is used to read data from the load set storage module as DUT input stimulus; load the DUT input stimulus to the DUT in turn, and is used to automatically store and upload the DUT monitoring output data to the read back set storage module for storage.

[0040] As an improvement of the above system, the register module includes: a configuration code stream length register, a configuration array length register, a configuration frame length register, a readback command packet header length register, a readback command packet tail length register, a readback data delay period register, a readback start position register, a single frame reconstruction command packet header length register, a single frame reconstruction command packet tail length register, an injection mode register, a fault point information length register, a JTAG scan instruction bit register, a CFG_IN instruction register, a CFG_OUT instruction register, a JPROG_B instruction register, a JSTART instruction register, a DUT operation cycle register, a DUT monitoring start register and a DUT monitoring cycle register, which are shared by the JTAG interface control module and the DUT interface control module.

[0041] As an improvement of the above system, the DUT interface control module, based on the control of the JTAG interface control module, is used to read M data from the load set storage module as DUT input stimulus; load the DUT input stimulus to the DUT in turn, and start counting; when the value of the count reaches N, the DUT interface control module is used to automatically store and upload X DUT monitoring output data to the read back set storage module for storage; wherein M is the value in the DUT operation cycle register of the register module, N is the value in the DUT monitoring start register of the register module, and X is the value in the DUT monitoring cycle register of the register module; the DUT interface control module is also used to provide clock input and reset signals for the DUT.

[0042] As an improvement of the above system, the fault frame address in the fault point information is an address stored in the FAR frame address register of the FPGA to be tested;

[0043] The fault bit of the fault point information indicates a bit in the fault word where a fault is injected or not injected, wherein a fault bit of 1 represents that a fault is injected, and a fault bit of 0 represents that a fault is not injected;

[0044] In the fault grouping of the fault point information, 00 is used to represent faults that are not in the same group, and FF is used to represent faults in the same group;

[0045] The Flash read address of the fault point information is the starting address of the fault frame data in the external FLASH device.

[0046] As an improvement of the above system, the single frame reconstruction instruction storage module adopts a simple dual-port RAM of 512*8 bits;

[0047] The load set storage module adopts a simple dual-port RAM of 64K*8 bits;

[0048] The read-back set storage module adopts a 1K*8-bit standard FIFO;

[0049] The FLASH interface control module adopts a 64M*16-bit universal parallel interface FLASH;

[0050] The register module uses register groups of different lengths.

[0051] As an improvement of the above system, the JTAG interface control module is used to repair the fault of the FPGA to be tested in the bit-by-bit injection mode by using the FPGA reconfiguration method, specifically including:

[0052] The JTAG interface control module is used to control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; is used to load the JPROG_B and CFG_IN instructions in sequence so that the TAP controller enters the Shift-DR state; is used to control the FLASH interface control module so that the FLASH interface control module reads the configuration code stream data from the external FLASH device and writes the configuration code stream data into the FPGA in the Shift-DR state to perform FPGA reconfiguration; is used to load the JSTART instruction to start the FPGA function operation; is used to control the JTAG interface timing so that the TAP controller enters the Test-Logic-Reset state.

[0053] As an improvement of the above system, the JTAG interface control module is used to inject faults into the FPGA to be tested by using a single frame reconstruction method, specifically including:

[0054] The JTAG interface control module is used to read a fault point information from the fault set storage module; to control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; to load the CFG_IN instruction so that the TAP controller enters the Shift-DR state; to read the header command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module; to replace the frame address in the header command with the fault frame address in the fault point information; to write the replaced header command into the FPGA in the Shift-DR state; to control the FLASH interface control module, using the Flash read address in the fault point information as the starting address, to read the fault frame data from the external FLASH device, wherein the fault frame data includes G bytes, and each byte of the fault frame data is represented by FLASH[i]; i represents the i-th byte, and the value range is 0 to G-1;

[0055] If the i-th byte of fault frame data FLASH[i] is the fault word in the fault point information, the JTAG interface control module is used to write the i-th byte of fault frame data FLASH[i] into the FPGA after performing an XOR operation with the fault bit in the fault point information; otherwise, the JTAG interface control module is used to directly write the i-th byte of fault frame data FLASH[i] into the FPGA;

[0056] The JTAG interface control module is also used to read the tail command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module, and write it into the FPGA in the Shift-DR state to perform FPGA single-frame fault injection; and is used to control the JTAG interface timing to enable the TAP controller to enter the Test-Logic-Reset state.

[0057] The FPGA circuit fault injection method and IP core of the present invention have the following advantages:

[0058] 1. The present invention stores the single-frame reconstruction instructions for fault injection into the FPGA to be tested separately, and can achieve compatibility with fault injection into different series of FPGA chips by transmitting different reconstruction instructions. The compatibility is strong, and fault injection into SRAM-type FPGA chips of Xilinx's V2, V4, V5, V6, V7, K7 and A7 series can be achieved;

[0059] 2. The FPGA reconfiguration method of the present invention repairs the fault of the FPGA to be tested and can support two injection modes, including: a bit-by-bit injection mode and a cumulative injection mode;

[0060] 3. The present invention adopts a single-frame reconstruction method to inject faults into the FPGA under test, and can support multiple fault types; for example, single-bit and multi-bit (same frame, physically adjacent frames, and any physically non-adjacent frames) fault types;

[0061] 4. The timing of the DUT interface control module in the present invention is presented by the IP in the form of counting, which has nothing to do with whether the DUT interface is connected. Therefore, the DUT interface is flexible. In actual use, the DUT interface of the IP core can be left floating or connected to the input / output of the FPGA circuit to be monitored, which is convenient to use and flexible to monitor.

[0062] 5. As long as the external interface of the IP core has a serial port and a CFI interface FLASH, it can be transplanted by Verilog. Therefore, the IP core provided by the present invention has the characteristics of strong portability and can be transplanted to any FPGA development board with a serial port and a CFI interface FLASH. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A structural diagram of the FPGA circuit fault injection IP core of the present invention;

[0064] Figure 2 A state transition diagram of a data protocol parsing module in an FPGA circuit fault injection IP core of the present invention;

[0065] Figure 3 A state transition diagram of a JTAG interface control module in an FPGA circuit fault injection IP core of the present invention;

[0066] Figure 4 It is a timing diagram of the DUT interface control module in the FPGA circuit fault injection IP core of the present invention;

[0067] Figure 5 It is a schematic diagram of transplanting the FPGA circuit fault injection IP core of the present invention into a development board. DETAILED DESCRIPTION

[0068] The technical solution provided by the present invention is further illustrated below in conjunction with embodiments.

[0069] The invention discloses an FPGA circuit fault injection method and an IP core thereof, and relates to the technical field of single particle effect evaluation of SRAM type FPGA circuits; the technical problems to be solved are that the FPGA circuit fault injection method and the IP core are not compatible with different series of FPGA devices, do not support multiple fault injection modes and fault types, and cannot cope with complex and changeable DUT interface protocols; the IP core for running the FPGA circuit fault injection method comprises a serial data transceiver module, a data protocol parsing module, a register module, a fault set storage module, a single frame reconstruction instruction storage module, a load set storage module, a readback set storage module, a FLASH interface control module, a JTAG interface control module and a DUT interface control module;

[0070] Among them, the serial data transceiver module is connected to the data protocol analysis module and the read back set storage module; the data protocol analysis module is connected to the register module, the single frame reconstruction instruction storage module, the fault set storage module, the load set storage module, the FLASH interface control module and the JTAG interface control module; the JTAG interface control module is also connected to the FLASH interface control module, the register module, the single frame reconstruction instruction storage module, the fault set storage module and the DUT interface control module; the DUT interface control module is also connected to the register module, the load set storage module and the read back set storage module;; the IP core of the present invention has a parameterized configuration function, which can realize fault injection into different series of FPGA chips of Xilinx company; through an improved fault injection algorithm and the selection of a suitable hardware structure, the injection and functional monitoring of different fault injection modes and fault types of FPGA circuits can be realized; the IP core designed by Verilog HDL language can realize the transplantation of different FPGAs.

[0071] The following is a further detailed description of an embodiment of the present invention in conjunction with the accompanying drawings, but this embodiment is not intended to limit the present invention. All similar structures, methods and similar variations of the present invention should be included in the protection scope of the present invention.

[0072] This embodiment provides an FPGA circuit fault injection IP core for aerospace payload engineering applications, which is compatible with different series of FPGA devices, supports multiple injection modes and fault types, and is compatible with complex and changeable DUT interface protocols, thereby realizing fault injection and monitoring of FPGA circuits.

[0073] like Figure 1 As shown, the IP core includes: a serial data transceiver module, a data protocol parsing module, a register module, a single frame reconstruction instruction storage module, a fault set storage module, a load set storage module, a read back set storage module, a FLASH interface control module, a JTAG interface control module and a DUT interface control module; wherein the serial data transceiver module is respectively connected to the data protocol parsing module and the read back set storage module; the data protocol parsing module is respectively connected to the register module, the single frame reconstruction instruction storage module, the fault set storage module, the load set storage module, the FLASH interface control module and the JTAG interface control module; the JTAG interface control module is respectively connected to the FLASH interface control module, the register module, the single frame reconstruction instruction storage module, the fault set storage module and the DUT interface control module; the DUT interface control module is respectively connected to the register module, the load set storage module and the read back set storage module;

[0074] The various functional modules in the present invention are further described below.

[0075] The serial data transceiver module is used to connect the FPGA circuit fault injection IP core of the present invention to an external serial port transceiver, so that the FPGA circuit fault injection IP core of the present invention has the function of communicating with a PC through a universal serial data bus. The serial data transceiver module is used to communicate with a PC and can realize full-duplex data transmission and reception, including data, commands and control information. In this embodiment, the baud rate of the serial data transceiver module is 115200bps / s, and the data character format is: 1 start bit, 8 data bits and 1 stop bit. Among the 8 data bits, the low bit is arranged in front and the high bit is arranged in the back.

[0076] The data protocol parsing module is used to parse the communication protocol data packets received by the serial data transceiver module, as shown in Table 1:

[0077]

[0078]

[0079] The serial communication protocol data packet format consists of six items: packet header, instruction type, data length, data content, check code, and packet tail. The packet header is 16-bit data EB90; the instruction type is 8-bit data, which can perform 255 functional operations, and in the implementation column, only 9 instruction types are defined, namely FLASH erase, FLASH programming, FPGA parameter setting, FPGA configuration, FPGA readback, DUT parameter setting, DUT operation, fault generation, and fault injection; the data length is 24-bit data, so the data length in the data packet is no more than 16M bytes; the data content is specific data information; the check code is the checksum of the data content field (accumulated as single bytes, the result is double bytes); the packet tail is 16-bit data 09D7. Figure 2 The state transition diagram for the data protocol parsing module to receive the communication protocol data packet.

[0080] The register module is used to store the configurable register information of the IP core of the present invention. The module contains 19 configurable registers, which are used for FPGA configuration, FPGA readback, and FPGA fault injection operations, as shown in Table 2:

[0081]

[0082]

[0083] For example, the function of the configuration code stream length register is used to indicate that when performing FPGA reconfiguration, the "configuration code stream length" data is read from the CFI FLASH; the function of the read-back start position register is used to indicate that when performing FPGA read-back, data is read from the "read-back start position" data of the CFI FLASH; the function of the injection mode register is to control the FPGA fault injection process when performing FPGA fault injection.

[0084] The single-frame reconstruction instruction storage module is implemented with a simple dual-port RAM of 512*8 bits, which is mainly used to store the single-frame reconstruction packet header and single-frame reconstruction packet tail instructions. Table 3 is a schematic diagram of the storage distribution of the single-frame reconstruction instructions of the XC2V1000 FPGA in the single-frame reconstruction instruction storage module:

[0085]

[0086]

[0087] The fault set storage module is implemented with a simple 64K*8-bit dual-port RAM, which is mainly used to store the fault point information generated by the PC. The single fault point information consists of the fault frame address (4Bytes), fault word (2Bytes), fault bit (1Bytes), fault group (1Bytes) and Flash read address (3Bytes). A single fault point consists of 11 Bytes, so a single fault injection requires reading 11Bytes of data from the fault set storage module. The fault frame in the fault point information is the address stored in the FAR frame address register of the FPGA to be tested in the register module, which is used to replace the address when performing fault injection. Figure 5 The single frame reconstruction instruction stores the data in the address 0x40--0x43 of the module. The fault word in the fault point information is the word in the configuration frame that needs to be fault injected, and its range is 0~(configuration frame length-1). For example, 0x1 means to inject fault into the first word in the configuration frame. The fault bit in the fault point information indicates which bits in the fault word are to be fault injected. 1 represents fault injection, and 0 represents no fault injection. For example, 0h05 means to inject fault into the 0th and 2nd bits of the word. The fault group in the fault point information indicates whether the current fault point and the next fault point are in the same group of faults. 00 indicates non-same group faults, and FF indicates same group faults. If they are not in the same group of faults, the DUT operation is performed, otherwise, the fault injection operation of the next fault point is continued. The Flash read address in the fault point information indicates the starting address of the configuration frame data in FLASH.

[0088] The load set storage module is implemented using a simple 64K*8-bit dual-port RAM, which is mainly used to store the DUT input stimulus generated by the PC.

[0089] The read-back set storage module is implemented using a 1K*8-bit standard FIFO, which is mainly used to store DUT monitoring output data.

[0090] The FLASH interface control module is used to connect the FPGA circuit fault injection IP core provided in this embodiment to an external general-purpose parallel FLASH chip. The external general-purpose parallel FLASH chip is used to store the mask data (.msk) and the matching code data (.bit) of the FPGA to be tested. In this embodiment, the upper 8 bits in each FLASH address store the mask data (.msk), and the lower 8 bits store the matching code data (.bit). The FLASH interface control module can recognize three instructions: FLASH erase, FLASH programming (writing the mask data and matching code data of the FPGA to be tested into FLASH) and FLASH readback (FPGA configuration, FPGA readback and fault injection).

[0091] The JTAG interface control module is used to connect the FPGA circuit fault injection IP core of this embodiment to the JTAG interface of the external FPGA to be tested. The JTAG interface control module implements the reconfiguration and fault injection operations on the FPGA chip to be tested. Figure 3 This is the state transition diagram of the JTAG interface control module, and its state jump can be divided into four main processes: FPGA configuration, FPGA readback, FPGA single frame reconstruction and DUT operation. According to the instructions sent by the PC, the corresponding state jump can be realized and the corresponding functional operation can be completed. Take the IP core receiving the "fault injection (bit-by-bit injection)" instruction sent by the PC as an example for detailed explanation: First, the injection mode is judged. If the current instruction is bit-by-bit injection, the FPGA configuration process is entered (the JPROG_B instruction, CFG_IN instruction, Flash configuration code stream data and JSTART instruction are loaded in sequence to complete the FPGA reconfiguration); then, a fault point information (fault frame, fault word, fault bit, fault group and Flash read address) is read from the fault set storage module, and the FPGA single frame reconstruction is entered (the CFG_IN instruction, the reconstruction command packet header, the single frame configuration code stream data and the reconstruction command packet tail are loaded in sequence to complete the FPG A fault injection); secondly, fault grouping judgment, judge whether the current fault point and the next fault point are in the same group of faults. If they are in the same group of faults, continue the injection process of the next fault point, otherwise, enter the DUT operation process (execute DUT reset, DUT operation and DUT stop in sequence); finally, after the DUT stops, judge whether the current fault point is the last fault point. If so, end the current fault injection process, otherwise, perform fault injection mode judgment. If it is a bit-by-bit injection mode, enter the FPGA configuration process (i.e. repeat the above steps). If it is a cumulative injection mode, do not repeat the FPGA, but continue the injection process of the next fault point.

[0092] The DUT interface control module is used to connect the FPGA circuit fault injection IP core of the present invention to the interface of the external FPGA circuit to be tested (DUT, Design Under Test). The DUT interface control module realizes the monitoring of the input stimulus loading and output data of the FPGA circuit to be tested. Figure 4 This is the timing diagram of the DUT interface control module. It can be divided into three stages: 1) DUT reset: provide clock input to the DUT and provide a reset signal of 5 clock cycles; 2) DUT operation (monitoring): read "DUT operation cycle" data from the load set storage module, load input stimulus for the DUT, and automatically store "DUT monitoring cycle" DUT output data when "DUT monitoring start" arrives; 3) DUT operation end: stop providing clock input to the DUT.

[0093] The FPGA circuit fault injection IP core of the present invention can be transplanted to any FPGA development board with a serial port and CFI interface FLASH, such as Figure 5 As shown, the FPGA circuit fault injection IP core provided in this embodiment is directly transplanted into the main control FPGA in the development board. The code does not need any change, and the host computer can send corresponding instructions to implement the reconfiguration and fault injection functions of the FPGA to be tested.

[0094] The present invention provides an FPGA circuit fault injection algorithm, comprising the following steps:

[0095] Step 1) Fault injection mode determination: if it is a bit-by-bit injection mode (fault needs to be repaired), execute step 2); if it is a cumulative injection mode (fault does not need to be repaired), execute step 3);

[0096] Step 2) Fault repair: Use FPGA reconfiguration to repair the fault. In some unpredictable situations, modifying a single configuration frame data will also affect other configuration frame data. FPGA reconfiguration can avoid the accumulation of faults caused by the inability to modify faults, and ensure the authenticity of the fault injection effect.

[0097] Step 3) Fault injection: Inject faults by single-frame reconstruction. The "fault frame" in the fault point information (fault frame, fault word, fault bit, fault group and Flash read address) is embedded into the single-frame reconstruction data packet (packet header instruction, single-frame configuration data and packet tail instruction) to achieve single-frame fault injection, solve the time-consuming problem of reconfiguration-based fault injection, and improve fault injection efficiency.

[0098] Step 4) Fault grouping judgment: If the "fault grouping" in the current fault point information is a non-same group fault (00 indicates a non-same group fault, that is, the current fault point and the next fault point are not the same group faults), then execute step 5), otherwise, execute step 3). This fault grouping judgment cleverly solves the injection problem of different frame fault types;

[0099] Step 5) Monitor the operation of the DUT: read the "DUT operation cycle" data from the load set storage module to load the input stimulus to the DUT, and automatically store and upload the "DUT monitoring cycle" DUT output data when the "DUT monitoring start" arrives. This counting-based DUT operation monitoring method can effectively solve the problem of the DUT operation monitoring jumping into an infinite loop due to DUT function abnormality;

[0100] Step 6) Fault point determination: If the current fault point is the last one in the fault set, execute step 7); otherwise, execute step 1);

[0101] Step 7) Fault injection is completed.

[0102] The step 2) specifically includes:

[0103] Step 2-1) Control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state;

[0104] Step 2-2) Load JPROG_B and CFG_IN instructions in sequence, so that the TAP controller enters the Shift-DR state;

[0105] Step 2-3) Control the FLASH interface control module, read the configuration code stream data from it, write the configuration code stream data into the FPGA in the Shift-DR state, and perform FPGA reconfiguration;

[0106] Step 2-4) Load the JSTART instruction to start the FPGA function operation;

[0107] Step 2-5) Control the JTAG interface timing so that the TAP controller enters the Test-Logic-Reset state.

[0108] The step 3) specifically includes:

[0109] Step 3-1) Reading fault point information: Reading a fault point information (fault frame address, fault word, fault bit, fault group and Flash read address) from the fault set storage module;

[0110] Step 3-2) Control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state;

[0111] Step 3-3) Load the CFG_IN instruction to make the TAP controller enter the Shift-DR state;

[0112] Step 3-4) Read the single frame reconstruction header command from the single frame reconstruction instruction storage module, replace the frame address in the header command with the "fault frame" in the fault point information, and write it into the FPGA in the Shift-DR state;

[0113] Step 3-5) Control the FLASH interface control module, use the "Flash read address" as the starting address, read the fault frame data from it, and write it into the FPGA in the Shift-DR state;

[0114] Let N be the number of bytes of fault frame data, FLASH[i] be the i-th data read from FLASH

[0115] For i from 0 to N-1, perform the following loop operation:

[0116] If i = "fault word", perform XOR operation on FLASH[i] and "fault bit" and write it into FPGA;

[0117] Otherwise, write FLASH[i] directly to FPGA;

[0118] Step 3-6) Read the single frame reconstruction packet tail command from the single frame reconstruction instruction storage module, write it into the FPGA in the Shift-DR state, and perform FPGA single frame fault injection;

[0119] Step 3-7) Control the JTAG interface timing so that the TAP controller enters the Test-Logic-Reset state.

[0120] From the above specific description of the present invention, it can be seen that the FPGA circuit fault injection method and its IP core provided by the present invention are highly compatible and can realize fault injection into SRAM-type FPGA chips of Xilinx's V2, V4, V5, V6, V7, K7 and A7 series; support two injection modes: bit-by-bit injection mode and cumulative injection mode; support multiple fault types: single bit, multi-bit (same frame, physically adjacent frames, any physically non-adjacent frames); the DUT interface is flexible, and in actual use, the DUT interface of the IP core can be left floating, or it can be connected to the input / output of the FPGA circuit to be monitored, which is easy to use and flexible to monitor; it is highly portable and can be transplanted to any FPGA development board with a serial port and a CFI interface FLASH.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A method for injecting faults into an FPGA circuit, characterized in that: The method comprises the following steps: Step 1) determining the fault injection mode stored in the fault set storage module through the JTAG interface control module, and if the fault injection mode is a bit-by-bit injection mode, executing step 2), and if the fault injection mode is a cumulative injection mode, executing step 3); wherein the bit-by-bit injection mode indicates a fault that needs to be repaired, and the cumulative injection mode indicates a fault that does not need to be repaired; Step 2) repairing the fault of the FPGA to be tested by reconfiguring the FPGA through the JTAG interface control module to ensure the authenticity of the fault injection effect, and then executing step 3); Step 3) injecting faults into the FPGA to be tested by the JTAG interface control module in a single frame reconstruction mode, and then proceeding to step 4); Step 4) determining whether the fault grouping in the current fault point information is a fault of a different group through the JTAG interface control module; if the fault grouping in the current fault point information is a fault of a different group, executing step 5); otherwise, executing step 3), wherein the fault of a different group is that the current fault point and the next fault point are not faults of the same group; Step 5) through the JTAG interface control module, control the DUT interface control module to read M data from the load set storage module as DUT input stimulus; sequentially load the DUT input stimulus to the DUT, and start counting, when the count value reaches N, the DUT interface control module automatically stores and uploads X monitoring output data of the DUT to the read back set storage module for storage; wherein M is the value in the DUT operation cycle register of the register module, N is the value in the DUT monitoring start register of the register module, and X is the value in the DUT monitoring cycle register of the register module; Step 6) determining, through the JTAG interface control module, whether the fault point in the current fault point information is the last fault point in the known fault set, if yes, executing step 7), otherwise, executing step 1); Step 7) Fault injection is completed.

2. The FPGA circuit fault injection method according to claim 1, characterized in that: The step 2) specifically includes: Step 2-1) Control the JTAG interface timing through the JTAG interface control module, so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; Step 2-2) sequentially loading JPROG_B and CFG_IN instructions through the JTAG interface control module to make the TAP controller enter the Shift-DR state; Step 2-3) Controlling the FLASH interface control module through the JTAG interface control module, so that the FLASH interface control module reads the configuration code stream data from the external FLASH device, and writes the configuration code stream data into the FPGA in the Shift-DR state to perform FPGA reconfiguration; Step 2-4) Loading the JSTART instruction through the JTAG interface control module to start the FPGA function operation; Step 2-5) Control the JTAG interface timing through the JTAG interface control module to make the TAP controller enter the Test-Logic-Reset state.

3. The FPGA circuit fault injection method according to claim 1, characterized in that: The step 3) specifically includes: Step 3-1) reading a fault point information from the fault set storage module through the JTAG interface control module; wherein the fault point information includes: fault frame address, fault word, fault bit, fault group and Flash read address; Step 3-2) controlling the JTAG interface timing by the JTAG interface control module so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; Step 3-3) Loading the CFG_IN instruction through the JTAG interface control module to make the TAP controller enter the Shift-DR state; Step 3-4) reading the header command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module through the JTAG interface control module; and replacing the frame address in the header command with the fault frame address in the fault point information; the JTAG interface control module writes the replaced header command into the FPGA in the Shift-DR state; Step 3-5) Controlling the FLASH interface control module through the JTAG interface control module, taking the Flash read address in the fault point information as the starting address, and reading the fault frame data from the external FLASH device, wherein the fault frame data includes G bytes, and each byte of the fault frame data is represented by FLASH[i]; i represents the i-th byte, and the value range is 0 to G-1; If the i-th byte of fault frame data FLASH[i] is the fault word in the fault point information, the i-th byte of fault frame data FLASH[i] is XORed with the fault bit in the fault point information by using the JTAG interface control module and then written into the FPGA; Otherwise, the fault frame data FLASH[i] of the i-th byte is directly written into the FPGA; Step 3-6) reading the tail command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module through the JTAG interface control module, and writing it into the FPGA in the Shift-DR state through the JTAG interface control module to perform FPGA single-frame fault injection; Step 3-7) Control the JTAG interface timing through the JTAG interface control module to make the TAP controller enter the Test-Logic-Reset state.

4. An IP core for FPGA circuit fault injection, executing any of the methods described in claims 1-3, the IP core comprising: The serial data transceiver module and the data protocol analysis module are characterized in that the IP core also includes: a register module, a single frame reconstruction instruction storage module, a fault set storage module, a load set storage module, a read back set storage module, a FLASH interface control module, a JTAG interface control module and a DUT interface control module; wherein, The register module is used to store register information; The single frame reconstruction instruction storage module is used to store a single frame reconstruction data packet; The fault set storage module is used to store fault point information; wherein the fault point information includes: fault frame address, fault word, fault bit, fault group and Flash read address; The load set storage module is used to store DUT input stimulus; The read-back set storage module is used to store DUT monitoring output data; The FLASH interface control module is used to write and read the FLASH memory based on the control of the JTAG interface control module; The JTAG interface control module is used to determine the fault injection mode stored in the fault set storage module; to repair the fault of the FPGA to be tested by using the FPGA reconfiguration method; to inject faults into the FPGA to be tested by using a single frame reconstruction method; to determine whether the fault group in the current fault point information is a non-same group fault; to determine whether the fault point in the current fault point information is the last fault point in the known fault set; The DUT interface control module, based on the control of the JTAG interface control module, is used to read data from the load set storage module as DUT input stimulus; load the DUT input stimulus to the DUT in turn, and is used to automatically store and upload the DUT monitoring output data to the read back set storage module for storage.

5. The IP core for FPGA circuit fault injection according to claim 4, characterized in that: The register module includes: a configuration code stream length register, a configuration array length register, a configuration frame length register, a readback command packet header length register, a readback command packet tail length register, a readback data delay period register, a readback start position register, a single frame reconstruction command packet header length register, a single frame reconstruction command packet tail length register, an injection mode register, a fault point information length register, a JTAG scan instruction bit register, a CFG_IN instruction register, a CFG_OUT instruction register, a JPROG_B instruction register, a JSTART instruction register, a DUT operation cycle register, a DUT monitoring start register and a DUT monitoring cycle register, which are shared by the JTAG interface control module and the DUT interface control module.

6. The IP core for FPGA circuit fault injection according to claim 4 or 5, characterized in that: The DUT interface control module, based on the control of the JTAG interface control module, is used to read M data from the load set storage module as DUT input stimulus; load the DUT input stimulus to the DUT in turn, and start counting; when the count value reaches N, the DUT interface control module is used to automatically store and upload X DUT monitoring output data to the read back set storage module for storage; wherein M is the value in the DUT operation cycle register of the register module, N is the value in the DUT monitoring start register of the register module, and X is the value in the DUT monitoring cycle register of the register module; the DUT interface control module is also used to provide clock input and reset signals for the DUT.

7. The IP core for FPGA circuit fault injection according to claim 4, characterized in that: The fault frame address in the fault point information is the address stored in the FAR frame address register of the FPGA to be tested; The fault bit of the fault point information indicates a bit in the fault word where a fault is injected or not injected, wherein a fault bit of 1 represents that a fault is injected, and a fault bit of 0 represents that a fault is not injected; In the fault grouping of the fault point information, 00 is used to represent faults that are not in the same group, and FF is used to represent faults in the same group; The Flash read address of the fault point information is the starting address of the fault frame data in the external FLASH device.

8. The IP core for FPGA circuit fault injection according to claim 4, characterized in that: The single frame reconstruction instruction storage module adopts a simple dual-port RAM of 512*8 bits; The load set storage module adopts a simple dual-port RAM of 64K*8 bits; The read-back set storage module adopts a 1K*8-bit standard FIFO; The FLASH interface control module adopts a 64M*16-bit universal parallel interface FLASH; The register module uses register groups of different lengths.

9. The IP core for FPGA circuit fault injection according to claim 4, characterized in that: The JTAG interface control module is used to repair the fault of the FPGA to be tested in the bit-by-bit injection mode by using the FPGA reconfiguration method, specifically including: The JTAG interface control module is used to control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; is used to load the JPROG_B and CFG_IN instructions in sequence so that the TAP controller enters the Shift-DR state; is used to control the FLASH interface control module so that the FLASH interface control module reads the configuration code stream data from the external FLASH device and writes the configuration code stream data into the FPGA in the Shift-DR state to perform FPGA reconfiguration; is used to load the JSTART instruction to start the FPGA function operation; is used to control the JTAG interface timing so that the TAP controller enters the Test-Logic-Reset state.

10. The IP core for FPGA circuit fault injection according to claim 4, characterized in that: The JTAG interface control module is used to inject faults into the FPGA to be tested by using a single frame reconstruction method, specifically including: The JTAG interface control module is used to read a fault point information from the fault set storage module; to control the JTAG interface timing so that the TAP controller enters the Shift-IR state from the Test-Logic-Reset state; to load the CFG_IN instruction so that the TAP controller enters the Shift-DR state; to read the header command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module; to replace the frame address in the header command with the fault frame address in the fault point information; to write the replaced header command into the FPGA in the Shift-DR state; to control the FLASH interface control module, using the Flash read address in the fault point information as the starting address, to read the fault frame data from the external FLASH device, wherein the fault frame data includes G bytes, and each byte of the fault frame data is represented by FLASH[i]; i represents the i-th byte, and the value range is 0 to G-1; If the i-th byte of fault frame data FLASH[i] is the fault word in the fault point information, the JTAG interface control module is used to write the i-th byte of fault frame data FLASH[i] into the FPGA after performing an XOR operation with the fault bit in the fault point information; otherwise, the JTAG interface control module is used to directly write the i-th byte of fault frame data FLASH[i] into the FPGA; The JTAG interface control module is also used to read the tail command in the single-frame reconstruction data packet from the single-frame reconstruction instruction storage module, and write it into the FPGA in the Shift-DR state to perform FPGA single-frame fault injection; and is used to control the JTAG interface timing to enable the TAP controller to enter the Test-Logic-Reset state.

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