Memory system having a memory controller

Abstract

The present invention relates to a memory system, the memory system comprising: a memory block including a plurality of pages, each of which includes a plurality of memory cells connected to a bit line and a word line; an address manager configured to output addresses corresponding to the plurality of pages; and a system data manager configured to generate index data corresponding to each of the addresses and output the index data and information about the memory cell to be stored with the index data, respectively, the index data indicating whether user data is inverted. The system data manager is configured to determine the memory cells connected to different bit lines from among the memory cells included in the adjacent pages corresponding to the consecutive addresses in the addresses as the memory cells to be stored with the index data corresponding to the consecutive addresses.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0183762, filed on December 24, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a memory system having a memory controller, and more particularly, to a memory system having a memory controller that can generate and manage system data. Background Art

[0004] The memory system may include a memory device capable of storing data and a memory controller capable of controlling the memory device.

[0005] The storage device may include a memory device capable of storing data, and the memory device may be classified into a volatile memory device and a nonvolatile memory device.

[0006] A volatile memory device is a memory device that stores data only when power is supplied and the stored data disappears when the power supply is interrupted. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0007] A nonvolatile memory device is a memory device in which stored data does not disappear even when power supply is interrupted. Nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, etc. Summary of the invention

[0008] Various embodiments of the present disclosure provide a memory system having a memory controller that can prevent a phenomenon in which the same data is stored in flag cells included in the same column.

[0009] According to one aspect of the present disclosure, a memory system is provided, the memory system comprising: a memory block including a plurality of pages, wherein each of the plurality of pages includes a plurality of memory cells connected to a bit line and one of the word lines; an address manager configured to output addresses corresponding to the plurality of pages, each of the addresses indicating a page of the plurality of pages where user data is to be stored; and a system data manager configured to generate index data corresponding to each of the addresses and output the index data and information about the memory cell where the index data is to be stored, respectively, the index data indicating whether the user data is inverted. The system data manager may be configured to determine memory cells connected to different bit lines from among the memory cells included in adjacent pages corresponding to consecutive addresses in the address as memory cells where the index data corresponding to the consecutive addresses is to be stored.

[0010] According to another aspect of the present disclosure, a memory system is provided, the memory system comprising: a memory device including a first memory cell connected to a first bit line and a first word line, a second memory cell connected to a second bit line adjacent to the first bit line and the first word line, a third memory cell connected to the first bit line and the second word line adjacent to the first word line, and a fourth memory cell connected to the second bit line and the second word line; and a memory controller configured to transmit a data set including index data to the memory device in a programming operation. The memory controller may generate the data set so that the index data is stored in the first to fourth memory cells.

[0011] According to another aspect of the present disclosure, a memory system is provided, the memory system comprising: a memory block including a first area storing index data and a second area storing user data; a peripheral circuit configured to program the index data and the user data in the memory block; and a memory controller configured to generate index data according to a state of the user data and transmit the user data and the index data to the peripheral circuit. The index data may have a predetermined bit size. The index data may be stored in memory cells connected to different bit lines in the first area. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings; however, the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0014] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram illustrating a memory device.

[0016] Figure 3 is a diagram illustrating a memory cell array and a page buffer group.

[0017] Figure 4 is a diagram illustrating a memory block.

[0018] Figure 5 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0019] Figure 6 is a diagram illustrating a program operation according to an embodiment of the present disclosure.

[0020] Fig. 7A and Figure 7B is a diagram illustrating a data set generated by a memory controller according to an embodiment of the present disclosure.

[0021] Figure 8 is a diagram illustrating a schema of system data including index data according to an embodiment of the present disclosure.

[0022] Fig.9A and Fig. 9B is a diagram illustrating a method for transmitting a data set generated by a memory controller to a memory device according to an embodiment of the present disclosure.

[0023] Fig.10 is a diagram showing a schema of system data according to the first embodiment of the present disclosure.

[0024] Fig.11 is a diagram illustrating a schema of system data according to the second embodiment of the present disclosure.

[0025] Fig.12 is a diagram illustrating a schema of system data according to the third embodiment of the present disclosure.

[0026] Fig.13 is a diagram illustrating a schema of system data according to a fourth embodiment of the present disclosure.

[0027] Fig.14is a diagram illustrating a schema of system data according to a fifth embodiment of the present disclosure.

[0028] Fig.15 is a diagram illustrating a read operation according to an embodiment of the present disclosure.

[0029] Fig.16 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0030] Fig.17 is a diagram illustrating a solid state drive (SDD) to which a memory device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0031] For the purpose of describing embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are illustrative only. Embodiments of the concepts according to the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0032] Method described herein, process and / or operation can be performed by code or instruction to be run by computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or the element except the element described herein.Because the algorithm of the basis of formation method (or the operation of computer, processor, controller or other signal processing device) is described in detail, the code or instruction for implementing the operation of method embodiment can convert computer, processor, controller or other signal processing device into the special processor for performing the method herein.

[0033] When implemented at least in part in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0034] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , the memory system 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may include a plurality of memory devices MD, and the plurality of memory devices MD may be connected to the memory controller 1200 through input / output lines.

[0036] The memory controller 1200 may communicate between the host 1500 and the memory device MD. The memory controller 1200 may generate a command CMD for controlling the memory device MD according to a request RQ of the host 1500 and perform background operations for performance improvement of the memory system 1000 even when the request RQ of the host 1500 does not exist.

[0037] The host 1500 may generate request RQ for various operations and output the generated request RQ to the memory system 1000. For example, the request RQ may include a program request capable of controlling a program operation, a read request capable of controlling a read operation, an erase request capable of controlling an erase operation, and the like.

[0038] The host 1500 can communicate with the memory system 1000 through various communication standards and interfaces such as: Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0039] The memory controller 1200 according to the present embodiment may transmit the command CMD, address and data for the programming operation to the memory device MD in the programming operation and may receive the data set read from the memory device MD in the reading operation. The memory controller 1200 may generate system data related to the user data received from the host 1500, and then may transmit the data set including the user data and the system data to the selected memory device MD, and the system data is managed by the memory controller 1200. The memory controller 1200 may control the memory device MD to store the user data as one of the non-inverted version and the inverted version according to the number of cycles of the programming operation and the erase operation of the memory device MD (hereinafter referred to as the number of cycles). When the user data is stored in the memory device MD, the memory controller 1200 may generate index data indicating whether the user data is stored as a non-inverted version or an inverted version and may include the index data in the system data related to the (inverted or non-inverted) user data to generate a data set. The memory controller 1200 may change the position, such as the column of the index data included in the data set. For example, the column refers to an area (e.g., a memory cell) determined according to a string or a bit line in a storage block to store the system data. For example, in a memory block, a row region (e.g., page) may be determined according to a word line, and a column region (e.g., memory cell) may be determined according to a string or a bit line. A column (or a column address) may indicate a storage location (e.g., location of a memory cell) in a first direction (e.g., column direction). Here, the first direction may be a direction different from a second direction (e.g., row direction) in which pages are arranged. A column may indicate an arrangement of a plurality of bit lines.

[0040] Therefore, in a read operation, the memory controller 1200 can determine the state of the user data according to the system data of the data set read from the memory device MD. For example, in the system data, when the index data indicates that the read user data related to the index data is an inverted version, the memory controller 1200 can determine that the read user data is inverted data and can restore the read user data to non-inverted data, and then output the original user data (i.e., non-inverted data) to the host 1500.

[0041] The following will be described in detail Figure 1 The memory device MD shown is as follows.

[0042] Figure 2 is a diagram illustrating a memory device.

[0043] Reference Figure 2 The memory device MD may include a memory cell array 110 storing data, a peripheral circuit 200 for performing a program operation, a read operation, or an erase operation, and a logic circuit 160 for controlling the peripheral circuit 200 .

[0044] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKi (i is a positive integer) storing data. Each of the memory blocks BLK1 to BLKi may include a plurality of memory cells. The memory cells may be implemented as a two-dimensional structure in which the memory cells are arranged parallel to the substrate or a three-dimensional structure in which the memory cells are stacked on the substrate in a vertical direction.

[0045] The peripheral circuit 200 may include a voltage generator 120 , a row decoder 130 , a page buffer group 140 , and an input / output circuit 150 .

[0046] The voltage generator 120 may generate and output operation voltages Vop necessary for various operations in response to the voltage code VCD. For example, the voltage generator 120 may generate and output operation voltages Vop including a program voltage, a verification voltage, a read voltage, a pass voltage, an erase voltage, and the like.

[0047] The row decoder 130 may select one memory block among the memory blocks BLK1 to BLKi included in the memory cell array 110 according to the row address RADD and transmit the operating voltage Vop to the selected memory block.

[0048] The page buffer group 140 may be connected to the memory cell array 110 through the bit lines. For example, the page buffer group 140 may include page buffers connected to the respective bit lines. The page buffers may operate simultaneously in response to the page buffer control signal PBSIG and temporarily store data in a program operation or a read operation.

[0049] The input / output circuit 150 can be connected to the memory controller ( Figure 1 1200 as shown). The input / output circuit 150 can input / output commands CMD, addresses ADD, and data DATA through the input / output lines. For example, the input / output circuit 150 can transmit the commands CMD and addresses ADD received through the input / output lines to the logic circuit 160, and transmit the data DATA received through the input / output lines to the page buffer group 140. The input / output circuit 150 can output the data DATA received from the page buffer group 140 to the memory controller 1200 through the input / output lines. The data DATA can be referenced to Figure 1 Describes the dataset.

[0050] The logic circuit 160 may output a voltage code VCD, a row address RADD, and a page buffer control signal PBSIG in response to a command CMD and an address ADD. For example, the logic circuit 160 may include software that executes an algorithm in response to a command CMD and hardware configured to output various signals according to the address ADD and the algorithm.

[0051] Figure 3 is a diagram illustrating a memory cell array and a page buffer group.

[0052] Reference Figure 3 , the memory cell array 110 may include a first storage block BLK1 to an i-th storage block BLKi. Each of the first storage block BLK1 to the i-th storage block BLKi may include a plurality of regions in which different types of data may be stored. For example, each of the first storage block BLK1 to the i-th storage block BLKi may include a first sub-block 1SB and a second sub-block 2SB corresponding to different regions. The first sub-block 1SB may be connected in common to a first bit line BL1 to a j-th bit line BLj (j is a positive integer), and the second sub-block 2SB may be connected in common to a (j+1)-th bit line BLj+1 to a (j+m)-th bit line BLj+m. System data may be stored in the first sub-block 1SB, and user data may be stored in the second sub-block 2SB. Therefore, the storage capacity of the first sub-block 1SB is less than the storage capacity of the second sub-block 2SB. That is, the number of memory cells included in the first sub-block 1SB is less than the number of memory cells included in the second sub-block 2SB. In some embodiments, memory cells included in the first sub-block 1SB may be defined as flag cells, and memory cells included in the second sub-block 2SB may be defined as normal memory cells.

[0053] The page buffer group 140 may include first to j-th page buffers PB1 to PBj commonly connected to the first sub-block 1SB and (j+1)-th page buffers PBj+1 to (j+m)-th page buffers PBj+m commonly connected to the second sub-block 2SB. In a programming operation, a data set received from a memory controller may be stored in the first to (j+m)-th page buffers PB1 to PBj+m, and a voltage of the first to (j+m)-th bit lines BL1 to BLj+m may be determined based on the data sets stored in the first to (j+m)-th page buffers PB1 to PBj+m.

[0054] In a program operation, a selected memory block among the first to i-th memory blocks BLK1 to BLKi may be connected to the first to (j+m)-th bit lines BLj+m, and selected memory cells included in the selected memory block may be programmed.

[0055] Figure 4 is a diagram showing a storage block, and shows as an example Figure 3 The i-th memory block BLKi among the plurality of memory blocks BLK1 to BLKi is shown.

[0056] Reference Figure 4 , the i-th storage block BLKi may include a plurality of strings ST. The plurality of strings ST may be connected between the first bit line BL1 to the (j+m)-th bit line BLj+m and the source line SL. For example, one string ST may be connected between the first bit line BL1 and the source line SL, and one string ST may be connected between the second bit line BL2 and the source line SL. In this way, one string ST may also be connected between the (j+m)-th bit line BLj+m and the source line SL.

[0057] A plurality of strings ST may be included in each of the first sub-block 1SB and the second sub-block 2SB, and the number of strings ST included in the first sub-block 1SB may be different from the number of strings ST included in the second sub-block 2SB. When it is set that system data is stored in the first sub-block 1SB and user data is stored in the second sub-block 2SB, the number of strings ST included in the first sub-block 1SB may be less than the number of strings ST included in the second sub-block 2SB. Each of the strings ST included in the first sub-block 1SB and the second sub-block 2SB may include a source selection transistor SST, first to nth memory cells F1 to Fn, and a drain selection transistor DST. The string ST connected to the first bit line BL1 will be described in detail as an example.

[0058] The source selection transistor SST included in the string ST can electrically connect the source line SL and the first memory cell F1 or interrupt the connection between the source line SL and the first memory cell F1 according to the voltage applied to the source selection line SSL. The gates of the first memory cell F1 to the nth memory cell Fn included in the string ST can be connected to the first word line WL1 to the nth word line WLn, respectively. The drain selection transistor DST included in the string ST can electrically connect the first bit line BL1 and the nth memory cell Fn or interrupt the connection between the first bit line BL1 and the nth memory cell Fn according to the voltage applied to the drain selection line DSL. The gates of the source selection transistors SST included in different strings ST can be commonly connected to the source selection line SSL, the gates of the first memory cells F1 to the nth memory cells Fn included in different strings ST can be connected to the first word line WL1 to the nth word line WLn, and the gates of the drain selection transistors DST included in different strings ST can be commonly connected to the drain selection line DSL. A group of memory cells connected to the same word line is referred to as a page PG, and a program operation and a read operation may be performed in units of page PG.

[0059] The programming operation according to the embodiment can be performed by using an incremental step pulse programming (ISPP) method that gradually increases the programming voltage. In the programming operation using the ISPP method, a plurality of programming loops can be performed until the threshold voltage of the selected memory cell increases to the target voltage, and the programming voltage can be gradually increased each time the programming loop is performed.

[0060] The first memory cell F1 to the nth memory cell Fn can be programmed or read in various ways according to the number of bits stored. For example, 1 bit of data can be stored in one memory cell in a single-layer cell (SLC) manner, and 2 or more bits of data can be stored in one memory cell in a multi-layer cell (MLC) manner. For example, 2 bits of data can be stored in one memory cell in an MLC manner, 3 bits of data can be stored in one memory cell in a three-layer cell (TLC) manner, and 4 bits of data can be stored in one memory cell in a four-layer cell (QLC) manner. In addition, 5 or more bits of data can be stored in one memory cell. In the MLC manner or the manner of more layers of cells, the data of multiple bits stored in one memory cell can be different logical page data. The TLC manner will be described as an example. In the TLC manner, three logical page data can be stored in one page. The three logical page data can be the least significant bit (LSB) data, the middle significant bit (CSB) data, and the most significant bit (MSB) data.

[0061] Figure 5 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0062] Reference Figure 5 , the memory controller 1200 may include a host interface 51, a user data manager 52, a system data manager 53, an address manager 54, a central processing unit 55, a system memory 56, a cycle counter 57, and a memory interface 58. The host interface 51, the user data manager 52, the system data manager 53, the address manager 54, the central processing unit 55, the system memory 56, the cycle counter 57, and the memory interface 58 may communicate with each other through a bus 60. The host interface 51, the user data manager 52, the system data manager 53, the address manager 54, the system memory 56, the cycle counter 57, and the memory interface 58 may operate under the control of the central processing unit 55. Each unit will be described in detail as follows.

[0063] The host interface 51 may transfer a request, an address, or data between the host 1500 and the memory controller 1200. For example, when receiving a request output from the host 1500, the host interface 51 may transfer the received request to the central processing unit 55. The central processing unit 55 may change the received request into a command that may be used in the memory system, and may control each of the host interface 51, the user data manager 52, the system data manager 53, the address manager 54, the system memory 56, the loop counter 57, and the memory interface 58 according to the received request. For example, under the control of the central processing unit 55, information input to the host interface 51 may be selectively transferred to other units 52 to 54 and 56 to 58, and information may be transferred between different units 52 to 54 and 56 to 58.

[0064] The user data manager 52 may transfer the user data output from the host interface 51 to the memory interface 58 or change the user data into inverted data and then transfer the inverted user data to the system memory 56. For example, the user data manager 52 may determine whether the number of cycles of the selected memory block corresponds to a reference value in the programming operation. When the number of cycles of the selected memory block does not correspond to the reference value, the user data manager 52 may transfer the user data as non-inverted data to the system memory 56. When the number of cycles of the selected memory block corresponds to the reference value, the user data manager 52 may invert the user data and transfer the inverted data to the system memory 56. For example, the reference value may be an odd number or an even number. When the reference value is an even number, the user data manager 52 may transfer the user data as non-inverted data to the system memory 56 when the number of cycles of the selected memory block is an odd number, and transfer the inverted user data to the system memory 56 when the number of cycles of the selected memory block is an even number. Therefore, the user data manager 52 may selectively invert the user data of each memory block according to the number of cycles of the memory block.

[0065] The system data manager 53 may manage user data in units of pages. For example, the system data manager 53 may generate various information about the user data as system data. For example, the system data may include index data, parity check, etc. The index data may be data indicating whether the user data has been inverted. For example, when the user data manager 52 maintains the user data as non-inverted data, the system data manager 53 may generate index data as first index data. The first index data may be set to data 1 selected from data 0 and 1. When the user data manager 52 inverts the user data, the system data manager 53 may generate index data as second index data. The second index data may be set to data 0 selected from data 0 and 1. Data 1 may indicate that the first sub-block ( Figure 3The erased state of the memory cells included in the first sub-block (1SB) is shown, and data 0 can represent the erased state of the memory cells included in the first sub-block ( Figure 3 When the user data manager 52 inverts the user data, the system data manager 53 may generate index data corresponding to the programming state of the memory cell.

[0066] Moreover, the system data manager 53 can change the storage location of the index data to be stored among the flag cells configured to store the system data according to the word line address generated by the address manager 54. The storage location or flag cell where the index data is to be stored can be represented by a column. Hereinafter, the storage location or flag cell where the index data is to be stored is referred to as a column. In other words, the system data manager 53 can generate index data corresponding to each of the addresses. The system data manager 53 can output the index data and the information about the memory cell where the index data is to be stored, respectively. In order to describe this, the address manager 54 will be described as follows.

[0067] The address manager 54 may distinguish user data for word lines and transmit a word line address representing a distinguished unit of user data to the system data manager 53. For example, the address manager 54 may distinguish the second sub-block 2SB for word lines (see Figure 3 ), associates the distinguishing units of the user data with the respective word lines, and transmits each address of the word lines respectively associated with the distinguishing units of the user data to the system data manager 53. In other words, the address manager 54 may output addresses corresponding to a plurality of pages. Each of the addresses may indicate a page among the plurality of pages where the user data is to be stored.

[0068] For example, when user data associated with a first word line is transferred from the user data manager 52 to the system memory 56, the address manager 54 may transfer the address of the first word line to the system data manager 53 for the user data associated with the first word line. When user data associated with a second word line is transferred from the user data manager 52 to the system memory 56 after the user data associated with the first word line is transferred to the system memory 56, the address manager 54 may transfer the address of the second word line to the system data manager 53 for the user data associated with the second word line. In this way, whenever user data differentiated for a word line is transferred from the user data manager 52 to the system memory 56, the address manager 54 may transfer the address of the word line to the system data manager 53. The second sub-block 2SB (see FIG. 2 ) may be used for each memory block according to the number of cycles of each memory block. Figure 3) as a unit to invert or non-invert the user data. In an embodiment, the inverted or non-inverted user data may be transferred from the user data manager 52 to the system memory 56 at a time in units of the second sub-block 2SB. In an embodiment, the user data in units of the second sub-block 2SB and stored in the system memory 56 may be distinguished for word lines. In an embodiment, the addresses of the word lines associated with the respective distinguishing units of the user data may be provided to the system data manager 53 for distinguishing units of the user data respectively associated with the word lines. In other words, the addresses of the word lines may correspond to pages respectively. Specifically, each of the addresses of the word lines may indicate a page connected to the word line.

[0069] The system data manager 53 may determine the memory cells connected to different bit lines from among the memory cells included in the adjacent pages corresponding to the consecutive addresses in the address as the memory cells to be stored with respect to the index data corresponding to the consecutive addresses. In other words, the system data manager 53 may change the column in which the system data is to be stored according to the word line address output from the address manager 54. For example, the system data manager 53 may change the column of the index data so that the index data of the consecutive word line addresses will not be stored in the same column. When the column of the index data is changed, since there is a correlation between the column storing the index data and the arrangement of the index data in the system data or data set, the arrangement of the index data in the data set may change. The system data manager 53 may generate system data having various arrangements or patterns by changing the column of the index data. The system data manager 53 may transmit the generated system data to the system memory 56. The system data manager 53 may output the index data and the information about the memory cell to be stored with respect to the index data. The information may indicate the location of the index data to be stored.

[0070] The system memory 56 may include a buffer unit capable of temporarily storing data. For example, the buffer unit may be implemented using a dynamic random access memory (DRAM) or a static random access memory (SRAM). In addition, the buffer unit may be implemented using various types of units. The system memory 56 may store various information necessary for the operation of the memory controller 1200. For example, the system memory 56 may include an address mapping table as information on the connection relationship between a physical address and a logical address, and temporarily store data in a programming operation or a read operation. The physical address may be an address used in the storage device 1100, and the logical address may be an address used in the host 1500. In a programming operation, the system memory 56 may temporarily store a data set including user data and system data, which is associated with a word line address, and then transfer the data set to the memory interface 58 under the control of the central processing unit 55.

[0071] The cycle counter 57 may count the number of cycles of the selected memory block in the programming operation. The number of cycles of the selected memory block refers to the number of times the programming operation and the erase operation are performed in the selected memory block. For example, when a programming operation is performed once and an erase operation is performed once, the number of cycles increases by 1. The cycle counter 57 may transmit the accumulated number of cycles of the selected memory block in the programming operation to the user data manager 52.

[0072] The memory interface 58 may transfer information between the memory controller 1200 and the memory device 1100. For example, in a program operation, the memory interface 58 may transfer a command output from the central processing unit 55 and a data set and an address output from the system memory 56 to a selected memory device included in the memory device 1100. In a read operation, the memory interface 58 may transfer a data set output from the memory device 1100 to the system memory 56. Errors of the data set transferred to the system memory 56 may be detected and corrected by an error correction operation performed by an error corrector (not shown), and user data included in the data set may be output to the host 1500 through the host interface 51.

[0073] Figure 6 is a diagram illustrating a program operation according to an embodiment of the present disclosure.

[0074] Reference Figure 5 and Figure 6 When the host 1500 outputs a program request to the memory controller 1200 (S61), the memory controller 1200 may select a memory block to be programmed in response to the program request (S62). For example, the memory controller 1200 may select a block address of a memory block to be programmed.

[0075] When the cycle counter 57 transmits the cycle number of the selected memory block to the user data manager 52, the user data manager 52 may compare the cycle number with a reference value (S63). The reference value may be an odd number or an even number.

[0076] When the cycle number of the selected memory block does not correspond to the reference value (No), the user data manager 52 may transfer the user data as non-inverted data to the system memory 56, and the system data manager 53 may generate system data related to the user data and transfer the generated system data to the system memory 56. Since the user data is maintained as non-inverted data, the first index data may be included in the system data.

[0077] Subsequently, the data set temporarily stored in the system memory 56 may be transferred to the memory interface 58, and the data set stored in the memory interface 58 may be output to the selected memory device (S66).

[0078] When the cycle number of the selected memory block corresponds to the reference value (Yes), the user data manager 52 may invert the user data (S64). The inverted user data may be transferred to the system memory 56.

[0079] Subsequently, the system data manager 53 may generate system data related to the inverted user data. The system data manager 53 may generate second index data indicating that the user data is inverted data, and select a column to store the second index data according to the word line address (S65). For example, whenever the word line address changes, the system data manager 53 may change the column to store the index data.

[0080] When the inverted user data and system data generated in operations S64 and S65 are transmitted to the system memory 56, the system memory 56 may transmit a data set including the user data and the system data to the memory interface 58, and the memory interface 58 may output the data set to the selected memory device (S66).

[0081] In the above embodiment, when the number of cycles of the selected storage block corresponds to the reference value (yes), the column storing the second index data is changed. However, even when the number of cycles of the selected storage block does not correspond to the reference number (no), the operation of changing the column storing the first index data can be performed.

[0082] Fig. 7A and Figure 7B is a diagram illustrating a data set generated by a memory controller according to an embodiment of the present disclosure.

[0083] Reference Fig. 7A , when (j+m)-bit data is stored in one page, the first column C1 to the (j+m)-th column C(j+m) may be allocated to each memory cell storing 1-bit data. The first bit line may be connected to the memory cell corresponding to the first column C1, and the (j+m)-th bit line may be connected to the memory cell corresponding to the (j+m)-th column C(j+m).

[0084] In one page, system data may be stored in memory cells corresponding to the first to j-th columns C1 to Cj, and user data may be stored in memory cells corresponding to the (j+1)-th to (j+m)-th columns C(j+m).

[0085] The system data may include an index data ID and page information PIF. The index data ID may be stored in any one of the memory cells corresponding to the first column C1 to the jth column Cj. The page information PIF may be stored in the memory cells corresponding to the first column C1 to the jth column Cj except for the column corresponding to the memory cell storing the index data ID. The page information PIF may include various information about the user data. For example, the page information PIF may include logical page data information of the user data. The logical page data information is information that may be included in the system data in an MLC manner or in a multi-layer unit manner. For example, the user data may be determined as LSB data, CSB data, or MSB data according to the logical page data information.

[0086] Reference Figure 7B ,and Fig. 7A The order of storing system data and user data may be changed depending on the illustrated figures. For example, user data may be stored in memory cells corresponding to the first column C1 to the mth column Cm, and system data may be stored in memory cells corresponding to the (m+1)th column Cm+1 to the (m+j)th column Cm+j.

[0087] Figure 8 is a diagram illustrating a schema of system data including index data according to an embodiment of the present disclosure.

[0088] Reference Figure 8 , the arrangement or pattern of the system data including the index data ID may vary depending on the page storing the index data ID. The page is represented by a word line. As described above, user data may be distinguished for word lines, which means that user data may be distinguished for pages represented by word lines. A data set including user data and system data related to the user data may be stored in a page represented by a word line. The arrangement of the index data ID within the system data of the data set may vary depending on the page storing the data set, which means that the arrangement of the index data ID within the system data may vary depending on the page storing the index data ID. The first word line address ADD_WL1 to the fourth word line address ADD_WL4 will be described as an example. The first data set 1 st data set to the fourth data set 4 thThe data set may be stored in a first page 1PG to a fourth page 4PG respectively represented by a first word line WL1 to a fourth word line WL4. The index data ID to be stored in the first page 1PG may be stored in a memory cell corresponding to the second column C2, and the index data ID to be stored in the second page 2PG may be stored in a column different from the second column C2. For example, the index data ID to be stored in the second page 2PG may be stored in a memory cell corresponding to the first column C1. When the index data ID to be stored in the second page 2PG is stored in the first column C1, the index data ID to be stored in the third page 3PG may be stored in a second column C2 different from the first column C1. Other page information PIF other than the index data ID in the system data may be stored in memory cells of other columns among the columns allocated to the system data except for the column of the memory cell allocated to store the index data ID.

[0089] A method for transmitting a data set generated by a memory controller to a memory device will be described in detail as follows.

[0090] Fig.9A and Fig. 9B is a diagram illustrating a method for transmitting a data set generated by a memory controller to a memory device according to an embodiment of the present disclosure.

[0091] exist Fig.9A , a method of converting a first data set 1 st The data set is stored in a group of memory cells, such as a first page connected to a first word line WL1. Fig. 9B In the first data set 1, st After the data set is stored in the first page, the second data set 2 nd The data set is stored in a group of memory cells, such as a second page connected to a second word line WL2.

[0092] Reference Fig.9A , the user data manager 52 may transfer the inverted or non-inverted first user data 1UDT to the system memory 56, and the system data manager 53 may transfer the first system data 1SDT associated with the first user data 1UDT to the system memory 56. When the address manager 54 transfers the first word line address 1ADD_wl of the word line representing the first page and associated with the first user data 1UDT to the system memory 56, the system memory 56 may transfer the first data set 1ADD_wl including the first user data 1UDT and the first system data 1SDT to the system memory 56. stThe memory interface 58 can transmit the first data set 1 data set corresponding to the first word line address 1ADD_wl to the memory interface 58. st The data set is transferred to the memory device MD.

[0093] When the first data set is input, the memory device MD may store the first system data 1SDT in the memory cells included in the first sub-block 1SB among the memory cells connected to the first word line WL1 and store the first user data 1UDT in the memory cells included in the second sub-block 2SB among the memory cells connected to the first word line WL1. The memory cells storing the first system data 1SDT and the memory cells storing the first user data 1UDT may configure a first page.

[0094] Reference Fig. 9B When the first data set is stored in the first page, the user data manager 52 may transmit the inverted or non-inverted second user data 2UDT to the system memory 56, and the system data manager 53 may transmit the second system data 2SDT related to the second user data 2UDT to the system memory 56. When the address manager 54 transmits the second word line address 2ADD_wl of the word line representing the second page and related to the second user data 2UDT to the system memory 56, the system memory 56 may transmit the second data set 2ADD_wl including the second user data 2UDT and the second system data 2SDT to the system memory 56. nd The memory interface 58 can transmit the second data set 2 data set corresponding to the second word line address 2ADD_wl to the memory interface 58. nd The data set is transferred to the memory device MD.

[0095] When the second data set is input, the memory device MD may store the second system data 2SDT in the memory cells included in the first sub-block 1SB among the memory cells connected to the second word line WL2 and store the second user data 2UDT in the memory cells included in the second sub-block 2SB among the memory cells connected to the second word line WL2. The memory cells storing the second system data 2SDT and the memory cells storing the second user data 2UDT may configure a second page.

[0096] According to the above method, system data can be stored in a selected area (ie, first sub-block 1SB) within a memory block of a memory device, and the modes of the system data stored in the selected area can be implemented differently. Various modes of system data will be described as follows.

[0097] Fig.10 is a diagram showing a schema of system data according to the first embodiment of the present disclosure.

[0098] Reference Fig.10 , the system data may include an index data ID having a zigzag pattern. The index data may be selectively stored in a memory cell connected to the first bit line BL1 or the second bit line BL2. For example, the index data ID may be stored in a memory cell connected to the second bit line BL2 in the odd-numbered word lines WL1, WL3, WL5, ..., and WLn, and the index data ID may be stored in a memory cell connected to the first bit line BL1 in the even-numbered word lines WL2, WL4, WL6, ..., and WLn-1. That is, the index data ID may be stored in the memory cell in a zigzag pattern so that the same index data ID is not stored in memory cells that are located in the same column and adjacent to each other in the row direction.

[0099] Fig.11 is a diagram illustrating a schema of system data according to the second embodiment of the present disclosure.

[0100] Reference Fig.11 , the system data may include an index data ID having a zigzag pattern, and the index data ID may be selectively stored in a memory cell connected to the third bit line BL3 or the fourth bit line BL4. For example, the index data ID may be stored in a memory cell connected to the fourth bit line BL4 among the odd-numbered word lines WL1, WL3, WL5, ..., and WLn, and the index data ID may be stored in a memory cell connected to the third bit line BL3 among the even-numbered word lines WL2, WL4, WL6, ..., and WLn-1. That is, in reference to Fig.11 In the described second embodiment, the index data ID may be stored in the memory cell of the column corresponding to the midpoint of the first sub-block 1SB.

[0101] Fig.12 is a diagram illustrating a schema of system data according to the third embodiment of the present disclosure.

[0102] Reference Fig.12 , the system data may include index data having a pattern proportional to the addresses of the word lines and columns in the first sub-block 1SB. A case where each page included in the first sub-block 1SB is configured as 6 bits will be described as an example. The first bit line BL1 to the sixth bit line BL6 may be connected to the first sub-block 1SB. The serial number of the column increases as the serial number of the bit line increases. That is, the first bit line BL1 may correspond to the first column, and the second bit line BL2 may correspond to the second column. In this way, the sixth bit line BL6 may correspond to the sixth column.

[0103] The index data ID corresponding to the first word line WL1 to the sixth word line WL6 may be respectively stored in the memory cells where the first word line WL1 to the sixth word line WL6 overlap with the first bit line BL1 to the sixth bit line BL6. The index data ID corresponding to the word line from the seventh word line WL7 may be respectively stored in the memory cells where the word line overlaps with the first bit line BL1 to the sixth bit line BL6 again. For example, the index data ID may be respectively stored in the memory cells connected to the first word line WL1 and the first bit line BL1, the memory cells connected to the second word line WL2 and the second bit line BL2, the memory cells connected to the third word line WL3 and the third bit line BL3, the memory cells connected to the fourth word line WL3 and the fourth bit line BL4, the memory cells connected to the fifth word line WL5 and the fifth bit line BL5, and the memory cells connected to the sixth word line WL6 and the sixth bit line BL6. Since the sixth bit line BL6 is the bit line corresponding to the largest column of the first sub-block 1SB, the index data ID may be stored in the memory cell connected from the seventh word line WL7 to the first bit line BL1.

[0104] Fig.13 is a diagram illustrating a schema of system data according to a fourth embodiment of the present disclosure.

[0105] Reference Fig.13 , the system data may include an index data ID having a pattern proportional to the address of the word line and the column and a pattern inversely proportional to consecutive addresses of the word line and the column.

[0106] A case where each page included in the first sub-block 1SB is configured as 6 bits will be described as an example. The first bit line BL1 to the sixth bit line BL6 may be connected to the first sub-block 1SB. In the fourth embodiment, the index data ID may be stored in the memory cell in a pattern in which the serial number of the column increases from the smallest column to the largest column and then decreases from the largest column to the smallest column. That is, in proportion to the address of the word line, the pattern of the memory cell storing the index data ID may have a pattern in which the serial number of the column increases sequentially or decreases sequentially.

[0107] Fig.14 is a diagram illustrating a schema of system data according to a fifth embodiment of the present disclosure.

[0108] Reference Fig.14, the i-th memory block BLKi may include a plurality of groups GR1 to GR3 divided in the column direction. For example, the first page 1PG distinguished by the first word line WL1 may be divided into the first group GR1 to the third group GR3, and the second page 2PG distinguished by the second word line WL2 may be divided into the first group GR1 to the third group GR3. In this way, each of the first page 1PG to the eighth page 8PG may be divided into the first group GR1 to the third group GR3. Each of the different pages included in the different groups may be divided into the first sub-block 1SB and the second sub-block 2SB, and the system data about the user data of each group may be stored in the first sub-block 1SB included in the corresponding group. The system data may include an index data ID and page information, and the index data ID may have a pattern in which the index pattern ID is not stored in the memory cells of the same column in the pages adjacent to each other.

[0109] Fig.15 is a diagram illustrating a read operation according to an embodiment of the present disclosure.

[0110] Reference Fig.15 , when the host transmits a read request together with a logical address to the memory system (S151), the memory system may perform a read operation of the selected storage block according to the physical address corresponding to the logical address (S152). For example, a memory controller included in the memory system may generate a read command according to the read request and detect a physical address corresponding to the logical address. Subsequently, the memory controller may transmit the read command and the physical address to the memory device. The memory device may output a data set read by performing a read operation of the selected storage block according to the physical address to the memory controller.

[0111] The memory controller may check the index data ID included in the received data set and determine whether the user data included in the data set is non-inverted data or inverted data (S153). Since the column storing the index data has been changed according to the word line in the program operation, the memory controller may detect the index data ID from the system data according to the word line address corresponding to the received data set in the read operation.

[0112] When the index data ID is the first index data, the memory controller may determine the user data received from the memory device as non-inverted data. The memory controller outputs the user data received from the memory device to the host (S155).

[0113] In operation S153, when the index data ID is the second index data, the memory controller may determine the user data received from the memory device as inversion data. The memory controller may restore the inversion data received from the memory device to non-inversion data (S154), and output the non-inversion data as user data to the host (S155).

[0114] Fig.16 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0115] Reference Fig.16 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0116] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control a program operation, a read operation, or an erase operation of the memory device 2200, or control a background operation of the memory device 2200. The memory controller 2100 provides an interface between the memory device 2200 and the host Host. The memory controller 2100 may include Figure 5 The memory controller shown includes units 51 to 58, and the memory device 2200 can be connected with Figure 2 The memory devices MD shown are configured identically.

[0117] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) according to a specific communication protocol. The memory controller 2100 may communicate with an external device through at least one of various communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. The connector 2300 may be defined by at least one of the various communication protocols described above.

[0118] The memory device 2200 may be implemented using various nonvolatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0119] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to constitute a memory card. For example, the memory controller 2100 and the memory device 2200 may constitute a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC, and eMMC), an SD card (SD, Mini SD, Micro SD, and SDHC), and a Universal Flash Storage (UFS).

[0120] Fig.17 is a diagram illustrating a solid state drive (SDD) to which the memory device of the present disclosure is applied.

[0121] Reference Fig.17 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives a voltage through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0122] Fig.17 The flash memories 3221 to 322n shown can be used with Figure 2 The memory devices MD shown are configured identically. Fig.17 The SSD controller 3210 shown may include Figure 5 The memory controller 1200 shown includes units 51 to 58.

[0123] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. The signal may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal may be a signal defined by at least one of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WI-FI, Bluetooth, and NVMe.

[0124] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can receive power input from the host 3100 and charge. When the power supply from the host 3100 is not stable, the auxiliary power supply 3230 can provide power to the SSD 3200. The auxiliary power supply 3230 can be located in the SSD 3200, or located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the mainboard and provide auxiliary power to the SSD 3200.

[0125] The buffer memory 3240 may operate as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store information necessary for the operation of the SSD system 3000, and Figure 5 The system memory 56 is shown separate. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0126] According to the present disclosure, a phenomenon in which the same data is stored in flag cells of a column is prevented, thereby improving the reliability of a read operation of the flag cells.

[0127] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made in the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0128] In the above-described embodiments, all steps may be selectively performed, or some or part of the steps may be omitted. In each embodiment, the steps may not necessarily be performed in the order described and the steps may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0129] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these are only for the purpose of describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and there may be many variations within the concept and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure. Further, it is noted that, as those skilled in the art will recognize in view of the present disclosure, the present disclosure may be implemented in various ways by replacements, changes and modifications that fall within the scope of the appended claims.

Claims

1. A memory system, comprising: a memory block including a plurality of pages, wherein each of the plurality of pages includes a plurality of memory cells connected to a bit line and one of the word lines; An address manager outputs addresses corresponding to the plurality of pages, each of the addresses indicating a page among the plurality of pages where user data is to be stored; as well as a system data manager that generates index data corresponding to each of the addresses and outputs the index data and information about a memory unit to store the index data, respectively, the index data indicating whether the user data is inverted, The system data manager determines memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses among the addresses as memory cells to store index data corresponding to the consecutive addresses.

2. The memory system according to claim 1, wherein the memory block comprises: a first area storing system data including the index data corresponding to each of the addresses; as well as The second area stores the user data.

3. The memory system according to claim 1, further comprising: a cycle counter for counting the number of cycles of programming and erasing operations performed in the memory block; a user data manager, which maintains the user data as non-inverted data or changes the user data into inverted data according to the cycle number of the memory block; a system memory storing the user data and the system data and outputting a data set including the user data and the system data; as well as A memory interface outputs the data set to a memory device including the memory block.

4. The memory system of claim 3, wherein the user data manager: determining whether the number of cycles corresponds to a reference value; and When the number of cycles corresponds to the reference value, the user data is changed to the inversion data. The memory system according to claim 4 , wherein the reference value is set to an even number or an odd number.

6. The memory system of claim 1, wherein the system data manager: When the user data is maintained as non-inverted data, generating first index data to be included in the system data as information of the user data; and When the user data is changed into inverted data, second index data to be included in the system data is generated as information of the user data.

7. The memory system of claim 6, wherein a memory cell storing the first index data or the second index data is maintained in an erased state according to the first index data or a memory cell storing the first index data or the second index data is programmed according to the second index data.

8. The memory system of claim 1, wherein the system data manager: controlling the memory block to store the system data in a memory cell connected to a first bit line among memory cells connected to odd-numbered word lines among the word lines, and The memory block is controlled to store the system data in a memory cell connected to a second bit line among memory cells connected to an even-numbered word line among the word lines.

9. The memory system of claim 1, wherein the system data manager: controlling the memory block to store the system data in a memory cell connected to a first bit line among memory cells connected to a selected word line among the word lines, and The memory block is controlled to store the system data in a memory cell connected to a second bit line closest to the first bit line in the first direction among memory cells connected to a next word line closest to the selected word line in the second direction.

10. A memory system comprising: a memory device comprising a first memory cell connected to a first bit line and a first word line, a second memory cell connected to a second bit line adjacent to the first bit line and the first word line, a third memory cell connected to the first bit line and a second word line adjacent to the first word line, and a fourth memory cell connected to the second bit line and the second word line; as well as a memory controller that transmits a data set including index data to the memory device in a programming operation, the index data indicating whether the user data is inverted, The memory controller further generates the data set so that the index data is stored in the first to fourth memory units.

11. The memory system of claim 10, wherein the memory controller comprises: The system data manager allocates a memory cell connected to one of the first bit line and the second bit line for the index data included in each of the data sets according to the addresses of the first word line and the second word line.

12. The memory system of claim 11, wherein the system data manager further: allocating, for the index data, a memory cell connected to one of the first bit line and the second bit line from among the first memory cell and the second memory cell according to an address of the first word line; and The index data is allocated to a memory cell connected to one of the first bit line and the second bit line from among the first memory cell and the second memory cell according to the address of the second word line.

13. The memory system of claim 11, wherein the system data manager further: generating the index data as first index data when non-inverted data of user data to be stored in a fifth memory cell connected to the first word line and the second word line is transferred to the memory device; and When inverted data of the user data to be stored in the fifth memory unit is transferred to the memory device, the index data is generated as second index data. 14 . The memory system of claim 13 , wherein the first memory cell and the fourth memory cell are maintained in an erased state according to the first index data or are programmed according to the second index data. 15 . The memory system of claim 13 , wherein the system data manager further generates page information about the user data to be stored in the fifth memory unit and generates the data set so that the page information is stored in the fifth memory unit.

16. A memory system comprising: a storage block, comprising a first area storing index data and a second area storing user data, wherein the index data indicates whether the user data is inverted; A peripheral circuit, programming the index data and the user data in the storage block; as well as a memory controller that generates the index data according to the state of the user data and transmits the user data and the index data to the peripheral circuit, wherein the index data has a predetermined bit size, and The index data is stored in memory cells connected to different bit lines in the first region. The memory system of claim 16 , wherein the index data stored in the first area are the same. 18 . The memory system of claim 16 , wherein the index data is stored in a memory cell coupled to a cross point of a different bit line and a different word line connected to the first region. 19 . The memory system according to claim 16 , wherein the memory controller further changes positions of the memory cells in a column direction where the index data is to be stored according to addresses of pages where the index data is to be stored.

20. The memory system according to claim 19, wherein the memory controller inverts the user data, and wherein the memory controller generates the index data when the memory controller transmits the inverted user data to the peripheral circuit.

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