A vision-based method, system and storage medium for detecting defects in IC chips

Abstract

This invention discloses a vision-based method, system, and storage medium for detecting defects in IC chips. The invention first processes an image of a normal IC chip product to obtain a template image I. M and line template image I BM Next, an image of the IC chip product to be tested is captured and processed to obtain the affine transformation coefficients C and the approximate detection area R of the IC chip product to be tested. Then, within the approximate detection area R of the IC chip product to be tested, the line binary diagram I of the image I of the IC chip product to be tested is obtained through further processing. BI Then, an affine transformation is performed to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC Then, the connected components are labeled; finally, the binary graph of the line I is... BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to I and single-strand line and I BC The number of connected components or I in the corresponding region BC single-strand line and I and The defect of the IC chip product under test is determined by whether the number of connected components in the corresponding region is greater than 1.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of image processing, and particularly relates to a vision-based IC chip defect detection method, system and storage medium. BACKGROUND

[0002] In the production process of IC chips, various defects will inevitably occur due to various factors and production processes, and the defects of metal circuit disconnection and short circuit will cause the product to be unusable and generate waste products. Therefore, after the packaging process of the IC chip is completed, it needs to be strictly detected, and how to improve the product quality and reduce the unqualified rate of the final product in the production process has become the goal that the industry constantly pursues.

[0003] At present, there are mainly two forms of IC chip defect detection: one is the traditional manual detection method, which detects the defects of the product by visual inspection of the human eye combined with the understanding of the workers to the defects, and this method has low detection efficiency and is dependent on the understanding degree of the workers to the defects, and is easy to miss detection. Non-contact detection, such as automatic optical detection system (AOI), is an important research direction in this type of method, but in the current vision-based method, ordinary template comparison or image subtraction method is mostly used to detect the disconnection and short circuit of the IC chip, and when the template matching error occurs or the product itself has a tolerance, this type of method will lead to missed detection or false detection.

[0004] Therefore, it is necessary to develop a vision-based IC chip defect detection method to solve the above technical problems. SUMMARY

[0005] The purpose of the present application is to overcome the shortcomings of the prior art, and provide a vision-based IC chip defect detection method, system and storage medium. The existing vision-based method mostly uses ordinary template comparison or image subtraction method to detect the disconnection and short circuit of the IC chip, and when the template matching error occurs or the product itself has a tolerance, this type of method will lead to missed detection or false detection and other problems.

[0006] One purpose of the present application is to provide a vision-based IC chip defect detection method.

[0007] A vision-based IC chip defect detection method, comprising the following steps:

[0008] S1, obtaining K images of normal IC chip products and aligning, then performing weighted fusion on the aligned images to obtain a template image I M , performing binarization processing on the template image I M and extracting a line binary image thereof to obtain a line template image I BM ;

[0009] S2. Take an image of the IC chip product to be tested to obtain image I of the IC chip product to be tested, and then use the template matching method to obtain template image I. M The affine transformation coefficients C of the image I of the IC chip product to be tested and the approximate detection area R of the IC chip product to be tested;

[0010] S3. Within the approximate detection area R of the IC chip product to be tested, a threshold-based binarization method is used to obtain the line binary image I of the IC chip product image I. BI Then, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC And mark its connected components;

[0011] S4. Transform the binary image of the line into I. BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line I and The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

[0012] Furthermore, in step S1, the value of K ranges from 50 to 500.

[0013] Further, in step S1, the alignment method is as follows: select one of the product images with a near-horizontal angle as the reference image, and align the remaining images with the reference image using an affine transformation method.

[0014] Furthermore, in step S2, the template matching method is a shape-based template matching method.

[0015] Furthermore, in step S4, based on the binary diagram of the line I... and China and I BC The method for determining defects in the IC chip product under test by checking whether the number of connected components in the region corresponding to a single line is greater than 1 is as follows: Sequentially convert the binary graph of the line into I... and China and I BC The area R corresponding to a single line in the middle i , (i = [1:N bc ], N bc For I BC Extract the number of connected components in the middle path and calculate R. iThe number of connected domains M, if M>1, judges that R i exists a short circuit defect, thereby determining that the IC chip product to be detected exists a short circuit defect.

[0016] Further, in step S4, according to whether the number of connected domains of the region corresponding to a single line in the line binary image Iand in the IBC is greater than 1, the method for judging the defect of the IC chip product to be detected is as follows: the region Rj corresponding to a single line in the line binary image Iand in the IBC is extracted in turn, and the number of connected domains N of Rj is calculated, if N>1, it is judged that Rj exists a short circuit defect, thereby determining that the IC chip product to be detected exists a short circuit defect.

[0017] The application also provides an IC chip defect detection system based on vision, which comprises:

[0018] A line template image acquisition unit: acquiring images of K normal IC chip products and aligning, then performing weighted fusion on the aligned images to obtain a template image I M , performing binaryzation processing on the template image I M and extracting a line binary image to obtain a line template image I BM ;

[0019] An IC chip product to be detected processing unit: taking images of the IC chip product to be detected to obtain an IC chip product to be detected image I, then adopting a template matching method to obtain an affine transformation coefficient C of the template image I M to the IC chip product to be detected image I and a rough detection region R of the IC chip product to be detected;

[0020] An affine transformation unit: in the rough detection region R of the IC chip product to be detected, a threshold-based binaryzation method is adopted to obtain a line binary image I BI of the IC chip product to be detected image I, then performing affine transformation on the line template image I BM and the affine transformation coefficient C to obtain a line template I BM projected on the IC chip product to be detected image I BC , and performing connected domain marking on it;

[0021] An IC chip defect judging unit: performing intersection on the line binary image I BI and I BC to obtain a line binary image I and after intersection, according to the number of connected domains of the region corresponding to a single line in the line binary image I and or I BC , or the number of connected domains of the region corresponding to a single line in the line binary image I BCBinary diagram of the line I and The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

[0022] Finally, the present invention provides a storage medium for storing a computer program, which is loaded by a processor to execute the detection method described in any of the preceding claims.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] This invention first processes the image of a normal IC chip product to obtain template image I. M and line template image I BM Next, an image of the IC chip product to be tested is captured and processed to obtain the affine transformation coefficients C and the approximate detection area R of the IC chip product to be tested. Then, within the approximate detection area R of the IC chip product to be tested, the line binary diagram I of the image I of the IC chip product to be tested is obtained through further processing. BI Next, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC Then, the connected components are labeled; finally, the binary graph of the line I is... BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line I and The system determines the defects of the IC chip by checking whether the number of connected regions corresponding to a single line is greater than 1. The entire process is non-contact and automated, which can reduce secondary damage to the product and improve testing efficiency. At the same time, it is not affected by matching errors and can more accurately detect open circuit and short circuit defects in IC chip products. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of the vision-based IC chip defect detection method of the present invention;

[0027] Figure 2 This is a framework diagram of the vision-based IC chip defect detection system of the present invention;

[0028] Figure 3 This is a flowchart of the vision-based IC chip open circuit defect detection process of the present invention.

[0029] Figure 4 This is a flowchart of the vision-based IC chip short-circuit defect detection process of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1 A vision-based method for detecting defects in IC chips includes the following steps:

[0032] S1. Obtain K images of normal IC chip products and align them. Then, perform weighted fusion on the aligned images to obtain template image I. M For template image I M Binarization is performed and the binary image of the line is extracted to obtain the line template image I. BM ;

[0033] S2. Take an image of the IC chip product to be tested to obtain image I of the IC chip product to be tested, and then use the template matching method to obtain template image I. M The affine transformation coefficients C of the image I of the IC chip product to be tested and the approximate detection area R of the IC chip product to be tested;

[0034] S3. Within the approximate detection area R of the IC chip product to be tested, a threshold-based binarization method is used to obtain the line binary image I of the IC chip product image I. BI Then, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC And mark its connected components;

[0035] S4. Transform the binary image of the line into I. BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and IBC The number of region connected domains corresponding to a single line or I BC The line binary image I and The number of region connected domains corresponding to a single line is greater than 1, so as to determine the defects of the IC chip product to be detected.

[0036] Specifically, in step S1, the value range of K is 50-500. In the present scheme, the selection can be made according to the fusion image effect. Starting from 50, if the fusion image effect is not good, it is increased. The purpose is mainly to eliminate the burr phenomenon of the line through the fusion of multiple images, so that the line template image is more accurate.

[0037] Specifically, in step S1, the alignment method is as follows: one of the product images with an angle close to horizontal is selected as a reference image, and the other remaining images are aligned with the reference image through an affine transformation method.

[0038] Specifically, the template matching method is a shape-based template matching method. It should be noted that although the shape-based template matching method is used in the present scheme, other conventional template matching methods are also within the protection scope of the present application.

[0039] Specifically, please continue to refer to Figure 1 and Figure 3 In step S4, according to the line binary image I and The number of region connected domains corresponding to a single line is greater than 1, so as to determine the defects of the IC chip product to be detected. BC The number of region connected domains corresponding to a single line is greater than 1, so as to determine the defects of the IC chip product to be detected. and The line binary image I BC The region R i (i=[1:N bc ], N bc is the number of line connected domains in I BC ) corresponding to a single line is extracted, and the number M of connected domains of R i is calculated. If M>1, it is judged that there is an open circuit defect in R i , so as to determine that the IC chip product to be detected has an open circuit defect.

[0040] Specifically, please continue to refer to Figure 1 and Figure 4In step S4, the method for determining the defect of the IC chip product under test based on whether the number of connected components corresponding to a single line in the IBC and the binary line graph Iand is greater than 1 is as follows: The region Rj corresponding to a single line in the IBC and the binary line graph Iand is extracted sequentially (j = [1:Nand], where Nand is the number of connected components in the binary line graph Iand), and the number of connected components N in Rj is calculated. If N > 1, it is determined that there is a short circuit defect in Rj, thereby determining that there is a short circuit defect in the IC chip product under test.

[0041] Please continue reading. Figure 2 The present invention also provides a vision-based IC chip defect detection system, the detection system comprising: a circuit template image acquisition unit 301, an IC chip product processing unit 302, an affine transformation unit 303, and an IC chip defect judgment unit 304;

[0042] The line template image acquisition unit acquires K images of normal IC chip products and aligns them. Then, it performs weighted fusion of the aligned images to obtain template image I. M For template image I M Binarization is performed and the binary image of the line is extracted to obtain the line template image I. BM ;

[0043] The IC chip product processing unit under test captures an image of the IC chip product under test to obtain image I of the IC chip product under test, and then uses a template matching method to obtain template image I. M The affine transformation coefficients C of the image I of the IC chip product to be tested and the approximate detection area R of the IC chip product to be tested;

[0044] The affine transformation unit uses a threshold-based binarization method within the approximate detection area R of the IC chip product to be tested, to obtain a line binary image I of the IC chip product image I. BI Then, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC And mark its connected components;

[0045] The IC chip defect determination unit will determine the circuit binary diagram I. BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line Iand The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

[0046] The present invention also provides a storage medium for storing a computer program, which is loaded by a processor to execute the detection method described in any of the preceding claims. For example, the computer program, when loaded by a processor, can perform the following steps:

[0047] Acquire K images of normal IC chip products and align them. Then, perform weighted fusion on the aligned images to obtain template image I. M For template image I M Binarization is performed and the binary image of the line is extracted to obtain the line template image I. BM The image of the IC chip product to be tested is obtained by taking an image of the IC chip product to be tested, and then a template image I is obtained by using a template matching method. M The affine transformation coefficients C of the IC chip product image I to be tested and the approximate detection area R of the IC chip product to be tested are obtained. In the approximate detection area R of the IC chip product to be tested, a threshold-based binarization method is used to obtain the line binary map I of the IC chip product image I to be tested. BI Then, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC And mark the connected components of it; transform the binary graph of the line I BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line I and The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

[0048] The computer-readable storage medium can be an internal storage unit of the image processing device described in the foregoing embodiments, such as a hard disk or memory of the image processing device. Alternatively, the computer-readable storage medium can be an external storage device of the image processing device, such as a pluggable hard disk, SmartMediaCard (SMC), SecureDigital (SD) card, or FlashCard.

[0049] The above examples are only specific embodiments of the present application, used to illustrate the technical solutions of the present application, but not limit the present application, the protection scope of the present application is not limited to this, although the present application is described in detail with reference to the foregoing examples, those skilled in the art should understand that any person skilled in the art within the technical range disclosed by the present application, still can modify or easily think of changes to the technical solutions recorded in the foregoing examples, or equivalent replacement of part of the technical features, and these modifications, changes or replacement do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, all should be covered in the protection scope of the present application.

Claims

1. A vision-based method for detecting defects in IC chips, characterized in that, Includes the following steps: S1. Obtain K images of normal IC chip products and align them. Then, perform weighted fusion on the aligned images to obtain template image I. M For template image I M Binarization is performed and the binary image of the line is extracted to obtain the line template image I. BM ; S2. Take an image of the IC chip product to be tested to obtain image I of the IC chip product to be tested, and then use the template matching method to obtain template image I. M The affine transformation coefficients C of the image I of the IC chip product to be tested and the approximate detection area R of the IC chip product to be tested; S3. Within the approximate detection area R of the IC chip product to be tested, a threshold-based binarization method is used to obtain the line binary image I of the IC chip product image I. BI Then, the line template image I BM The circuit template I is obtained by performing an affine transformation using the affine transformation coefficients C. BM Projection I on the image I of the IC chip product to be tested BC And mark its connected components; S4. Transform the binary image of the line into I. BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line I and The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

2. The vision-based IC chip defect detection method according to claim 1, characterized in that, In step S1, the value of K ranges from 50 to 500.

3. The vision-based IC chip defect detection method according to claim 1, characterized in that, In step S1, the alignment method is as follows: select one of the product images with a near-horizontal angle as the reference image, and align the remaining images with the reference image using an affine transformation method.

4. The vision-based IC chip defect detection method according to claim 1, characterized in that, In step S2, the template matching method is a shape-based template matching method.

5. The vision-based IC chip defect detection method according to claim 1, characterized in that, In step S4, according to the binary diagram of the line I and China and I BC The method for determining defects in the IC chip product under test by checking whether the number of connected components in the region corresponding to a single line is greater than 1 is as follows: Sequentially convert the binary graph of the line into I... and China and I BC The area R corresponding to a single line in the middle i Extracted, where i=[1:N bc ], N bc For I BC The number of connected components in the middle path; and calculate R. i The number of connected components M; if M > 1, then determine R. i The presence of an open circuit defect indicates that the IC chip under test has an open circuit defect.

6. The vision-based IC chip defect detection method according to claim 1, characterized in that, In step S4, according to I BC Binary diagram of the line I and The method for determining defects in the IC chip product under test by checking whether the number of connected components corresponding to a single line in the test area is greater than 1 is as follows: Sequentially connect the I... BC Binary diagram of the line I and The area R corresponding to a single line in the middle j Extracted, where j=[1:N and ], N and Binary diagram of the line I and The number of connected components in the middle path; and calculate R. j Given the number of connected components N, if N > 1, then determine R. j The presence of a short-circuit defect confirms that the IC chip under test has a short-circuit defect.

7. A vision-based IC chip defect detection system, characterized in that, The detection system includes: The circuit template image acquisition unit acquires K images of normal IC chip products, aligns them, and then performs weighted fusion of the aligned images to obtain the template image I. M For template image I M Binarization is performed and the binary image of the line is extracted to obtain the line template image I. BM ; The IC chip product processing unit under test: captures an image of the IC chip product under test to obtain image I, and then uses a template matching method to obtain template image I. M The affine transformation coefficients C of the image I of the IC chip product to be tested and the approximate detection area R of the IC chip product to be tested; Affine Transformation Unit: Within the approximate detection area R of the IC chip product to be inspected, a threshold-based binarization method is used to obtain the line binary image I of the IC chip product image I. BI Then, the line template image I BM The affine transformation is performed on the affine transformation coefficients C to obtain the circuit template I. BM Projection I on the image I of the IC chip product to be tested BC And mark its connected components; IC chip defect detection unit: The binary circuit diagram I... BI and I BC Find the intersection to obtain the binary graph I of the intersecting lines. and According to the binary diagram of the line I and China and I BC The number of connected domains or I corresponding to a single line in the middle BC Binary diagram of the line I and The defect of the IC chip product under test is determined by whether the number of connected domains in the area corresponding to a single line is greater than 1.

8. A storage medium, characterized in that, The storage medium is used to store a computer program, which is loaded by a processor to execute the detection method according to any one of claims 1 to 6.

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