The invention provides an image processor-combined algorithm for speed restriction board detection during automatic driving. An image with the resolution of 1600*1200 is reduced to an image with the resolution of 1200*900, and a red image with a similar red color as a speed restriction board is obtained by means of CUDA C language on a CPU and is given back to the CPU. A connected-component analysis algorithm is used to obtain information of each connected component, such as the position. Then, on the original color image with the resolution of 1600*1200, a judgment is made whether each connected component is a speed restriction board or not, by means of a support vector machine classifier. Finally, positions and pixel sizes of all speed restriction boards in the original image with the resolution of 1600*1200 are obtained. The invention proposes that a part of steps of the detection algorithm, where parallel computing is easy, are executed on the CPU, and in combination with calculation advantages of a central processing unit and an image processor, serial and parallel computing is carried out at the same time, thereby improving the speed restriction board detection rate and the speed restriction board detection speed. The algorithm of the invention has the advantages of high running frame rate, short development cycle, easy understanding and convenient maintenance.