Array substrate motherboard, display panel and manufacturing method thereof, and display device

Abstract

Embodiments of the present application provide an array substrate motherboard, a display panel, a method for manufacturing the same, and a display device. The array substrate motherboard includes a substrate, a panel layer, and a protective film layer. The panel layer is located on one side of the substrate and includes multiple panel areas and spacer areas located outside the panel areas. The thickness of the panel areas is greater than that of the spacer areas, thereby forming recesses in the spacer areas. The protective film layer is located on a side of the panel layer away from the substrate and covers the multiple panel areas and the spacer areas. The side of the protective film layer closer to the panel layer is provided with protrusions corresponding to the recesses, and the protrusions fill the recesses. In the above-mentioned array substrate motherboard, the protrusions can reduce the thickness difference between the panel areas and the spacer areas, thereby reducing the probability of bubbles forming between the protective film layer, the panel areas, and the spacer areas. This further reduces the difficulty of the array substrate motherboard cutting process and improves the yield of the array substrate and display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate motherboard, a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] This section merely provides background information related to the present application and is not necessarily prior art.

[0003] In the actual mass production manufacturing process for display devices, a larger array substrate motherboard (i.e., array motherboard) is typically formed first. This array substrate is then cut into individual array substrates. In related art, to protect the array substrate motherboard during the cutting process and prevent abrasion from cutting debris, a protective film is often applied to the array substrate motherboard before cutting. However, bubbles may form between the protective film and the array substrate motherboard, hindering the cutting of the array substrate motherboard and causing problems such as cutting difficulties, which in turn affects the yield of the array substrate and display panel. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide an array substrate motherboard, a display panel, a manufacturing method thereof, and a display device to reduce the difficulty of the array substrate motherboard cutting process and improve the yield of the array substrate and display panel. The specific technical solution is as follows:

[0005] An embodiment of a first aspect of the present application provides an array substrate motherboard, the array substrate motherboard comprising:

[0006] substrate;

[0007] a panel layer, the panel layer being located on one side of the substrate, the panel layer comprising a plurality of panel areas, and a spacer area located at the periphery of the panel area, wherein the thickness of the panel area is greater than that of the spacer area so as to form a recessed portion at the spacer area;

[0008] A protective film layer is provided on a side of the panel layer away from the substrate, the protective film layer covers the multiple panel areas and the spacer areas, and a protrusion corresponding to the concave portion is provided on a side of the protective film layer close to the panel layer, and the protrusion fills the concave portion.

[0009] In some embodiments, the protective film layer includes a base film layer and a first adhesive layer located between the base film layer and the panel layer, and the protrusion is provided on a side of the first adhesive layer close to the panel layer.

[0010] In some embodiments, the depth of the recess is 3 μm to 7 μm.

[0011] In some embodiments, the protective film layer has a thickness of 25 μm to 35 μm.

[0012] In some embodiments, the panel area includes a display area and a bending area located on one side of the display area, the thickness of the bending area is smaller than the thickness of the display area, and the thickness of the bending area is greater than the thickness of the spacer area;

[0013] The concave portion includes a first portion and a second portion. The projection of the first portion on the substrate covers the projection of the spacing region on the substrate. The projection of the second portion on the substrate covers the projection of the bending region on the substrate.

[0014] In some embodiments, the second portion has a depth of 1 μm to 3 μm.

[0015] An embodiment of a second aspect of the present application provides a display panel, comprising an array substrate cut from any of the above-mentioned array substrate motherboards.

[0016] An embodiment of a second aspect of the present application provides a method for manufacturing a display panel, the method comprising:

[0017] providing a substrate;

[0018] A plurality of panel areas are formed on one side of the substrate, and a spacer area is formed on one side of the substrate and is located outside the panel area, wherein the thickness of the panel area is greater than that of the spacer area so as to form a recessed portion at the spacer area;

[0019] A protective film layer is covered on a side of the plurality of panel areas and the spacer area away from the substrate, and a protrusion corresponding to the concave portion is provided on a side of the protective film layer close to the panel layer, and the protrusion fills the concave portion;

[0020] cutting the substrate and the protective film layer along an extending direction of the spacer region to obtain a plurality of array substrates;

[0021] peeling off the protective film layer on the array substrate;

[0022] A cover layer is provided on a side of the array substrate away from the substrate.

[0023] In some embodiments, the step of forming a plurality of panel areas on one side of the substrate includes:

[0024] forming a first buffer layer on one side of the substrate;

[0025] forming a thin film transistor array layer on a side of the buffer layer away from the substrate;

[0026] forming a first planarization layer on a side of the thin film transistor array layer away from the substrate;

[0027] forming a light-emitting layer on a side of the planarization layer away from the substrate;

[0028] A packaging layer covers the side of the light emitting layer away from the substrate.

[0029] In some embodiments, the step of forming a thin film transistor array layer on a side of the buffer layer away from the substrate includes:

[0030] forming an active layer on a side of the buffer layer away from the substrate;

[0031] forming a first insulating layer on a side of the active layer away from the substrate;

[0032] forming a first metal layer on a side of the first insulating layer away from the substrate, and patterning the first metal layer to form a gate;

[0033] forming a second insulating layer on a side of the first metal layer away from the substrate;

[0034] A second metal layer is formed on a side of the second insulating layer away from the substrate, and the second metal layer is patterned to form a source electrode and a drain electrode, wherein the source electrode or the drain electrode is connected to the active layer through a via hole.

[0035] In some embodiments, the step of forming a spacer region on one side of the substrate and located outside the panel region includes:

[0036] forming a second buffer layer on one side of the substrate, wherein the second buffer layer is disposed on the same layer as the first buffer layer;

[0037] forming a third insulating layer on a side of the second buffer layer away from the substrate, wherein the third insulating layer is provided on the same layer as the first insulating layer;

[0038] forming a fourth insulating layer on a side of the third insulating layer away from the substrate, wherein the fourth insulating layer is provided on the same layer as the second insulating layer;

[0039] A second planarization layer is formed on a side of the third insulating layer away from the substrate, and the second planarization layer is arranged on the same layer as the first planarization layer.

[0040] An embodiment of the third aspect of the present application provides a display device, which includes the above-mentioned display panel, or a display panel manufactured according to any of the above-mentioned display panel manufacturing methods.

[0041] Beneficial effects of the embodiments of the present application:

[0042] In an array substrate motherboard provided in an embodiment of the present application, the array substrate motherboard includes a substrate, a panel layer located on the substrate, and a protective film layer covering the panel layer, wherein the panel layer includes a plurality of panel areas and a spacer area surrounding the periphery of the panel area, the spacer area is used to separate adjacent panel areas, and the spacer area is also used to provide a cutting area for the array substrate motherboard. The panel area is used to form an array substrate after the array substrate motherboard is cut. The thickness difference between the panel area and the spacer area causes a recess to be formed at the spacer area, and a protrusion is provided at a position corresponding to the recess on the protective film layer. When the protective film layer is covered on the panel layer, the protrusion on the protective film layer can fill the recess. In the embodiment of the present application, since the protrusion on the protective film layer can fill the recess at the spacer area, the protrusion can reduce the thickness difference between the panel area and the spacer area, thereby reducing the probability of bubbles generated between the protective film layer and the panel area and the spacer area, thereby reducing the difficulty of the cutting process of the array substrate motherboard and improving the yield of the array substrate and the display panel.

[0043] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0045] Figure 1 A schematic structural diagram of an array substrate motherboard in some embodiments of the present application;

[0046] Figure 2 For the Figure 1 A cross-sectional view in the AA direction;

[0047] Figure 3 For the Figure 1 Another cross-sectional view in the AA direction;

[0048] Figure 4 For the Figure 1 A cross-sectional view in the middle DD direction;

[0049] Figure 5 A flow chart of a method for manufacturing a display panel in some embodiments of the present application;

[0050] Figure 6 A schematic structural diagram of a display panel in some embodiments of the present application;

[0051] Figure 7 For the Figure 1A cross-sectional view in the middle BB direction;

[0052] Figure 8 For the Figure 1 A cross-sectional view in the CC direction. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0054] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0055] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates otherwise, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0056] For ease of description, spatially relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures, such as "inside," "outside," "inside," "outside," "below," "below," "above," and the like. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "below" another element or feature would then be oriented as "above" or "above" another element or feature. Thus, the example term "below" may include both above and below orientations. The device may be oriented otherwise, such as rotated 90 degrees or in other orientations, and the spatially relative descriptors used herein are interpreted accordingly.

[0057] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0058] In order to reduce the difficulty of the cutting process of the array substrate motherboard and improve the yield of the array substrate and display panel, the embodiments of the present application provide an array substrate motherboard, a display panel, a manufacturing method thereof, and a display device. The array substrate motherboard, the display panel, a manufacturing method thereof, and the display device provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Among them, the display panel is composed of an array substrate formed by cutting the array substrate motherboard, as well as other layer structures such as a polarizer and a glass cover. The display panel includes but is not limited to an LCD (Liquid Crystal Display) display panel, a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) display panel, an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light-Emitting Diodes) display panel, a miniLED (mini Light-Emitting Diode) display panel, and a micro LED (micro Light-Emitting Diode) display panel.

[0059] The embodiment of the first aspect of the present application provides an array substrate motherboard, such as Figures 1 to 4 As shown, the array substrate motherboard includes a substrate 1, a panel layer 2, and a protective film layer 3. The panel layer 2 is located on one side of the substrate 1 and includes multiple panel areas 21 and spacer areas 22 located outside the panel areas 21. The thickness H1 of the panel areas 21 is greater than the thickness H2 of the spacer areas 22, forming recesses 23 in the spacer areas 22. The protective film layer 3 is located on the side of the panel layer 2 away from the substrate 1. The protective film layer 3 covers the multiple panel areas 21 and the spacer areas 22. The side of the protective film layer 3 close to the panel layer 2 is provided with protrusions 31 corresponding to the recesses 23, and the protrusions 31 fill the recesses 23.

[0060] In the embodiment of this application, Figure 2 and Figure 3 As shown, the thickness H1 of the panel area 21 is greater than the thickness H2 of the spacer area 22. Therefore, there is a thickness difference between the panel area 21 and the spacer area 22. This thickness difference causes a recess 23 to be formed on the array substrate motherboard in the spacer area 22. Furthermore, the depth of the recess 23 is the thickness difference between the panel area 21 and the spacer area 22.

[0061] The protrusion 31 is located on the protective film layer 3 at a position corresponding to the recess 23. The shape of the protrusion 31 is substantially the same as that of the recess 23, and the size of the protrusion 31 is also the same as or slightly smaller than that of the recess 23, so that the protrusion 31 can fill the recess 23. Optionally, the thickness of the protrusion 31 is less than the depth of the recess 23, and the protrusion 31 can partially fill the recess 23. Optionally, the thickness of the protrusion 31 is equal to the depth of the recess 23, and the protrusion 31 can completely fill the recess 23.

[0062] In the embodiment of the present application, the substrate 1 may be a rigid substrate, such as a glass substrate, etc.; the substrate 1 may also be a flexible substrate, such as polyimide, etc., which is not limited in the present application.

[0063] In the embodiment of this application, Figure 1 As shown, the spacer 22 extends along the long and short sides of the array substrate motherboard to separate the panel areas 21 adjacent to each other along the long and short sides. The spacer 22 also provides a cutting area for the array substrate motherboard. The panel area 21 is used to form array substrates after the array substrate motherboard is cut, thereby forming a display panel including the array substrate. The thickness difference between the panel area 21 and the spacer 22 forms a recess 23 in the spacer 22. A protrusion 31 is provided on the protective film layer 3 at a position corresponding to the recess 23. When the protective film layer 3 is covered on the panel layer 2, the protrusion 31 on the protective film layer 3 can fill the recess 23. Because the protrusion 31 on the protective film layer 3 can fill the recess 23 in the spacer 22, the protrusion 31 can reduce the thickness difference between the panel area 21 and the spacer 22, thereby reducing the probability of bubbles forming between the protective film layer 3 and the panel area 21 and the spacer 22. This reduces the difficulty of the array substrate motherboard cutting process and improves the yield of the array substrate and display panel.

[0064] In some embodiments, such as Figure 2 As shown, the protective film layer 3 includes a base film layer 32 and a first adhesive layer 33 located between the base film layer 32 and the panel layer 2 , and the protrusion 31 is provided on a side of the first adhesive layer 33 close to the panel layer 2 .

[0065] In the embodiment of the present application, the base film layer 32 is used to cover the panel layer 2 to protect the panel layer 2 during the process of cutting the array substrate motherboard, thereby reducing the probability of the array substrate motherboard being contaminated. The first adhesive layer 33 is used to bond and connect the panel layer 2 and the base film layer 32 to reduce the probability of the base film layer 32 falling off the panel layer 2 or being misaligned with the panel layer 2 during the process of cutting the array substrate motherboard. Furthermore, the base film layer can be a polyethylene film layer, etc. The first adhesive layer 33 can be a PSA (Pressure Sensitive Adhesive) adhesive layer. When the base film layer 32 and the panel layer 2 are connected by the PSA adhesive layer, the PSA adhesive layer can be pressurized by a tool such as a roller to make it have better adhesion. The first adhesive layer 33 can also be a silicone layer, a rubber layer, etc., which is not specifically limited in the embodiment of the present application.

[0066] In some embodiments, the depth H3 of the recess 23 is 3 μm to 7 μm.

[0067] In the embodiment of the present application, during the display panel fabrication process, the array substrate motherboard is cut along the extension direction of the spacer region 22. Panel region 21 is cut to form the array substrate, while spacer region 22 is removed during the display panel fabrication process. Therefore, the depth of recess 23 is 3 μm to 7 μm, making spacer region 22 thinner and reducing the difficulty of cutting. Furthermore, the depth H3 of recess 31 is related to the thickness difference between panel region 21 and spacer region 22. Therefore, the depth H3 of recess 23 is related to the type of display panel fabricated from the array substrate motherboard. The depth H3 of recess 23 can be 3 μm, 4 μm, and so on, and this application does not impose any limitations on this.

[0068] In some embodiments, the thickness of the protective film layer 3 is 25 μm to 35 μm.

[0069] In the embodiment of the present application, the thickness of the protective film layer 3 is the distance between the side of the protective film layer 3 closest to the panel layer 2 and the side of the protective film layer 3 farther from the panel layer 2, along a direction perpendicular to the substrate 1. The thickness of the protective film layer 3 is no greater than 35 μm, so that the protective film layer 3 is not too thick, thereby reducing the probability that the cutting process will be more difficult due to the excessive thickness of the protective film layer 3. In addition, the thickness of the protective film layer 3 is no less than 25 μm, which can increase the strength of the protective film layer 3, reduce the probability of damage to the protective film layer 3 during cutting and other processes, and facilitate the peeling of the protective film layer 3.

[0070] In some embodiments, such as Figure 4As shown, the panel area 21 includes a display area 211 and a bending area 212 located on one side of the display area 211. The thickness H4 of the bending area 212 is less than the thickness H5 of the display area 211, and the thickness H4 of the bending area 212 is greater than the thickness H2 of the spacer area 22. The recess 23 includes a first portion 231 and a second portion 232. The projection of the first portion 231 on the substrate 1 overlaps the projection of the spacer area 22 on the substrate 1, and the projection of the second portion 232 on the substrate 1 overlaps the projection of the bending area 212 on the substrate 1.

[0071] In an embodiment of the present application, the bending area 212 is located on one side of the display area 211. The bending area 212 is used to bond components such as driver chips, and can be bent toward the non-display side of the display panel after bonding components such as driver chips to reduce the border size of the display panel.

[0072] In the embodiment of the present application, along a direction perpendicular to the extension of the recess 23, the recess 23 may include adjacent and interconnected first and second portions 231 and 232. The width of the recess 23 may be substantially equal to the sum of the widths of the spacer 22 and the width of the bending region 212. The thickness H4 of the bending region 212 is greater than the thickness H2 of the spacer 22 and less than the thickness H5 of the display region 211. Therefore, the thickness difference between the bending region 212 and the display region 211 allows the second portion 232 to be formed in the bending region 212, and the thickness difference between the bending region 212 and the spacer 22 allows the bending region 212 to form the first portion 231 in the spacer 22. This results in the recess 23 having a stepped shape, creating a thickness transition between the display region 211 and the spacer 22. This further reduces the probability of bubbles forming between the protective film layer 3 and the panel region 21 and the spacer 22, thereby further reducing the difficulty of the array substrate motherboard cutting process and improving the yield of the array substrate and display panel.

[0073] In some embodiments, the depth H6 of the second portion 232 is 1 μm to 3 μm, that is, the thickness difference between the bending area 212 and the display area 211 is 1 μm to 3 μm, so that the bending area 212 can achieve a thickness transition between the display area 211 and the spacer area 22 while reducing the probability of the display panel being too thick due to the excessive thickness of the bending area 212.

[0074] An embodiment of a second aspect of the present application provides a display panel, which includes an array substrate cut from an array substrate motherboard according to the embodiment of the first aspect.

[0075] The array substrate of the display panel provided in the embodiment of the present application is cut from the above-mentioned array substrate motherboard. Since the protrusion 31 on the protective film layer 3 in the array substrate motherboard can fill the recess 23 in the spacer area 22, the protrusion 31 can reduce the thickness difference between the panel area 21 and the spacer area 22, thereby reducing the probability of bubbles generated between the protective film layer 3 and the panel area 21 and the spacer area 22, thereby reducing the difficulty of the cutting process of the array substrate motherboard, and can improve the yield of the array substrate and the display panel.

[0076] The third aspect of the present application provides a method for manufacturing a display panel, such as Figure 5 As shown, the method for manufacturing a display panel includes the following steps:

[0077] Step S501: providing a substrate.

[0078] In step S502 , a plurality of panel regions are formed on one side of the substrate, and a spacer region is formed on one side of the substrate around the panel region. The thickness of the panel region is greater than that of the spacer region to form a recess in the spacer region.

[0079] Step S503 , covering the side of the plurality of panel areas and the spacer area away from the substrate with a protective film layer, and providing a protrusion corresponding to the concave portion on the side of the protective film close to the panel layer, and the protrusion fills the concave portion.

[0080] Step S504 , cutting the substrate and the protective film layer along the extending direction of the spacer region to obtain a plurality of array substrates.

[0081] Step S505 , peeling off the protective film layer on the array substrate.

[0082] Step S506 , covering the side of the array substrate away from the substrate with a cover layer.

[0083] In the embodiment of this application, Figure 6 As shown, the array substrate 20 is a layer structure in the display panel 100 that has both light-emitting and display functions. The array substrate 20 is formed by cutting the array substrate motherboard along the spacer region 22. Each array substrate 20 includes a panel region 21. During the manufacturing process of the display panel 100, a protective film layer 3 is used to protect the array substrate motherboard during the cutting process. After cutting, the protective film layer 3 needs to be peeled off to cover the array substrate 20 with a cover layer 30 and other layer structures. The cover layer 30 can be a flexible cover layer or a rigid cover layer, which is not limited in this application.

[0084] Further, such as Figure 6As shown, the display panel 100 may further include a polarizer layer 40 located between the cover layer 30 and the array substrate 20, and a second adhesive layer 50 located between the polarizer layer 40 and the cover layer 30. The polarizer layer 40 is not only used to separate the second adhesive layer 50 from the array substrate 20 and protect the array substrate 20, but is also used to control the polarization direction of light, and to convert and analyze the light beam generated by the array substrate 20 to generate light and dark contrast, thereby generating a display image. The second adhesive layer 50 may be an OCA (Optically Clear Adhesive) layer. Both the second adhesive layer 50 and the cover layer 30 have high light transmittance and low light absorption, so that the light generated by the array substrate 20 can pass through the second adhesive layer 50 and the cover layer 30 well.

[0085] In the display panel manufactured by the display panel manufacturing method provided by the embodiment of the present application, the array substrate is cut from the above-mentioned array substrate motherboard. Since the protrusion 31 on the protective film layer 3 in the array substrate motherboard can fill the recess 23 at the spacer area 22, the protrusion 31 can reduce the thickness difference between the panel area 21 and the spacer area 22, thereby reducing the probability of bubbles generated between the protective film layer 3 and the panel area 21 and the spacer area 22, thereby reducing the difficulty of the cutting process of the array substrate motherboard, and can improve the yield of the array substrate and the display panel.

[0086] In some embodiments, step S502 may be further divided into the following steps:

[0087] A first buffer layer is formed on one side of the substrate.

[0088] A thin film transistor array layer is formed on a side of the buffer layer away from the substrate.

[0089] A first planarization layer is formed on a side of the thin film transistor array layer away from the substrate.

[0090] A light emitting layer is formed on a side of the planarization layer away from the substrate.

[0091] The encapsulation layer covers the side of the light emitting layer away from the substrate.

[0092] In the embodiment of this application, Figure 7As shown, the panel area 21 includes a first buffer layer 201, a thin film transistor array layer 202, a first planarization layer 203, a light-emitting layer 204, and an encapsulation layer 205, which are stacked in a direction away from the substrate 1. The thin film transistor array layer 202 includes multiple drive circuits 2021, and the light-emitting layer 204 includes multiple light-emitting units 2041 arranged in a one-to-one correspondence with the multiple drive circuits 2021. Each drive circuit 2021 is used to provide a voltage to its corresponding light-emitting unit 2041 to drive the light-emitting unit 2041 to emit light. The first buffer layer 201 is used to reduce the probability of harmful substances in the substrate 1 invading the interior of the array substrate 20, and is also used to increase the adhesion of the film layer of the array substrate 20 to the substrate 1. The material of the first buffer layer 201 can include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The first planarization layer is used to planarize the side of the thin film transistor array layer 202 away from the substrate 1. The encapsulation layer 205 is used to encapsulate the thin film transistor array layer 202 and the light emitting layer 204 , thereby reducing the probability of water vapor, oxygen, etc. entering the thin film transistor array layer 202 and the light emitting layer 204 .

[0093] In some embodiments, the step of forming a thin film transistor array layer on a side of the buffer layer away from the substrate includes:

[0094] An active layer is formed on a side of the buffer layer away from the substrate.

[0095] A first insulating layer is formed on a side of the active layer away from the substrate.

[0096] A first metal layer is formed on a side of the first insulating layer away from the substrate, and the first metal layer is patterned to form a gate.

[0097] A second insulating layer is formed on a side of the first metal layer away from the substrate.

[0098] A second metal layer is formed on a side of the second insulating layer away from the substrate, and the second metal layer is patterned to form a source electrode and a drain electrode, wherein the source electrode or the drain electrode via is connected to the active layer.

[0099] In the embodiment of the present application, the display panel 100 may be a bottom gate structure, a top gate structure or a double gate structure. Taking the bottom gate structure of the display panel 100 as an example, Figure 7As shown, each pixel circuit 2021 includes an active layer 20211, a first insulating layer 20212, a first metal layer 20213, a second insulating layer 20214, and a second metal layer 20215, which are stacked in sequence in a direction away from the substrate 1. The first metal layer 20213 includes a gate 20213a, which can be formed by patterning the first metal layer 20213 through exposure, development, and etching. The second metal layer 20215 includes a source electrode 20215a and a drain electrode 20215b formed after patterning, and the source electrode 20215a and the drain electrode 20215b are electrically connected to the active layer 20211 through a via structure. The materials of the first metal layer 20213 and the second metal layer 20215 include metal materials such as copper, aluminum, and silver, or alloy materials containing the above metal materials.

[0100] In some embodiments, such as Figure 7 As shown, the light-emitting unit 2041 includes an anode layer 20411 , an organic light-emitting layer 20422 and a cathode layer 20423 which are sequentially arranged in a direction away from the substrate 1 .

[0101] In some embodiments, step S502 can be further divided into the following steps.

[0102] A second buffer layer is formed on one side of the substrate, and the second buffer layer is arranged on the same layer as the first buffer layer.

[0103] A third insulating layer is formed on a side of the second buffer layer away from the substrate, and the third insulating layer is arranged on the same layer as the first insulating layer.

[0104] A fourth insulating layer is formed on a side of the third insulating layer away from the substrate, and the fourth insulating layer is arranged on the same layer as the second insulating layer.

[0105] A second planarization layer is formed on a side of the third insulating layer away from the substrate, and the second planarization layer is arranged on the same layer as the first planarization layer.

[0106] In the embodiment of this application, Figure 8As shown, the spacer 22 includes a second buffer layer 221, a third insulating layer 222, a fourth insulating layer 223, and a second planarizing layer 224, sequentially arranged in a direction away from the substrate 1. The second buffer layer 221 is disposed on the same layer as the first buffer layer 201, meaning that the second buffer layer 221 and the first buffer layer 201 can be deposited in the same process. Correspondingly, the third insulating layer 222 is disposed on the same layer as the first insulating layer 20212, meaning that the third insulating layer 222 and the first insulating layer 20212 can be deposited in the same process. The fourth insulating layer 223 is disposed on the same layer as the second insulating layer 20214, meaning that the fourth insulating layer 223 and the second insulating layer 20214 can be deposited in the same process. The second planarizing layer 224 is disposed on the same layer as the first planarizing layer 203, meaning that the second planarizing layer 224 and the first planarizing layer 203 can be deposited in the same process. This simplifies the manufacturing process of the display panel 100.

[0107] An embodiment of the fourth aspect of the present application provides a display device, which includes the display panel in the embodiment of the second aspect above, or a display panel manufactured according to the manufacturing method of the display panel in the embodiment of the third aspect above.

[0108] Display devices include but are not limited to mobile phones, tablet computers, monitors, televisions, picture screens, advertising screens, electronic papers, etc. The display device provided in the embodiment of the application includes the above-mentioned display panel, so the display device provided in the embodiment of the present application has all the advantages of the above-mentioned display panel.

[0109] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. An array substrate motherboard, characterized in that: include: substrate; a panel layer, the panel layer being located on one side of the substrate, the panel layer comprising a plurality of panel areas, and a spacer area located at the periphery of the panel area, wherein the thickness of the panel area is greater than that of the spacer area so as to form a recessed portion at the spacer area; a protective film layer, the protective film layer being located on a side of the panel layer away from the substrate, the protective film layer covering the multiple panel areas and the spacer areas, and a protrusion corresponding to the concave portion being provided on a side of the protective film layer close to the panel layer, the protrusion filling the concave portion; The panel area includes a display area and a bending area located on one side of the display area, the thickness of the bending area is smaller than the thickness of the display area, and the thickness of the bending area is greater than the thickness of the spacer area; The concave portion includes a first portion and a second portion. The projection of the first portion on the substrate covers the projection of the spacing region on the substrate. The projection of the second portion on the substrate covers the projection of the bending region on the substrate.

2. The array substrate motherboard according to claim 1, wherein: The protective film layer includes a base film layer and a first adhesive layer located between the base film layer and the panel layer, and the protrusion is arranged on a side of the first adhesive layer close to the panel layer.

3. The array substrate motherboard according to claim 1, wherein: The depth of the concave portion is 3 μm to 7 μm.

4. The array substrate motherboard according to claim 1, wherein: The thickness of the protective film layer is 25 μm to 35 μm.

5. The array substrate motherboard according to claim 1, wherein: The second portion has a depth of 1 μm to 3 μm.

6. A display panel, characterized in that: The display panel includes an array substrate cut from the array substrate motherboard according to any one of claims 1 to 5.

7. A method for manufacturing a display panel, characterized in that: include: providing a substrate; A plurality of panel areas are formed on one side of the substrate, and a spacer area is formed on one side of the substrate and is located outside the panel area, wherein the thickness of the panel area is greater than that of the spacer area so as to form a recessed portion at the spacer area; A protective film layer is covered on a side of the plurality of panel areas and the spacer area away from the substrate, and a protrusion corresponding to the concave portion is provided on a side of the protective film layer close to the panel layer, and the protrusion fills the concave portion; cutting the substrate and the protective film layer along an extending direction of the spacer region to obtain a plurality of array substrates; peeling off the protective film layer on the array substrate; A cover layer is provided on a side of the array substrate away from the substrate.

8. The method for manufacturing a display panel according to claim 7, wherein: The step of forming a plurality of panel areas on one side of the substrate includes: forming a first buffer layer on one side of the substrate; forming a thin film transistor array layer on a side of the buffer layer away from the substrate; forming a first planarization layer on a side of the thin film transistor array layer away from the substrate; forming a light-emitting layer on a side of the planarization layer away from the substrate; A packaging layer covers the side of the light emitting layer away from the substrate.

9. The method for manufacturing a display panel according to claim 8, wherein: The step of forming a thin film transistor array layer on a side of the buffer layer away from the substrate comprises: forming an active layer on a side of the buffer layer away from the substrate; forming a first insulating layer on a side of the active layer away from the substrate; forming a first metal layer on a side of the first insulating layer away from the substrate, and patterning the first metal layer to form a gate; forming a second insulating layer on a side of the first metal layer away from the substrate; A second metal layer is formed on a side of the second insulating layer away from the substrate, and the second metal layer is patterned to form a source electrode and a drain electrode, wherein the source electrode or the drain electrode is connected to the active layer through a via hole.

10. The method for manufacturing a display panel according to claim 9, wherein: The step of forming a spacer area on one side of the substrate and located outside the panel area includes: forming a second buffer layer on one side of the substrate, wherein the second buffer layer is disposed on the same layer as the first buffer layer; forming a third insulating layer on a side of the second buffer layer away from the substrate, wherein the third insulating layer is provided on the same layer as the first insulating layer; forming a fourth insulating layer on a side of the third insulating layer away from the substrate, wherein the fourth insulating layer is provided on the same layer as the second insulating layer; A second planarization layer is formed on a side of the third insulating layer away from the substrate, and the second planarization layer is arranged on the same layer as the first planarization layer.

11. A display device, characterized in that: A display panel comprising the display panel according to claim 6, or a display panel manufactured according to the method for manufacturing a display panel according to any one of claims 7 to 10.

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