Integrated circuit device

Abstract

An integrated circuit device includes a semiconductor-on-insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active regions and a plurality of second fin-type active regions defined by a plurality of trenches and extending in a first horizontal direction above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stack structures including a plurality of nanosheets extending parallel to each other and spaced apart from upper surfaces of the plurality of first fin-type active regions and the plurality of second fin-type active regions; a plurality of first source / drain regions extending into the SOI substrate layer; and a plurality of second source / drain regions extending into the semiconductor substrate layer. Lower surfaces of the first source / drain regions and the second source / drain regions can be non-coplanar with each other.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0183521, filed with the Korean Intellectual Property Office on December 24, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to integrated circuit devices including multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Background Technology

[0004] As the integration density of integrated circuit devices increases, their size is shrinking to extreme dimensions (e.g., extremely small sizes), and the scale of integrated circuit devices may be reaching its limit. Therefore, new methods for fabricating and using structural changes in integrated circuit devices are being considered to improve their performance. For example, an integrated circuit device equipped with transistors having novel structures, such as multi-gate MOSFETs, has been proposed. Summary of the Invention

[0005] The present invention provides an integrated circuit device equipped with transistors, including multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with improved operating characteristics.

[0006] To achieve the above-mentioned technical objectives, and / or other technical objectives related to this disclosure, the present invention provides an integrated circuit device that may include: a first region including a semiconductor-on-insulator (SOI) substrate layer, the SOI substrate layer including a base substrate layer, an insulating substrate layer and a cover substrate layer; and a second region including a semiconductor substrate layer; and a plurality of first fin active regions defined by a plurality of first trenches in the first region, the first fin active regions protruding from the main surface of the SOI substrate layer and extending in a first horizontal direction. A plurality of second fin-shaped active regions, defined by a plurality of second trenches in a second region, the second fin-shaped active regions protruding from the main surface of the semiconductor substrate layer and extending in a first horizontal direction; a plurality of nanosheet stacked structures, above the plurality of first fin-shaped active regions and the plurality of second fin-shaped active regions, each of the plurality of nanosheet stacked structures including a plurality of nanosheets extending parallel to each other and spaced apart from the upper surfaces of the plurality of first fin-shaped active regions and the plurality of second fin-shaped active regions; a plurality of first source / drain regions, located between adjacent nanosheet stacked structures in the first region, each first source / drain region extending into the SOI substrate layer and contacting the insulating substrate layer, and the lower surface of each first source / drain region at a first vertical horizontal direction; and a plurality of second source / drain regions, in the second region, each of the plurality of second source / drain regions extending into the semiconductor substrate layer, and the lower surface of each second source / drain region at a second vertical horizontal direction, the second vertical horizontal direction being further away from the main surface of the SOI substrate layer and the semiconductor substrate layer than the first vertical horizontal direction.

[0007] This invention provides an integrated circuit device, which may include: a semiconductor-on-insulator (SOI) substrate layer, comprising a base substrate layer, an insulating substrate layer, and a capping substrate layer in a first region; a semiconductor substrate layer in a second region; a plurality of first fin active regions and a plurality of second fin active regions, the plurality of first fin active regions and the plurality of second fin active regions being defined by a plurality of trenches on the SOI substrate layer and the semiconductor substrate layer respectively and extending in a first horizontal direction; a plurality of first nanosheets extending parallel to each other and spaced apart from the plurality of first fin active regions in a vertical direction; and a plurality of gate electrodes extending in a second horizontal direction intersecting the first horizontal direction, the plurality of gate electrodes being on the plurality of first fin active regions and the plurality of second fin active regions, the plurality of gate electrodes being... The electrode comprises a first portion between vertically adjacent first nanosheets; a gate dielectric layer between the first nanosheets and a plurality of first fin active regions; a plurality of first source / drain regions located above the plurality of first fin active regions between horizontally adjacent first nanosheets, each of the plurality of first source / drain regions extending into the SOI substrate layer to contact the insulating substrate layer, and the lower surface of each first source / drain region at a first vertical level above the plurality of first fin active regions; and a plurality of second source / drain regions located above the plurality of second fin active regions, each of the plurality of second source / drain regions extending over the plurality of second fin active regions into the semiconductor substrate layer, and the lower surface of each second source / drain region at a second vertical level above the plurality of second fin active regions, the second vertical level being higher than the first vertical level.

[0008] This invention provides an integrated circuit device comprising: a semiconductor-on-insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a capping substrate layer in a first region; a semiconductor substrate layer in a second region different from the first region; a first impurity region in a portion of the SOI substrate layer having a first impurity type; a second impurity region in a portion of the semiconductor substrate layer having a second impurity type; a plurality of first fin active regions and a plurality of second fin active regions, the plurality of first fin active regions and the plurality of second fin active regions being defined by a plurality of trenches and extending in a first horizontal direction on the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures, each nanosheet stacked structure including a plurality of nanosheets extending parallel to each other and spaced apart from the upper surfaces of the plurality of first fin active regions and the plurality of second fin active regions; a plurality of first source / drain regions connected to the ends of the plurality of adjacent nanosheets on the plurality of first fin active regions, the plurality of first source / drain regions extending through the capping substrate layer and into the insulating substrate layer. The semiconductor substrate comprises: a substrate layer with its lower surface at a first vertical horizontal level; a plurality of second source / drain regions extending over a plurality of second fin active regions into the semiconductor substrate layer and contacting a second impurity region, the lower surfaces of the plurality of second source / drain regions being at a second vertical horizontal level higher than the first vertical horizontal level; a plurality of gate electrodes extending in a second horizontal direction intersecting the first horizontal direction, the plurality of gate electrodes extending over a plurality of first fin active regions and a plurality of second fin active regions, each of the plurality of gate electrodes including a main gate unit and a plurality of sub-gate units, wherein the main gate unit is located above a corresponding nanosheet stack in a plurality of nanosheet stacks, and each sub-gate unit is located below a corresponding nanosheet in a plurality of nanosheet stacks; a gate dielectric layer disposed between the plurality of gate electrodes and the plurality of nanosheets; a plurality of insulating spacers located in a first region between the plurality of first fin active regions and the plurality of nanosheets, the plurality of insulating spacers covering a first end and a second end of each of the plurality of sub-gate units, and a gate dielectric layer between each sub-gate unit and an insulating spacer. Attached Figure Description

[0009] Some aspects of this disclosure and exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 14B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments, and the cross-sectional view also illustrates an integrated circuit device manufactured using the manufacturing method;

[0011] Figures 15 to 19 These are cross-sectional views of an integrated circuit device according to some embodiments;

[0012] Figure 20Aand Figure 20B These are cross-sectional views of an integrated circuit device according to some embodiments;

[0013] Figure 21 These are cross-sectional views of an integrated circuit device according to some embodiments; and

[0014] Figures 22A to 23B This is a cross-sectional view showing a method for manufacturing an integrated circuit device according to some embodiments, and a cross-sectional view showing an integrated circuit device manufactured using this manufacturing method. Detailed Implementation

[0015] Figures 1 to 14B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments, and an integrated circuit manufactured using this method. Figures 1 to 8A and Figures 9 to 14A This is a cross-sectional view showing the YZ surface. Figure 8B and Figure 14B This shows the respective directions along... Figure 8A and Figure 14A The cross-sectional view of the XZ surface intercepted by the V1-V1′ and V2-V2′ lines.

[0016] Reference Figure 1 A semiconductor-on-insulator (SOI) substrate 100 is provided. The SOI substrate 100 may include a substrate layer 101, an insulating substrate layer 102 and a cover substrate layer 103 stacked in sequence, and is provided with a first region R1 and a second region R2.

[0017] The substrate layer 101 may include semiconductors such as Si and Ge, or compound semiconductor materials such as SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate layer 101 may include at least one of group III-V materials and group IV materials. Group III-V materials may include binary, ternary, or quaternary compounds comprising at least one group III element and at least one group V element. The insulating substrate layer 102 may include an insulating material. The insulating substrate layer 102 may include, for example, silicon oxide. The insulating substrate layer 102 may have a thickness of tens of nanometers. For example, the insulating substrate layer 102 may have a thickness of about 10 nm to about 20 nm. The cover substrate layer 103 may include semiconductor materials such as Si and Ge, or compound semiconductor materials such as SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the cover substrate layer 103 may include a semiconductor material of a different type than that of the substrate layer 101. The cover substrate layer 103 may have a thickness of about 10 nanometers. For example, the substrate layer 101 may include Si, while the cover substrate layer 103 may include any of the III-V group materials described above.

[0018] Reference Figure 2 The substrate recess 100R can be formed by removing both the cover substrate layer 103 and the insulating substrate layer 102 in the second region R2. The upper surface of the base substrate layer 101 can be exposed by the substrate recess 100R. In other words, the lower surface of the base substrate layer 101 can be exposed by the substrate recess 100R. In some embodiments, during the formation of the substrate recess 100R, the upper portion of the base substrate layer 101 can be removed together with the cover substrate layer 103 and the insulating substrate layer 102 in the second region R2.

[0019] The substrate layer 101, insulating substrate layer 102, and cover substrate layer 103, which are sequentially stacked in the first region R1, can be referred to as SOI substrate layer 100A. Therefore, SOI substrate layer 100A can be arranged in the first region R1, and substrate layer 101 can be arranged in the second region R2.

[0020] Reference Figure 3 In the second region R2, an epitaxial substrate layer 101E can be formed on the substrate layer 101 to fill the substrate recess 100R. The epitaxial substrate layer 101E may include a semiconductor material. By using an epitaxial growth method with the substrate layer 101 as a seed layer, the epitaxial substrate layer 101E can be formed to have the same crystal structure as the substrate layer 101. In some embodiments, the epitaxial substrate layer 101E may include a semiconductor material of the same type as the substrate layer 101. In some embodiments, the epitaxial substrate layer 101E may include a semiconductor material of a different type having the same crystal structure as the substrate layer 101. For example, the substrate layer 101 may include Si, while the epitaxial substrate layer 101E may include GE or SiGe.

[0021] In the second region R2, the epitaxial substrate layer 101E and the substrate layer 101 formed on the substrate layer 101 can be referred to as the semiconductor substrate layer 100B. Therefore, the SOI substrate layer 100A can be disposed in the first region R1, and the semiconductor substrate layer 101B can be disposed in the second region R2. Here, the SOI substrate layer 100A and the semiconductor substrate layer 100B can be referred to together as a "substrate".

[0022] In some embodiments, the upper surface of the SOI substrate layer 100A and the upper surface of the semiconductor substrate layer 100B may be located at the same vertical level as the upper surface of the substrate layer 101. For example, the upper surface of the SOI substrate layer 100A may be coplanar with the upper surface of the semiconductor substrate layer 100B.

[0023] In some embodiments, an initial epitaxial layer may be formed over a first region R1 and a second region R2. The initial epitaxial layer may fill the substrate recess 100R and may cover the upper surface of the cover substrate layer 103 and the upper surface of the base substrate layer 101. Subsequently, an epitaxial substrate layer 101E can be formed by performing a planarization operation and removing a portion of the upper surface of the initial epitaxial layer, thereby exposing the cover substrate layer 103 in the first region R1. During the planarization operation for forming the epitaxial substrate layer 101E, a portion of the upper surface of the cover substrate layer 103 may be removed together; in this case, Figure 3 The thickness of the cover substrate layer 103 shown can be less than Figure 1 and Figure 2 The thickness of the cover substrate layer 103 shown.

[0024] In some embodiments, the initial epitaxial layer may include the same material as the cover substrate layer 103. After the initial epitaxial layer is formed to fill the substrate recess 100R and cover the upper surface of the cover substrate layer 103 and the upper surface of the base substrate layer 101 in the second region R2, the epitaxial substrate layer 101E can be formed by performing a planarization operation and removing a portion of the upper surface of the initial epitaxial layer. In some embodiments, some initial epitaxial layers may remain on the cover substrate layer 103, but since the initial epitaxial layer and the cover substrate layer 103 may include the same material as each other, the initial epitaxial layer can be treated as the cover substrate layer 103. Figure 3 The thickness of the cover substrate layer 103 shown can be greater than Figure 1 and Figure 2 The thickness of the cover substrate layer 103 shown.

[0025] Reference Figure 4 A first impurity region 104 can be formed by implanting an impurity with first conductivity into a portion of the SOI substrate layer 100A, and a second impurity region 105 can be formed by implanting an impurity with second conductivity into a portion of the semiconductor substrate layer 100B. For example, when the first region R1 is an NMOS region and the second region R2 is a PMOS region, the impurity with first conductivity can include a p-type impurity, and the impurity with second conductivity can include an n-type impurity. The lower surfaces of the first impurity region 104 and the second impurity region 105 can be located at the same vertical level as the substrate layer 101, but this disclosure is not limited thereto. For example, the lower surface of the first impurity region 104 can be located at a lower level than the lower surface of the second impurity region 105, or the lower surface of the first impurity region 104 can be located at a higher level than the lower surface of the second impurity region 105.

[0026] In some embodiments, the first impurity region 104 may be formed on a portion of the upper surface of the base substrate layer 101 of the SOI substrate layer 100A, but this disclosure is not limited thereto. In some embodiments, the first impurity region 104 may be formed together with the cover substrate layer 103 of the SOI substrate layer 100A in a portion of the upper part of the base substrate layer 101. In this case, a first conductive impurity may be implanted into the insulating substrate layer 102, but since the insulating substrate layer 102 includes an insulating material, the first conductive impurity may not be applied to the first impurity region 104.

[0027] In some embodiments, the second impurity region 105 may be formed in a portion of the upper part of the semiconductor substrate layer 100B, but this disclosure is not limited thereto. In some embodiments, the second impurity region 105 may be formed only in a portion of the upper part of the semiconductor substrate layer 100B, but in some embodiments, it may not be formed in the uppermost part of the semiconductor substrate layer 100B.

[0028] Reference Figure 5 Multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS may be alternately stacked on a substrate in a first region R1 where an SOI substrate layer 100A is disposed and in a second region R2 where a semiconductor substrate layer 100B is disposed. The multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS may comprise semiconductor materials different from each other. In some embodiments, the multiple nanosheet semiconductor layers NS may comprise a single material. In some embodiments, the multiple nanosheet semiconductor layers NS may comprise the same material as at least one of the overlay substrate layer 103 of the SOI substrate layer 100A and the epitaxial substrate layer 101E of the semiconductor substrate layer 100B. In some embodiments, the multiple sacrificial semiconductor layers 106S may comprise SiGe, and the multiple nanosheet semiconductor layers NS may comprise Si, but this disclosure is not limited thereto.

[0029] The plurality of sacrificial semiconductor layers 106S may all be formed to have equal thicknesses, but this disclosure is not limited thereto. In some embodiments, the thickness of the sacrificial semiconductor layer 106S closest to the substrate may be greater than the thickness of the remaining sacrificial semiconductor layers 106S.

[0030] Refer to together Figure 5 and Figure 6Multiple trench TREs can be formed by etching a stacked structure of multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS, as well as portions of SOI substrate layer 100A and semiconductor substrate layer 100B. Therefore, multiple first fin active regions FAA and multiple second fin active regions FAB defined by the multiple trench TREs can be formed in a first region R1 and a second region R2, respectively. Each of the multiple first fin active regions FAA can include a portion of the SOI substrate layer 100A defined by the multiple trench TREs in the first region R1. Each of the multiple second fin active regions FAB can include a portion of the semiconductor substrate layer 100B defined by the multiple trench TREs in the second region R2. In this disclosure, the multiple first fin active regions FAA and the multiple second fin active regions FAB can be referred to as multiple fin active regions.

[0031] Multiple first finned active regions FAA and multiple second finned active regions FAB can extend parallel to each other in a first horizontal direction (X direction). The multiple first finned active regions FAA and multiple second finned active regions FAB can protrude upward from the main surface 100M of the substrate composed of SOI substrate layer 100A and semiconductor substrate layer 100B, i.e., in the vertical direction (Z direction). The main surface 100M of the substrate can be the main surface 100M of SOI substrate layer 100A (e.g., base substrate layer 101) in the first region R1 and the main surface 100M of semiconductor substrate layer 100B in the second region R2. In the first region R1, the multiple first finned active regions FAA can be spaced apart at a constant pitch in a second horizontal direction (Y direction). In the second region R2, the multiple second finned active regions FAB can be spaced apart at a constant pitch in the second horizontal direction (Y direction). In some embodiments, a plurality of first fin-shaped active regions FAA and a plurality of second fin-shaped active regions FAB may be arranged at the same spacing in the second horizontal direction (Y direction) in the first region R1 and the second region R2, respectively, but this disclosure is not limited thereto. For example, the plurality of first fin-shaped active regions FAA may be spaced apart at a constant first spacing in the first region R1 in the second horizontal direction (Y direction), and the plurality of second fin-shaped active regions FAB may be spaced apart at different constant second spacings in the second region R2 in the second horizontal direction (Y direction).

[0032] In each of the first region R1 and the second region R2, a stacked structure NSS comprising multiple sacrificial semiconductor layers 106S and multiple nanosheets N1, N2, and N3 can be arranged on multiple fin active regions, namely, multiple first fin active regions FAA and multiple second fin active regions FAB. The stacked structure NSS of multiple nanosheets N1, N2, and N3 can be formed by etching away a portion of the multiple nanosheet semiconductor layers NS.

[0033] Reference Figure 7 An initial device separation layer can be formed by filling multiple trench TREs, and then a device separation layer 118 can be formed by performing a groove process and removing a certain thickness from the top of the initial device separation layer.

[0034] The initial device separation layer can be formed on the side surfaces of multiple first fin active regions (FAAs) and multiple second fin active regions (FABs), on the sidewalls and top surface of the stacked structure NSS of nanosheets N1, N2, and N3, and on the side and top surfaces of SOI substrate layer 100A and semiconductor substrate layer 100B. The trench process can include an etching process that performs dry etching, wet etching, or a combination of dry and wet etching.

[0035] The device separation layer 118 can be formed to include a vertically horizontal position at the same level as or substantially similar to the upper surfaces of the plurality of first fin active regions FAA and the plurality of second fin active regions FAB. In other words, the sidewalls of the stacked structure NSS of the plurality of nanosheets N1, N2 and N3 and the sidewalls of the plurality of sacrificial semiconductor layers 106S can be exposed on the plurality of first fin active regions FAA and the plurality of second fin active regions FAB.

[0036] Reference Figure 8A and Figure 8B In the first region R1 and the second region R2, multiple dummy gate structures (DGS) can be formed, intersecting at least a portion of multiple first fin active regions (FAA) and multiple second active regions (FAB), and extending on the stacked structure NSS of multiple nanosheets N1, N2 and N3, as well as the multiple first fin active regions (FAA) and multiple second fin active regions (FAB). The multiple dummy gate structures (DGS) can extend parallel to each other in the second horizontal direction (Y direction).

[0037] The dummy gate structure DGS can have a structure with an oxide layer D12, a dummy gate layer D14, and a capping layer D16 stacked sequentially. In an example of forming the dummy gate structure DGS, the oxide layer D12, the dummy gate layer D14, and the capping layer D16 can be formed and patterned such that only a portion of the oxide layer D12, the dummy gate layer D14, and the capping layer D16 is retained, such that the oxide layer D12, the dummy gate layer D14, and the capping layer D16 cover the exposed surfaces of the stacked structure NSS and the plurality of sacrificial semiconductor layers 106S, the exposed surfaces of the plurality of first fin active regions FAA and the plurality of second fin active regions FAB, and the exposed upper surface of the device separation layer 118, wherein the stacked structure NSS and the plurality of sacrificial semiconductor layers 106S cover the upper portions of the plurality of first fin active regions FAA and the plurality of second fin active regions FAB.

[0038] In some embodiments, the dummy gate layer D14 may include a polysilicon layer and the capping layer D16 may include a silicon nitride layer, but this disclosure is not limited thereto.

[0039] Gate spacers 130 can be formed to cover the two sidewalls of the dummy gate structure DGS. To form gate spacers 130, a spacer layer covering the dummy gate structure DGS can be formed, and then the spacer layer can be etched back to retain gate spacers 130. Gate spacers 130 may include, for example, a silicon nitride layer.

[0040] Reference Figure 9 By using a dummy gate structure DGS and a gate spacer 130 as an etching mask to remove a portion of the stacked structure NSS of multiple nanosheets N1, N2 and N3 and multiple sacrificial semiconductor layers 106S, multiple first groove regions RS1 and multiple second groove regions RS2 can be formed in the first region R1 and the second region R2, respectively.

[0041] In some embodiments, during the process of etching portions of multiple nanosheets N1, N2, and N3 and multiple sacrificial semiconductor layers 106S to form multiple first trench regions RS1 and multiple second trench regions RS2, a portion of the upper portion of multiple first fin active regions FAA and multiple second fin active regions FAB may also be removed. For example, each of the multiple first trench regions RS1 may penetrate the overlay substrate layer 103 and extend into the insulating substrate layer 102. Each of the multiple second trench regions RS2 may extend into the semiconductor substrate layer 100B.

[0042] In some embodiments, each of the plurality of first recessed regions RS1 may extend into the insulating substrate layer 102, and the insulating substrate layer 102 may be exposed by the first recessed region RS1. In some embodiments, each of the plurality of second recessed regions RS2 may extend into the semiconductor substrate layer 100B, and the second impurity region 105 may be exposed by the plurality of second recessed regions RS2. The bottom of the first recessed region RS1 may be located at a first vertical level LV1, and the bottom of the second recessed region RS2 may be located at a second vertical level LV2, which is higher than the first vertical level LV1. The second vertical level LV2 may be further away from the main surface 100M of the substrate, including the SOI substrate layer 100A and the semiconductor substrate layer 100B, than the first vertical level LV1.

[0043] Reference Figure 10In the first region R1, portions of the plurality of sacrificial semiconductor layers 106S exposed on both sides of each of the plurality of nanosheets N1, N2, and N3 in the first recess region RS1 can be removed using an isotropic etching process. Thereafter, insulating spacers 140 can be formed, filling a portion of the region formed between the plurality of nanosheets due to the isotropic etching process. The insulating spacers 140 may include, for example, a silicon nitride layer. In some embodiments, each insulating spacer 140 can be formed by stacking multiple insulating layers. In some embodiments, the insulating spacers 140 may be formed only in the first region R1 and may not be formed in the second region R2.

[0044] After forming the insulating spacer 140 in the first region R1, a plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B can be formed in the first region R1 and the second region R2, respectively. The plurality of first source / drain regions 160A and the plurality of second source / drain regions 160B can comprise semiconductor materials formed using an epitaxial growth method, where the exposed sidewalls of a plurality of nanosheets N1, N2, and N3, and the exposed surfaces of a plurality of first fin active regions FAA and a plurality of second fin active regions FAB, serve as seeds. For example, the plurality of first source / drain regions 160A can be formed using an epitaxial growth method, where the epitaxial growth method uses a cover substrate layer 103 and a stacked structure NSS of a plurality of nanosheets N1, N2, and N3 as seeds. The plurality of second source / drain regions 160B can be formed using an epitaxial growth method, where the epitaxial growth method uses a semiconductor substrate layer 100B and a stacked structure NSS of a plurality of nanosheets N1, N2, and N3 as seeds.

[0045] In some embodiments, the plurality of first source / drain regions 160A and the plurality of second source / drain regions 160B may comprise materials different from each other, and each of the plurality of first source / drain regions 160A and the plurality of second source / drain regions 160B may be formed by performing a separate epitaxial growth process. For example, the first source / drain region 160A may comprise Si, but not Ge. In some embodiments, the plurality of first source / drain regions 160A may comprise a semiconductor material such as Si, a compound semiconductor material such as SiC, or a multilayer structure thereof. The second source / drain regions 160B may comprise Ge. In some embodiments, the second source / drain regions 160B may comprise a semiconductor material such as Ge, a compound semiconductor material such as SiGe, or a semiconductor material such as Si and a multilayer structure thereof.

[0046] A plurality of first source / drain regions 160A may fill a portion of a plurality of first recessed regions RS1, and each of the plurality of first source / drain regions 160A may extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A may contact the insulating substrate layer 102. A plurality of second source / drain regions 160B may fill a portion of a plurality of second recessed regions RS2, and each of the plurality of second source / drain regions 160B may extend into the semiconductor substrate layer 100B, and the lower surface of each of the plurality of second source / drain regions 160B may contact the second impurity region 105. The lower surface of the first source / drain region 160A may be at a first vertical level LV1, and the lower surface of the second source / drain region 160B may be at a second vertical level LV2 above the first vertical level LV1, or at a second vertical level LV2 further away from the main surface 100M.

[0047] Reference Figure 10 and Figure 11 The inter-gate insulating layer 172 can be formed on a plurality of first source / drain regions 160A, a plurality of second source / drain regions 160B, and a plurality of dummy gate structures DGS. Subsequently, the portion of the inter-gate insulating layer 172 and the capping layer D16 covering the upper surface of the dummy gate layer D14 can be removed by planarizing the inter-gate insulating layer 172 and / or by grinding the gate spacers 130 and the inter-gate insulating layer 172 around the capping layer D16 to a certain thickness. As a result, the upper surface of the inter-gate insulating layer 172 can be substantially at the same level as the upper surface of the dummy gate layer D14. In some embodiments, the inter-gate insulating layer 172 may include a silicon oxide layer.

[0048] Reference Figure 11 and Figure 12 Multiple gate spaces GS are formed by removing the dummy gate layer D14 and the oxide layer D12 beneath it, and by removing at least a portion of the multiple sacrificial semiconductor layers 106S retained in the first region R1 and the second region R2. A portion of each surface of the multiple nanosheets N1, N2, and N3, the upper surface of the multiple first fin active regions FAA, and the upper surface of the multiple second fin active regions FAB can be exposed via the gate space GS. In some embodiments, portions of the multiple sacrificial semiconductor layers 106S may be retained instead of removed.

[0049] Reference Figure 12 and Figure 13 A gate dielectric layer 145 may be formed on a surface exposed by a plurality of gate spaces GS, and a plurality of gate electrodes 150 may be formed on the gate dielectric layer 145 filling the plurality of gate spaces GS. The plurality of gate electrodes 150 may extend parallel to each other in a second horizontal direction (Y direction).

[0050] In some embodiments, the gate dielectric layer 145 may have a stacked structure of an interface layer and a high-k dielectric layer. In some embodiments, as a non-limiting example, the interface layer may include a low-k dielectric material layer having a dielectric constant of about 9 or less, such as a silicon oxide layer, a silicon oxynitride film, or a combination thereof. In some embodiments, the interface layer may be omitted. The high-k dielectric layer may be a material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25.

[0051] In some embodiments, the gate dielectric layer 145 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties. The ferroelectric material layer may have negative capacitance, and the paraelectric material layer may have positive capacitance. For example, when two or more capacitors are connected in series, and each capacitor has a positive capacitance, the total capacitance can decrease from the value of each individual capacitor. However, when at least one of two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0052] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the two connected ferroelectric and paraelectric material layers can be increased. Because the total capacitance can be increased, transistors including ferroelectric material layers can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0053] The ferroelectric material layer can possess ferroelectric properties. The ferroelectric material layer may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In some embodiments, for example, the hafnium zirconium oxide may include a hafnium oxide doped with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0054] The ferroelectric material layer may also include doped dopants. As a non-limiting example, the dopants may include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopants included in the ferroelectric material layer may vary depending on which ferroelectric material is included in the ferroelectric material layer.

[0055] When the ferroelectric material layer includes hafnium oxide, as a non-limiting example, the dopant included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and / or yttrium (Y).

[0056] When the dopant is Al, the ferroelectric material layer may include about 3 at% to about 8 at% aluminum. For example, the dopant ratio may be the ratio of aluminum to the sum of hafnium and aluminum.

[0057] When the dopant is Si, the ferroelectric layer may include about 2 at% to 10 at% silicon. When the dopant is Y, the ferroelectric layer may include about 2 at% to 10 at% yttrium. When the dopant is Gd, the ferroelectric layer may include about 1 at% to 7 at% gadolinium. When the dopant is Zr, the ferroelectric layer may include about 50 at% to 80 at% zirconium.

[0058] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include at least one of silicon oxide and a high-k metal oxide. The metal oxide contained in the paraelectric material layer may include at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but this disclosure is not limited thereto.

[0059] The ferroelectric material layer and the paraelectric material layer may contain the same materials. The ferroelectric material layer may not have paraelectric properties, and the paraelectric material layer may not have ferroelectric properties. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0060] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can be, for example, from about 0.5 nm to about 10 nm, but this disclosure is not limited thereto. Because the critical thickness of the ferroelectric material exhibiting ferroelectric properties can vary, the thickness of the ferroelectric material layer can vary depending on the selected ferroelectric material.

[0061] As an example, the gate dielectric layer 145 may include a ferroelectric material layer. As another example, the gate dielectric layer 145 may include multiple ferroelectric material layers spaced apart from each other. The gate dielectric layer 145 may have a stacked structure in which multiple ferroelectric material layers and multiple paraelectric material layers are stacked alternately.

[0062] The gate electrode 150 may include a work function controlled metal incorporating layer and a gap-filled metal incorporating layer that fills the upper space of the work function controlled metal incorporating layer. In some embodiments, the gate electrode 150 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filled metal layer are sequentially stacked.

[0063] The gate electrode 150 may include a main gate unit 150M and a plurality of sub-gate units 150S. The main gate unit 150M covers the upper surface of a nanosheet stacked structure NSS comprising a plurality of nanosheets N1, N2, and N3, and the plurality of sub-gate units 150S are connected to the main gate unit 150M and formed in the space between each of the plurality of nanosheets N1, N2, and N3 and a first fin-type active region FAA, and in the space between each of the plurality of nanosheets N1, N2, and N3 and a second fin-type active region FAB. For example, the sub-gate units 150S may be formed below each of the plurality of nanosheets N1, N2, and N3.

[0064] In the first region R1, a plurality of insulating spacers 140 may be disposed at both ends of each of the plurality of sub-gate cells 150S, wherein a gate dielectric layer 145 is located between each sub-gate cell 150S and the insulating spacer 140. In the second region R2, a plurality of second source / drain regions 160B may be disposed at both ends of each of the plurality of sub-gate cells 150S, wherein a gate dielectric layer 145 is located between each sub-gate cell 150S and the second source / drain region 160B. In the first region R1, the gate dielectric layer 145 and the insulating spacer 140 may be disposed between the sub-gate cell 150S and the first source / drain region 160A. In the second region R2, the gate dielectric layer 145 may be present, but the insulating spacer 140 may not be present between the sub-gate cells 150S and the second source / drain region 160B. Therefore, in the second region R2, the sub-gate cells 150S and the second source / drain regions 160B may be in direct contact with the gate dielectric layer 145 disposed therebetween.

[0065] Reference Figure 14A and Figure 14B An interlayer insulating layer 174 covering multiple gate electrodes 150 and an inter-gate insulating layer 172 can be formed. Then, a first contact hole 192H exposing multiple first source / drain regions 160A and multiple second source / drain regions 160B can be formed by etching a portion of the interlayer insulating layer 174 and the inter-gate insulating layer 172. A metal silicide layer 162 can be formed on the surfaces of the multiple first source / drain regions 160A and multiple second source / drain regions 160B exposed via the multiple first contact holes 192H. Furthermore, by etching a portion of the interlayer insulating layer 174, multiple second contact holes 194H exposing the upper surfaces of the multiple gate electrodes 150 (i.e., the upper surface of the main gate cell 150M) can be formed. In some embodiments, the multiple first contact holes 192H and the multiple second contact holes 194H can be formed together in a single etching process; however, this disclosure is not limited thereto, and each of the multiple first contact holes 192H and the multiple second contact holes 194H can be formed by a separate etching process.

[0066] Subsequently, a plurality of first contact plugs 192 filling a plurality of first contact holes 192H can be formed, and a plurality of second contact plugs 194 filling a plurality of second contact holes 194H can be formed, and thus an integrated circuit device 1 can be formed.

[0067] A plurality of first contact plugs 192 can be connected to a plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B via a metal silicide layer 162, and a plurality of second contact plugs 194 can be connected to a plurality of gate electrodes 150. In some embodiments, the plurality of first contact plugs 192 and the plurality of second contact plugs 194 can be formed together, but this disclosure is not limited thereto, and each of the plurality of first contact plugs 192 and the plurality of second contact plugs 194 can be formed in a separate process.

[0068] The integrated circuit device 1 may include a plurality of first finned active regions FAA and a plurality of second finned active regions FAB protruding upward in the vertical direction (Z direction) from the main surface 100M of a substrate including an SOI substrate layer 100A and a semiconductor substrate layer 100B. It may also include a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surfaces of the plurality of first finned active regions FAA and the plurality of second finned active regions FAA from positions vertically spaced from the upper surfaces of the plurality of first finned active regions FAA and the plurality of second finned active regions FAA in the vertical direction (Z direction). The plurality of first finned active regions FAA may protrude upward in the vertical direction (Z direction) from the main surface 100M of the SOI substrate layer 100A in a first region R1, and the plurality of second finned active regions FAA may protrude upward in the vertical direction (Z direction) from the main surface 100M of the semiconductor substrate layer 100B in a second region R2.

[0069] Multiple trench TREs can confine or define multiple first fin active regions (FAAs) and multiple second fin active regions (FABs) on a substrate including an SOI substrate layer 100A and a semiconductor substrate layer 100B. The sidewalls of the multiple first fin active regions (FAAs) and multiple second fin active regions (FABs) can be covered by a device separation layer 118 that fills the multiple trench TREs. The upper surfaces of the multiple first fin active regions (FAAs) and multiple second fin active regions (FABs) can be at the same or similar level to the upper surface of the device separation layer 118 at a distance of 100M from the main surface.

[0070] The multiple nanosheet stacked structure NSS can be spaced apart from the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB. The multiple nanosheet stacked structure NSS can include multiple nanosheets N1, N2 and N3, which extend parallel to the upper surfaces of the multiple first fin active regions FAA and multiple second fin active regions FAB on a substrate including SOI substrate layer 100A and semiconductor substrate layer 100B.

[0071] Multiple nanosheets N1, N2, and N3 of a nanosheet stacked structure NSS can be sequentially stacked one after another on the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB. In some embodiments, as shown in the figure, a nanosheet stacked structure NSS includes three nanosheets N1, N2, and N3, but this disclosure is not limited thereto. Each of the multiple nanosheets N1, N2, and N3 can have a channel region. In some embodiments, the multiple nanosheets N1, N2, and N3 can comprise a single material.

[0072] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions (FAA) and multiple second finned active regions (FAB). At least a portion of the multiple gate electrodes 150 may overlap with each of the multiple nanosheet stacked structures (NSS) in the vertical direction (Z direction).

[0073] Each of the plurality of gate electrodes 150 may cover and surround at least a portion of the nanosheet stacked structure NSS. The gate electrode 150 may include a main gate cell 150M and a plurality of sub-gate cells 150S, the main gate cell 150M covering the upper surface of the nanosheet stacked structure NSS; and the plurality of sub-gate cells 150S connected to the main gate cell 150M and formed in the space between a plurality of first fin-type active regions FAA and a plurality of nanosheets N1, N2, and N3, and in the space between a plurality of second fin-type active regions FAB and a plurality of nanosheets N1, N2, and N3, i.e., below each of the plurality of nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure NSS from the gate electrode 150.

[0074] In the first region R1, a plurality of first source / drain regions 160A can be formed on a plurality of first fin active regions FAA, while in the second region R2, a plurality of second source / drain regions 160B can be formed on a plurality of second fin active regions FAA. Each of the plurality of first source / drain regions 160A and the plurality of second source / drain regions 160B can be connected to the adjacent ends of the plurality of nanosheets N1, N2 and N3. In the first region R1, each of the plurality of first source / drain regions 160A can extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160A can penetrate the covering substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A can contact the insulating substrate layer 102. In the first region R1, each of the plurality of first source / drain regions 160A may not contact the first impurity region 104. In the second region R2, each of the plurality of second source / drain regions 160B can extend into the semiconductor substrate layer 100B, and the lower surface of each of the plurality of second source / drain regions 160B can contact the second impurity region 105. The lower surface of the first source / drain region 160A can be at a first vertical level LV1, and the lower surface of the second source / drain region 160B can be at a second vertical level LV2, which is higher than the first vertical level LV1 and further away from the main surface 100M.

[0075] The integrated circuit device 1 may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of second transistors TRB disposed in a second region R2. Each of the first transistors TRA and the second transistors TRB may be or may include a multi-gate metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the first transistors TRA disposed in the first region R1 may include a multi-gate nMOSFET, and the second transistors TRB disposed in the second region R2 may include a multi-gate pMOSFET.

[0076] In some embodiments, when the gate dielectric layer 145 includes a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties, each of the first transistor TRA and the second transistor TRB may include a negative capacitance (NC) FET using negative capacitance.

[0077] Gate spacers 130 can be formed on multiple nanosheet stacked structures NSS, multiple first fin active regions FAA, and multiple second fin active regions FAB, sequentially covering the sidewalls of the gate electrode 150. Gate spacers 130 may include a silicon nitride layer, but this disclosure is not limited thereto. Gate spacers 130 may cover the sidewalls of the main gate cell 150M of the gate electrode 150.

[0078] In the first region R1, insulating spacers 140 may contact the first source / drain regions 160A and may be formed at both ends of each of the plurality of nanosheets N1, N2, and N3. In the space between the plurality of first finned active regions FAA and the plurality of nanosheets N1, N2, and N3, insulating spacers 140 may be disposed between the sub-gate cells 150S and the first source / drain regions 160A. In the second region R2, insulating spacers 140 may not be formed, and the second source / drain regions 160B may contact the gate dielectric layer 145.

[0079] Inter-gate insulating layer 172 and inter-layer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B. Each of the inter-gate insulating layer 172 and inter-layer insulating layer 174 may include a silicon oxide layer, but this disclosure is not limited thereto.

[0080] Multiple first contact plugs 192 can be connected to multiple first source / drain regions 160A and multiple second source / drain regions 160B. The multiple first contact plugs 192 can penetrate the interlayer insulating layer 174 and the intergate insulating layer 172, and can be connected to the multiple first source / drain regions 160A and multiple second source / drain regions 160B. A metal silicide layer 162 can be disposed between the multiple first source / drain regions 160A and the first contact plugs 192, and between the multiple second source / drain regions 160B and the first contact plugs 192. In some embodiments, the metal silicide layer 162 can be omitted.

[0081] Multiple second contact plugs 194 can be connected to multiple gate electrodes 150. The second contact plugs 194 can penetrate the interlayer insulating layer 174 and can be connected to the gate electrodes 150.

[0082] Each of the first contact plug 192 and the second contact plug 194 may include a metal, a conductive metal nitride, or a combination thereof.

[0083] In the integrated circuit device 1 conceived according to the present invention, each of the plurality of first transistors TRA formed in the first region R1 can be formed on an SOI substrate layer 100A, the SOI substrate layer 100A including a substrate layer 101, an insulating substrate layer 102 and a cover substrate layer 103 stacked in sequence, and each of the plurality of second transistors TRB formed in the second region R2 can be formed on a semiconductor substrate layer 100B.

[0084] Because the first transistor TRA is separated from the first impurity region 104 by the insulating substrate layer 102, no off-state leakage current of the first transistor TRA occurs in the first transistor TRA. Therefore, since the off-state leakage current of at least a plurality of first transistors TRA is reduced, the operating characteristics of the integrated circuit device 1 according to the present invention can be improved. The on-state current of the first transistor TRA is formed not only by using a stacked structure of multiple nanosheets N1, N2 and N3, but also by using a cover substrate layer 103 that is spaced from the first impurity region 104 by the insulating substrate layer 102. Therefore, since the on-state current of the plurality of first transistors TRA is increased, the output characteristics of the integrated circuit device 1 according to the present invention can be improved.

[0085] Furthermore, in the second region R2, multiple second source / drain regions 160B of the multiple second transistors TRB are formed by epitaxial growth using a semiconductor substrate 100B with a second impurity region 105 and a nanosheet stacked structure NSS of multiple nanosheets N1, N2, and N3 as seeds. Therefore, the multiple second source / drain regions 160B can have good crystallinity. Thus, the operating characteristics of the multiple second transistors TRB can be improved.

[0086] Therefore, the integrated circuit device 1 according to the present invention may include a plurality of first fin active regions FAA and a plurality of second fin active regions FAB, wherein the operating characteristics are improved, and thus reliability and improved operating characteristics can be ensured.

[0087] Figures 15 to 19 These are cross-sectional views of an integrated circuit device according to some embodiments. Figures 15 to 19 The description omits the reference. Figures 1 to 14B The given description is repetitive. Figures 15 to 19 This is a cross-sectional view showing the XZ surface.

[0088] Reference Figure 15 The integrated circuit device 1a may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of second transistors TRB disposed in a second region R2. Each of the first transistors TRA and the second transistors TRB may include a multi-gate MOSFET.

[0089] The integrated circuit device 1a may include: a plurality of first fin active regions FAA and a plurality of second fin active regions FAB protruding upward in the vertical direction (Z direction) from the main surface 100M of the substrate including the SOI substrate layer 100A and the semiconductor substrate layer 100B; and a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surface of the plurality of first fin active regions FAA and the plurality of second fin active regions FAA from a position spaced apart from the plurality of first fin active regions FAA and the plurality of second fin active regions FAA.

[0090] The multiple nanosheet stacked structure NSS can be spaced apart from the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB. The multiple nanosheet stacked structure NSS may include multiple nanosheets N1, N2 and N3 extending parallel to the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB on a substrate including SOI substrate layer 100A and semiconductor substrate layer 100B.

[0091] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions FAA and multiple second finned active regions FAB. The gate electrodes 150 may include a main gate unit 150M and multiple sub-gate units 150S. The main gate unit 150M covers the upper surface of the nanosheet stacked structure NSS; and the multiple sub-gate units 150S are connected to the main gate unit 150M and formed in the spaces between the multiple first finned active regions FAA and the multiple nanosheets N1, N2, and N3, and in the spaces between the multiple second finned active regions FAB and the multiple nanosheets N1, N2, and N3, i.e., below each of the multiple nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure NSS and the gate electrodes 150.

[0092] In the first region R1, multiple first source / drain regions 160A can be formed on multiple first fin-shaped active regions FAA, while in the second region R2, multiple second source / drain regions 160B can be formed on multiple second fin-shaped active regions FAB.

[0093] The integrated circuit device 1a may include an air gap AG between each of a plurality of first source / drain regions 160A and an insulating substrate layer 102. Figure 15 In the illustration, the air gap AG is shown disposed at the lower surface of the first recessed region RS1, but this is merely exemplary and the present disclosure is not limited thereto. For example, the air gap AG may be disposed between each of the plurality of first source / drain regions 160A and the insulating substrate layer 102, spanning the lower surface and lower sidewall of the first recessed region RS1. Because the air gap AG reduces parasitic capacitance, the operating characteristics of the integrated circuit device 1a can be improved.

[0094] Gate spacers 130 can be formed on multiple nanosheet stacked structures NSS, multiple first fin active regions FAA, and multiple second fin active regions FAB, sequentially covering the sidewalls of the gate electrode 150.

[0095] In the first region R1, insulating spacers 140 contacting the first source / drain region 160A may be formed at both ends of each of the plurality of nanosheets N1, N2, and N3. In the second region R2, insulating spacers 140 may not be formed, and the second source / drain region 160B may contact (e.g., directly contact) the gate dielectric layer 145.

[0096] Inter-gate insulating layer 172 and inter-layer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B. A plurality of first contact plugs 192 may be connected to the plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B. The plurality of first contact plugs 192 may penetrate the inter-layer insulating layer 174 and the inter-gate insulating layer 172, and may be connected to the plurality of first source / drain regions 160A and a plurality of second source / drain regions 160B. A metal silicide layer 162 may be disposed between the plurality of first source / drain regions 160A and the first contact plugs 192, and disposed between the plurality of second source / drain regions 160B and the first contact plugs 192.

[0097] Multiple second contact plugs 194 can be connected to multiple gate electrodes 150, such as Figure 14A No.

[0098] Reference Figure 16 The integrated circuit device 1b may include a plurality of first transistors TRAa disposed in a first region R1 and a plurality of second transistors TRB disposed in a second region R2. Each of the first transistors TRAa and the second transistors TRB may include a multi-gate MOSFET.

[0099] The integrated circuit device 1b may include: a plurality of first fin active regions FAA and a plurality of second fin active regions FAB protruding upward in the vertical direction (Z direction) from the main surface 100M of the substrate including the SOI substrate layer 100A and the semiconductor substrate layer 100B; and a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surface of the plurality of first fin active regions FAA and the plurality of second fin active regions FAA from a position spaced apart from the plurality of first fin active regions FAA and the plurality of second fin active regions FAA.

[0100] The multiple nanosheet stacked structure NSS can be separated from the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB. The multiple nanosheet stacked structure NSS may include multiple nanosheets N1, N2 and N3 extending parallel to the upper surfaces of multiple first fin active regions FAA and multiple second fin active regions FAB on a substrate including SOI substrate layer 100A and semiconductor substrate layer 100B.

[0101] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions FAA and multiple second finned active regions FAB. The gate electrodes 150 may include a main gate unit 150M and multiple sub-gate units 150S. The main gate unit 150M covers the upper surface of the nanosheet stacked structure NSS; and the multiple sub-gate units 150S are connected to the main gate unit 150M and formed in the spaces between the multiple first finned active regions FAA and the multiple nanosheets N1, N2, and N3, and in the spaces between the multiple second finned active regions FAB and the multiple nanosheets N1, N2, and N3, i.e., below each of the multiple nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure NSS and the gate electrodes 150.

[0102] In the first region R1, a plurality of first source / drain regions 160Aa can be formed on a plurality of first fin active regions FAA, while in the second region R2, a plurality of second source / drain regions 160B can be formed on a plurality of second fin active regions FAB. Each of the plurality of first source / drain regions 160Aa and the plurality of second source / drain regions 160B can be connected to the adjacent ends of a plurality of nanosheets N1, N2 and N3. In the first region R1, the plurality of first source / drain regions 160Aa can fill a plurality of first recess regions RS1a and extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160Aa can penetrate the covering substrate layer 103, but may not extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160Aa can contact the insulating substrate layer 102. In the first region R1, each of the plurality of first source / drain regions 160Aa may not contact the first impurity region 104. In the second region R2, a plurality of second source / drain regions 160B can fill a plurality of second recess regions RS2 and extend into the semiconductor substrate layer 100B, and the lower surfaces of the plurality of second source / drain regions 160B can contact the lower surface of the second impurity region 105. The lower surface of the first source / drain region 160Aa can be at a first vertical horizontal level LV1a, and the lower surfaces of the second source / drain regions 160B can be at a second vertical horizontal level LV2, which is higher than the first vertical horizontal level LV1a.

[0103] Gate spacers 130 can be formed on multiple nanosheet stacked structures NSS, multiple first fin active regions FAA, and multiple second fin active regions FAB, sequentially covering the sidewalls of the gate electrode 150.

[0104] In the first region R1, insulating spacers 140 contacting the first source / drain region 160Aa may be formed at both ends of each of the plurality of nanosheets N1, N2, and N3. In the second region R2, insulating spacers 140 may not be formed, and the second source / drain region 160B may contact (e.g., directly contact) the gate dielectric layer 145.

[0105] Inter-gate insulating layer 172 and inter-layer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160Aa and a plurality of second source / drain regions 160B. A plurality of first contact plugs 192 may be connected to the plurality of first source / drain regions 160Aa and a plurality of second source / drain regions 160B. The plurality of first contact plugs 192 may penetrate the inter-layer insulating layer 174 and the inter-gate insulating layer 172, and may be connected to the plurality of first source / drain regions 160Aa and a plurality of second source / drain regions 160B. A metal silicide layer 162 may be disposed between the plurality of first source / drain regions 160Aa and the first contact plugs 192, and between the plurality of second source / drain regions 160B and the first contact plugs 192.

[0106] Reference Figure 17 ,exist Figure 16 In the integrated circuit device 1b shown, all the lower surfaces of the plurality of first source / drain regions 160Aa can contact the upper surface of the insulating substrate layer 102 on the lower surface of the first recess region RS1a, but as Figure 17 The illustrated integrated circuit device 1c may include an air gap AGa disposed between each of the plurality of first source / drain regions 160Aa and the insulating substrate layer 102. For example, the air gap AGa may be disposed between each of the plurality of first source / drain regions 160Aa and the insulating substrate layer 102, spanning the lower surface of the first recess region RS1a. Because the air gap AGa reduces parasitic capacitance, the operating characteristics of the integrated circuit device 1c can be improved.

[0107] Reference Figure 18 The integrated circuit device 1d may include a plurality of first transistors TRAb disposed in a first region R1 and a plurality of second transistors TRB disposed in a second region R2. Each of the first transistors TRAb and the second transistors TRB may include a multi-gate MOSFET.

[0108] The integrated circuit device 1d may include a plurality of first source / drain regions 160Ab and a plurality of second source / drain regions 160B. In a first region R1, the plurality of first source / drain regions 160Ab may be formed on a plurality of first fin active regions FAA, while in a second region R2, the plurality of second source / drain regions 160B may be formed on a plurality of second fin active regions FAB. Each of the plurality of first source / drain regions 160Ab and the plurality of second source / drain regions 160B may be connected to adjacent ends of a plurality of nanosheets N1, N2, and N3. In the first region R1, the plurality of first source / drain regions 160Ab may fill a plurality of first recessed regions RS1b and extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160Ab may penetrate the covering substrate layer 103 and the insulating substrate layer 102 and extend into a first impurity region 104 of the base substrate layer 101. The lower surface of each of the plurality of first source / drain regions 160Ab can contact the substrate layer 101. In the first region R1, each of the plurality of first source / drain regions 160Ab can contact the first impurity region 104. In the second region R2, the plurality of second source / drain regions 160B can fill the plurality of second recess regions RS2 and extend into the semiconductor substrate layer 100B, and the lower surface of the plurality of second source / drain regions 160B can contact the lower surface of the second impurity region 105. The lower surface of the first source / drain region 160Ab can be at a first vertical horizontal level LV1b, and the lower surface of the second source / drain region 160B can be at a second vertical horizontal level LV2 above the first vertical horizontal level LV1b, or at a second vertical horizontal level LV2 further away from the main surface 100M.

[0109] In the first region R1, insulating spacers 140 contacting the first source / drain region 160Ab can be formed at both ends of each of the plurality of nanosheets N1, N2, and N3. In the second region R2, insulating spacers 140 may not be formed, and the second source / drain region 160B may contact (e.g., directly contact) the gate dielectric layer 145.

[0110] Reference Figure 19 ,exist Figure 18 In the integrated circuit device 1d shown, multiple first source / drain regions 160Ab can contact all side surfaces of the insulating substrate layer 102 on the side surface of the first recess region RS1b, but as Figure 19 The illustrated integrated circuit device 1e may include an air gap AGb disposed between each of the plurality of first source / drain regions 160Ab and the insulating substrate layer 102. For example, the air gap AGb may be disposed on the side of the first recess region RS1b between each of the plurality of first source / drain regions 160Ab and the insulating substrate layer 102. Because the air gap AGb reduces parasitic capacitance, the operating characteristics of the integrated circuit device 1e can be improved.

[0111] Figure 20A and Figure 20B This is a cross-sectional view of an integrated circuit device according to some embodiments. Figure 20A and Figure 20B This is a cross-sectional view showing the XZ surface.

[0112] Reference Figure 20A The integrated circuit device 2 may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of third transistors TRC disposed in a third region R3. Each of the first transistors TRA and the third transistors TRC may include a multi-gate MOSFET. In some embodiments, the first transistors TRA disposed in the first region R1 and the third transistors TRC disposed in the third region R3 may include multi-gate nMOSFETs. In some embodiments, one of the first region R1 and the third region R3 may be an SRAM region and the other may be a logic region.

[0113] The integrated circuit device 2 may include: a plurality of first fin active regions FAA and a plurality of third fin active regions FAC protruding upward in the vertical direction (Z direction) from the main surface 100M of the substrate including the SOI substrate layer 100A; and a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surfaces of the plurality of first fin active regions FAA and the plurality of third fin active regions FAA from a position spaced apart from the upper surfaces of the plurality of first fin active regions FAA and the plurality of third fin active regions FAA in the vertical direction (Z direction).

[0114] The multiple nanosheet stacked structure NSS can be spaced apart from the upper surfaces of multiple first fin active regions FAA and multiple third fin active regions FAC. The multiple nanosheet stacked structure NSS can include multiple nanosheets N1, N2 and N3 extending parallel to the upper surfaces of multiple first fin active regions FAA and multiple third fin active regions FAC on a substrate including SOI substrate layer 100A.

[0115] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions (FAAs) and multiple third finned active regions (FACs). The gate electrodes 150 may include a main gate unit 150M and multiple sub-gate units 150S. The main gate unit 150M covers the upper surface of the nanosheet stacked structure (NSS); and the multiple sub-gate units 150S are connected to the main gate unit 150M and formed in the spaces between the multiple first finned active regions (FAAs) and multiple nanosheets N1, N2, and N3, and in the spaces between the multiple third finned active regions (FACs) and multiple nanosheets N1, N2, and N3, i.e., below each of the multiple nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure (NSS) and the gate electrodes 150.

[0116] In the first region R1, a plurality of first source / drain regions 160A can be formed on a plurality of first fin active regions FAA, while in the third region R3, a plurality of third source / drain regions 160C can be formed on a plurality of third fin active regions FAA. In some embodiments, the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160C can comprise the same material as each other. For example, the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160C can comprise Si, but not Ge. Each of the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160C can be connected to adjacent ends of a plurality of nanosheets N1, N2 and N3. In the first region R1, the plurality of first source / drain regions 160A can fill a plurality of first recessed regions RS1 and extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160A can penetrate the cover substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A can contact the insulating substrate layer 102. In the third region R3, a plurality of third source / drain regions 160C can fill a plurality of third recessed regions RS3 and extend into the SOI substrate layer 100A. In some embodiments, in the third region R3, each of the plurality of third source / drain regions 160C can penetrate the cover substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of third source / drain regions 160C can contact the insulating substrate layer 102. The lower surface of the first source / drain region 160A can be at a first vertical level LV1, and the lower surface of the third source / drain region 160C can be located at a third vertical level LV3 above the first vertical level LV1, or at a third vertical level LV3 further away from the main surface 100M.

[0117] Gate spacers 130 can be formed on multiple nanosheet stacked structures NSS, multiple first fin active regions FAA, and multiple third fin active regions FAC, sequentially covering the sidewalls of the gate electrode 150.

[0118] In the first region R1, insulating spacers 140 contacting the first source / drain region 160A can be formed at both ends of each of the plurality of nanosheets N1, N2 and N3, and in the third region R3, insulating spacers 140 contacting the third source / drain region 160C can be formed at both ends of each of the plurality of nanosheets N1, N2 and N3.

[0119] Inter-gate insulating layer 172 and inter-layer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160Aa and a plurality of third source / drain regions 160C. A plurality of first contact plugs 192 may be connected to the plurality of first source / drain regions 160Aa and a plurality of third source / drain regions 160C. The plurality of first contact plugs 192 may penetrate the inter-layer insulating layer 174 and the inter-gate insulating layer 172, and may be connected to the plurality of first source / drain regions 160Aa and a plurality of third source / drain regions 160C. A metal silicide layer 162 may be disposed between the plurality of first source / drain regions 160Aa and the first contact plugs 192, and between the plurality of third source / drain regions 160C and the first contact plugs 192.

[0120] Reference Figure 20B The integrated circuit device 2a may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of third transistors TRCa disposed in a third region R3. Each of the first transistors TRA and TRCa may include a multi-gate MOSFET. In some embodiments, the first transistors TRA disposed in the first region R1 and TRCa disposed in the third region R3 may include multi-gate nMOSFETs. In some embodiments, one of the first region R1 and the third region R3 may be an SRAM region and the other may be a logic region.

[0121] In the first region R1, a plurality of first source / drain regions 160A can be formed on a plurality of first fin active regions FAA, while in the third region R3, a plurality of third source / drain regions 160Ca can be formed on a plurality of third fin active regions FAA. In some embodiments, the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160Ca can comprise the same material as each other. For example, the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160Ca can comprise Si, but not Ge. Each of the plurality of first source / drain regions 160A and the plurality of third source / drain regions 160Ca can be connected to adjacent ends of a plurality of nanosheets N1, N2 and N3. In the first region R1, the plurality of first source / drain regions 160A can fill a plurality of first recessed regions RS1 and extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160A can penetrate the cover substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A can contact the insulating substrate layer 102. In the third region R3, the plurality of third source / drain regions 160Ca can fill the plurality of third recess regions RS3a and extend into the SOI substrate layer 100A. In some embodiments, in the third region R3, each of the plurality of third source / drain regions 160Ca can penetrate the cover substrate layer 103 and the insulating substrate layer 102 and extend into the first impurity region 104 of the substrate layer 101, and the lower surface of each of the plurality of third source / drain regions 160Ca can contact the first impurity region 102. The lower surface of the first source / drain region 160A may be located at the first vertical level LV1, and the lower surface of the third source / drain region 160Ca may be located at the third vertical level LV3a below the first vertical level LV1, or at the third vertical level LV3a closer to the main surface 100M.

[0122] Figure 21 This is a cross-sectional view of an integrated circuit device according to an embodiment. Figure 21 This is a cross-sectional view showing the XZ surface.

[0123] Reference Figure 21 The integrated circuit device 3 may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of fourth transistors TRD disposed in a fourth region R4. Each of the first transistors TRA and the fourth transistors TRD may include a multi-gate MOSFET. In some embodiments, the first transistors TRA disposed in the first region R1 and the fourth transistors TRD disposed in the fourth region R4 may include multi-gate nMOSFETs. In some embodiments, one of the first region R1 and the fourth region R4 may be an SRAM region and the other may be a logic region.

[0124] The integrated circuit device 3 may include: a plurality of first fin active regions FAA and a plurality of fourth fin active regions FAD protruding upward in the vertical direction (Z direction) from the main surface 100M of the substrate, including the SOI substrate layer 100A and the semiconductor substrate layer 100B; and a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surface of the plurality of first fin active regions FAA and the plurality of fourth fin active regions FAA from a position spaced apart from the plurality of first fin active regions FAA and the plurality of fourth fin active regions FAA. The plurality of first fin active regions FAA may protrude upward in the vertical direction (Z direction) from the main surface 100M of the SOI substrate layer 100A in the first region R1, and the plurality of fourth fin active regions FAA may protrude upward in the vertical direction (Z direction) from the main surface 100M of the semiconductor substrate layer 100B in the fourth region R4.

[0125] Instead of Figure 14A and Figure 14B The integrated circuit device 1 shown has a second impurity region 105 formed in the second region R2 on the semiconductor substrate layer 100B. The integrated circuit device 4 may include a third impurity region 104a formed in the fourth region R4 on the semiconductor substrate layer 100B. The first impurity region 104a can be formed by implanting an impurity with first conductivity into a portion of the SOI substrate layer 100A, and the third impurity region 104a can be formed by implanting an impurity with first conductivity into a portion of the semiconductor substrate layer 100B. In some embodiments, the shape of the third impurity region 104a may be similar to... Figure 14A and Figure 14B The second impurity region 105 shown has a basically the same shape.

[0126] A multi-nanosheet stacked structure (NSS) can be spaced apart from the upper surfaces of multiple first-fin active regions (FAAs) and multiple fourth-fin active regions (FADs). The multi-nanosheet stacked structure (NSS) can include multiple nanosheets N1, N2, and N3 extending parallel to the upper surfaces of the multiple first-fin active regions (FAAs) and multiple fourth-fin active regions (FADs) on a substrate including an SOI substrate layer 100A and a semiconductor substrate layer 100B. The multiple nanosheets N1, N2, and N3 of a single nanosheet stacked structure (NSS) can be sequentially stacked one after another on the upper surfaces of the multiple first-fin active regions (FAAs) and multiple fourth-fin active regions (FADs).

[0127] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions (FAAs) and multiple fourth finned active regions (FADs). Each of the multiple gate electrodes 150 may cover and surround at least a portion of the nanosheet stacked structure (NSS). The gate electrode 150 may include a main gate unit 150M and multiple sub-gate units 150S, the main gate unit 150M covering the upper surface of the nanosheet stacked structure (NSS); and the multiple sub-gate units 150S connected to the main gate unit 150M and formed in the space between the multiple first finned active regions (FAAs) and the multiple nanosheets N1, N2, and N3, and in the space between the multiple fourth finned active regions (FADs) and the multiple nanosheets N1, N2, and N3, i.e., below each of the multiple nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure (NSS) and the gate electrode 150.

[0128] In the first region R1, a plurality of first source / drain regions 160A can be formed on a plurality of first fin-shaped active regions FAA, while in the fourth region R4, a plurality of fourth source / drain regions 160D can be formed on a plurality of fourth fin-shaped active regions FAD. Each of the plurality of first source / drain regions 160A and the plurality of fourth source / drain regions 160D can be connected to an adjacent end of a plurality of nanosheets N1, N2, and N3. In some embodiments, the plurality of first source / drain regions 160A and the plurality of fourth source / drain regions 160D can comprise the same material as each other.

[0129] In the first region R1, each of the plurality of first source / drain regions 160A may extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160A may penetrate the overlay substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A may contact the insulating substrate layer 102. In the fourth region R4, each of the plurality of fourth source / drain regions 160D may extend into the semiconductor substrate layer 100B, and the lower surface of each of the plurality of fourth source / drain regions 160D may contact the third impurity region 104a. The lower surface of the first source / drain region 160A may be at a first vertical level LV1, and the lower surface of the fourth source / drain region 160D may be located at a fourth vertical level LV4 above the first vertical level LV1, or at a fourth vertical level LV4 further away from the main surface 100M.

[0130] Gate spacers 130 can be formed on multiple nanosheet stacked structures NSS, multiple first fin active regions FAA, and multiple fourth fin active regions FAD, sequentially covering the sidewalls of the gate electrode 150.

[0131] In the first region R1, insulating spacers 140 contacting the first source / drain region 160A can be formed at both ends of each of the plurality of nanosheets N1, N2 and N3, and in the fourth region R4, insulating spacers 140 contacting the fourth source / drain region 160D can be formed at both ends of each of the plurality of nanosheets N1, N2 and N3.

[0132] Inter-gate insulating layer 172 and inter-layer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160A and a plurality of fourth source / drain regions 160D. Each of the inter-gate insulating layer 172 and inter-layer insulating layer 174 may include a silicon oxide layer, but this disclosure is not limited thereto.

[0133] Multiple first contact plugs 192 can be connected to multiple first source / drain regions 160A and multiple fourth source / drain regions 160D. The multiple first contact plugs 192 can penetrate the interlayer insulating layer 174 and the intergate insulating layer 172, and can be connected to the multiple first source / drain regions 160A and multiple fourth source / drain regions 160D. A metal silicide layer 162 can be disposed between the multiple first source / drain regions 160A and the first contact plugs 192, and between the multiple fourth source / drain regions 160D and the first contact plugs 192.

[0134] Figures 22A to 23B This is a cross-sectional view showing a method for manufacturing an integrated circuit device according to some embodiments, and a cross-sectional view describing an integrated circuit device manufactured using the manufacturing method according to manufacturing steps. Figures 22A to 23A This is a cross-sectional view showing the YZ surface. Figure 23B It shows along Figure 23A The cross-sectional view of the YZ surface intercepted by the V1-V1′ and V5-V5′ lines.

[0135] Reference Figure 22A A stacked structure formed by alternately stacking multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS can be formed on a substrate including a first region R1 where an SOI substrate layer 100A is disposed and a fifth region R5 where a semiconductor substrate layer 100B is disposed. The stacking groove SR can be formed by removing a portion of the stacked structure of multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS formed in the fifth region R5. As a result, the upper surface of the semiconductor substrate layer 100B can be exposed in the fifth region R5. In some embodiments, the semiconductor substrate layer 100B in the fifth region R5 can be... Figure 5 The semiconductor substrate layer 100B in the second region R2 shown is basically the same.

[0136] Reference Figure 22BThe semiconductor epitaxial layer 110 can be formed on the semiconductor substrate layer 100B in the fifth region R5. The semiconductor epitaxial layer 110 may include a semiconductor material. The semiconductor epitaxial layer 110 may be formed to have the same crystal structure as the semiconductor substrate layer 100B. In some embodiments, the semiconductor epitaxial layer 110 may include a semiconductor material of the same type as the semiconductor substrate layer 100B. In some embodiments, the semiconductor epitaxial layer 110 may include a semiconductor material of a different type having the same crystal structure as the semiconductor substrate layer 100B.

[0137] The semiconductor epitaxial layer 110 may be formed with impurities having the same conductivity as the second impurity region 105. For example, an impurity with the second conductivity may be implanted into the semiconductor epitaxial layer 110.

[0138] In some embodiments, in the fifth region R5, similar to Figure 5 The first region R1 can be formed by alternately stacking multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS on the SOI substrate layer 100A, then removing all portions formed in the stacked structure of multiple sacrificial semiconductor layers 106S and multiple nanosheet semiconductor layers NS in the fifth region R5, as well as the portions of the covering substrate layer 103 and insulating substrate layer 102 in the fifth region R5, and then forming an epitaxial layer and a semiconductor epitaxial layer 110 corresponding to the second impurity region 105 by epitaxial growth, to form a structure similar to the second impurity region 105. Figure 22B The structure shown.

[0139] Refer to together Figure 23A and Figure 23B It can be done by... Figure 22B Result execution and reference Figures 6 to 14B The processes described are similar to those used to form the integrated circuit device 4. The integrated circuit device 4 may include: a plurality of first fin active regions FAA and a plurality of fifth fin active regions FAE protruding upward in the vertical direction (Z direction) from the main surface 100M of a substrate including an SOI substrate layer 100A and a semiconductor substrate layer 100B; and a plurality of nanosheet stacked structures NSS, wherein the plurality of nanosheet stacked structures NSS face the upper surface of the plurality of first fin active regions FAA from a position spaced apart from the upper surface of the plurality of first fin active regions FAA in a first region R1. The plurality of first fin active regions FAA may protrude upward in the vertical direction (Z direction) from the main surface 100M of the SOI substrate layer 100A in the first region R1, and the plurality of fifth fin active regions FAE may protrude upward in the vertical direction (Z direction) from the main surface 100M of the semiconductor substrate layer 100B in a fifth region R5.

[0140] Multiple trench TREs can confine or define multiple first fin active regions (FAAs) and multiple fifth fin active regions (FAEs) on a substrate including an SOI substrate layer 100A and a semiconductor substrate layer 100B. The sidewalls of the multiple first fin active regions (FAAs) and multiple fifth fin active regions (FAEs) can be covered by a device separation layer 118 that fills the multiple trench TREs. The horizontal distance of the upper surface of the multiple first fin active regions (FAAs) from the main surface to 100M, the horizontal distance of the upper surface of the second impurity region 105 of the multiple fifth fin active regions (FAEs) from the main surface to 100M, and the horizontal distance of the upper surface of the device separation layer 118 from the main surface to 100M can be equal, identical, or similar to each other.

[0141] Multiple nanosheet stacked structures (NSS) can be spaced apart from the upper surfaces of multiple first fin active regions (FAAs). The multiple nanosheet stacked structures (NSS) can include multiple nanosheets N1, N2, and N3 extending parallel to the upper surfaces of the multiple first fin active regions (FAAs) on the SOI substrate layer 100A. The multiple nanosheets N1, N2, and N3 of a single nanosheet stacked structure (NSS) can be sequentially stacked one after another on the upper surfaces of the multiple first fin active regions (FAAs).

[0142] A nanosheet stacked structure NSS of multiple nanosheets N1, N2, and N3 can be arranged in a first region R1 on multiple first fin active regions FAA, and can be located in a fifth region R5 at a substantially the same level as the semiconductor epitaxial layer 110 of each of the multiple fifth fin active regions FAA. In other words, the nanosheet stacked structure NSS of multiple nanosheets N1, N2, and N3 can be arranged in the first region R1 on multiple first fin active regions FAA, so that it is located at a substantially the same level as the semiconductor epitaxial layer 110 above the multiple fifth fin active regions FAA in the fifth region R5, 100M from the main surface.

[0143] Multiple gate electrodes 150 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction), and may extend over multiple first finned active regions (FAAs) and multiple fifth finned active regions (FAEs). At least a portion of the multiple gate electrodes 150 may overlap in the vertical direction (Z direction) with each of the multiple nanosheet stacked structures (NSS) in the first region R1, and may also overlap in the vertical direction (Z direction) with the multiple fifth finned active regions (FAEs) in the fifth region R5.

[0144] In the first region R1, each of the plurality of gate electrodes 150 may cover and surround at least a portion of the nanosheet stacked structure NSS. In the first region R1, the gate electrode 150 may include a main gate unit 150M and a plurality of sub-gate units 150S, the main gate unit 150M covering the upper surface of the nanosheet stacked structure NSS; and the plurality of sub-gate units 150S connected to the main gate unit 150M and formed in the space between the first fin-type active region FAA and the plurality of nanosheets N1, N2, and N3, i.e., below each of the plurality of nanosheets N1, N2, and N3. A gate dielectric layer 145 may separate the nanosheet stacked structure NSS from the gate electrode 150.

[0145] In the fifth region R5, multiple gate electrodes 150 may cover the surfaces of multiple fifth fin active regions (FAEs). In the fifth region R5, the multiple gate electrodes 150 may include only the main gate cell 150M and may not include the sub-gate cells 150S. A gate dielectric layer 145 may separate the fifth fin active regions (FAEs) and the gate electrodes 150.

[0146] In the first region R1, a plurality of first source / drain regions 160A can be formed on a plurality of first fin active regions FAA. In the first region R1, each of the plurality of first source / drain regions 160A can be connected to an adjacent end of a plurality of nanosheets N1, N2, and N3. In the fifth region R5, a plurality of fifth source / drain regions 160E can be connected to the sidewalls of adjacent fifth fin active regions FAA. In the first region R1, each of the plurality of first source / drain regions 160A can extend into the SOI substrate layer 100A. In some embodiments, in the first region R1, each of the plurality of first source / drain regions 160A can penetrate the covering substrate layer 103 and extend into the insulating substrate layer 102, and the lower surface of each of the plurality of first source / drain regions 160A can contact the insulating substrate layer 102. In the fifth region R5, each of the plurality of fifth source / drain regions 160E may extend into the semiconductor substrate layer 100B, and the lower surface of each of the plurality of fifth source / drain regions 160E may contact the second impurity region 105. The lower surface of the first source / drain region 160A may be at the first vertical level LV1, and the lower surface of the fifth source / drain region 160E may be located at a fifth vertical level LV5 above the first vertical level LV1, or at a fifth vertical level LV5 further away from the main surface 100M.

[0147] The integrated circuit device 4 may include a plurality of first transistors TRA disposed in a first region R1 and a plurality of fifth transistors TRS disposed in a fifth region R5. The first transistors TRA may include multi-gate MOSFETs, and the fifth transistors TRS may include single-gate MOSFETs. In some embodiments, the first transistors TRA disposed in the first region R1 may include multi-gate nMOSFETs, and the fifth transistors TRS disposed in the fifth region R5 may include multi-gate pMOSFETs. In some other embodiments, the first transistors TRA disposed in the first region R1 may include multi-gate nMOSFETs, and the fifth transistors TRS disposed in the fifth region R5 may include multi-gate nMOSFETs.

[0148] Gate spacers 130 can be formed sequentially covering the sidewalls of the gate electrode 150 on multiple nanosheet stacked structures NSS and multiple fifth fin active regions FAE. In the first region R1, insulating spacers 140 contacting the first source / drain regions 160A can be formed at both ends of each of the multiple nanosheets N1, N2 and N3.

[0149] Intergate insulating layer 172 and interlayer insulating layer 174 may be sequentially formed on a plurality of first source / drain regions 160A and a plurality of fifth source / drain regions 160E.

[0150] Multiple first contact plugs 192 can be connected to multiple first source / drain regions 160A and multiple fifth source / drain regions 160E. The multiple first contact plugs 192 can penetrate the interlayer insulating layer 174 and the intergate insulating layer 172, and can be connected to the multiple first source / drain regions 160A and multiple fifth source / drain regions 160E. A metal silicide layer 162 can be disposed between the multiple first source / drain regions 160A and the first contact plugs 192, and between the multiple fifth source / drain regions 160E and the first contact plugs 192.

[0151] Multiple second contact plugs 194 can be connected to multiple gate electrodes 150. The second contact plugs 194 can penetrate the interlayer insulating layer 174 and connect to the gate electrodes 150.

[0152] In some embodiments of this disclosure, the integrated circuit device may include, for example: Figures 1 to 23B At least two of the first region R1, second region R2, third region R3, fourth region R4, and / or fifth region R5, as shown and described with reference to integrated circuit devices 1, 1a, 1b, 1c, 1d, 1e, 2, 2a, 3, and 4. Given the foregoing discussion, those skilled in the art should readily understand such embodiments, and therefore they will not be shown separately.

[0153] Furthermore, among components arranged in at least two of the first region R1, second region R2, third region R3, fourth region R4, and fifth region R5, components arranged in different regions can be separately and distinctly referred to as first, second, etc. For example, a nanosheet stacked structure NSS comprising multiple nanosheets N1, N2, and N3 arranged in the first region R1 and the second region R2 can be respectively referred to as a first nanosheet stacked structure comprising multiple first nanosheets and a second nanosheet stacked structure comprising multiple second nanosheets.

[0154] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the scope of the claims.

Claims

1. An integrated circuit device, comprising: The first region includes a semiconductor-on-insulator (SOI) substrate layer, wherein the SOI substrate layer includes a base substrate layer, an insulating substrate layer, and a cover substrate layer. The second region includes the semiconductor substrate layer; Multiple first fin-shaped active regions are defined in the first regions by multiple first trenches, and the first fin-shaped active regions protrude from the main surface of the SOI substrate layer and extend in a first horizontal direction; Multiple second fin-shaped active regions are defined by multiple second trenches in the second regions, and the second fin-shaped active regions protrude from the main surface of the semiconductor substrate layer and extend in the first horizontal direction; A plurality of nanosheet stacked structures above the plurality of first fin active regions and the plurality of second fin active regions, each of the plurality of nanosheet stacked structures comprising a plurality of nanosheets extending parallel to each other and spaced apart from the upper surfaces of the plurality of first fin active regions and the plurality of second fin active regions. Multiple first source / drain regions are located between adjacent nanosheet stacks in the first region, each of the first source / drain regions extending into the SOI substrate layer and contacting the insulating substrate layer, and having a lower surface located at a first vertical horizontal position; as well as A plurality of second source / drain regions, each of which extends into the semiconductor substrate layer in the second region and has a lower surface at a second vertical level, the second vertical level being farther away from the SOI substrate layer and the main surface of the semiconductor substrate layer than the first vertical level.

2. The integrated circuit device according to claim 1, wherein, The plurality of first source / drain regions extend through the cover substrate layer and into the insulating substrate layer.

3. The integrated circuit device according to claim 1, wherein, The plurality of first source / drain regions extend through the cover substrate layer and contact the insulating substrate layer, but do not extend into the insulating substrate layer.

4. The integrated circuit device according to claim 1, wherein, The plurality of first source / drain regions extend through the cover substrate layer and the insulating substrate layer and contact the base substrate layer.

5. The integrated circuit device according to claim 1, further comprising: The third region includes the SOI substrate layer; Multiple third fin-shaped active regions are defined by multiple third trenches in the third regions, the third fin-shaped active regions protruding from the main surface of the SOI substrate layer and extending in the first horizontal direction; The nanosheet stacked structure above the plurality of third fin active regions, each nanosheet stacked structure comprising a plurality of nanosheets; as well as Multiple third source / drain regions are located between adjacent nanosheet stacks above the multiple third fin active regions. The multiple third source / drain regions extend into the SOI substrate layer to contact the insulating substrate layer. The lower surfaces of the multiple third source / drain regions are located at a third vertical level above the main surfaces of the SOI substrate layer and the semiconductor substrate layer. The third vertical level is different from the first vertical level.

6. The integrated circuit device according to claim 5, wherein, Each of the plurality of first source / drain regions and the plurality of third source / drain regions extends through the cover substrate layer and into the insulating substrate layer, and The first vertical horizontal plane is closer to the main surface of the SOI substrate layer and the semiconductor substrate layer than the third vertical horizontal plane.

7. The integrated circuit device according to claim 5, wherein, The plurality of first source / drain regions extend through the cover substrate layer and into the insulating substrate layer. The plurality of third source / drain regions extend through the cover substrate layer and the insulating substrate layer, and contact the base substrate layer, and Wherein, the first vertical horizontal plane is farther away from the main surface of the SOI substrate layer and the semiconductor substrate layer than the third vertical horizontal plane.

8. The integrated circuit device according to claim 1, further comprising: Multiple gate electrodes extend in a second horizontal direction intersecting the first horizontal direction. The multiple gate electrodes extend over the multiple first fin-shaped active regions and the multiple second fin-shaped active regions. Each of the multiple gate electrodes includes a main gate unit and multiple sub-gate units. The main gate unit is above a corresponding nanosheet stack in the multiple nanosheet stacked structures, and the multiple sub-gate units are below each nanosheet of the corresponding nanosheet stack in the multiple nanosheet stacked structures. as well as A gate dielectric layer separates the plurality of gate electrodes and the plurality of nanosheet stacked structures.

9. The integrated circuit device according to claim 8, further comprising: In the first region, there are multiple insulating spacers between the multiple first source / drain regions and the multiple nanosheets, the multiple insulating spacers covering the first and second ends of the multiple sub-gate units, wherein the gate dielectric layer is located between the multiple sub-gate units and the multiple insulating spacers.

10. The integrated circuit device according to claim 9, wherein, In the second region, the gate dielectric layer is disposed between the plurality of sub-gate cells and the plurality of second source / drain regions, and directly contacts the plurality of sub-gate cells and the plurality of second source / drain regions.

11. The integrated circuit device according to claim 1, further comprising: The fourth region includes the semiconductor substrate layer; Multiple fourth-fin active regions are defined by multiple trenches and extend in the first horizontal direction; The nanosheet stacked structure above the plurality of fourth fin active regions, each nanosheet stacked structure comprising a plurality of nanosheets; as well as A plurality of fourth source / drain regions are located between adjacent nanosheet stacks above the plurality of fourth fin active regions, each of the plurality of fourth source / drain regions extending into the semiconductor substrate layer and comprising the same material as the plurality of first source / drain regions.

12. The integrated circuit device according to claim 1, further comprising: The air gap between the plurality of first source / drain regions and the insulating substrate layer.

13. An integrated circuit device, comprising: The semiconductor-on-insulator (SOI) substrate layer includes a base substrate layer, an insulating substrate layer, and a cover substrate layer in a first region. Semiconductor substrate layer, in the second region; Multiple first fin-shaped active regions and multiple second fin-shaped active regions are defined by multiple trenches on the SOI substrate layer and the semiconductor substrate layer, respectively, and extend in a first horizontal direction. Multiple first nanosheets extend parallel to each other and are separated from the multiple first fin-shaped active regions in the vertical direction; Multiple gate electrodes extend in a second horizontal direction intersecting the first horizontal direction, the multiple gate electrodes being located on the multiple first fin active regions and the multiple second fin active regions, with the first portions of the multiple gate electrodes being located between vertically adjacent first nanosheets; A gate dielectric layer is located between the first nanosheet and the plurality of first fin-type active regions; A plurality of first source / drain regions are located between horizontally adjacent first nanosheets above the plurality of first fin active regions. Each of the plurality of first source / drain regions extends into the SOI substrate layer to contact the insulating substrate layer and has a lower surface located at a first vertical horizontal position above the plurality of first fin active regions. as well as A plurality of second source / drain regions are located above the plurality of second fin active regions. Each of the plurality of second source / drain regions extends into the semiconductor substrate layer and has a lower surface located at a second vertical level above the plurality of second fin active regions, the second vertical level being higher than the first vertical level.

14. The integrated circuit device of claim 13, further comprising a plurality of second nanosheets extending parallel to each other and spaced apart in the vertical direction from the plurality of second fin active regions. in, The second portion of the plurality of gate electrodes is located between vertically adjacent second nanosheets.

15. The integrated circuit device according to claim 13, wherein, At least one of the first nanosheets is coplanar with the upper part of at least one of the plurality of second fin active regions.

16. The integrated circuit device according to claim 13, further comprising: The first impurity region includes a first impurity type in a portion of the SOI substrate layer; And a second impurity region, in a portion of the semiconductor substrate, contacting the plurality of second source / drain regions and including a second impurity type.

17. The integrated circuit device according to claim 16, wherein, The first impurity region is disposed in a portion of the upper side of the substrate layer, and The plurality of first source / drain regions do not contact the first impurity region.

18. The integrated circuit device according to claim 16, wherein, The first impurity region is disposed in a portion of the upper side of the substrate layer, and The plurality of first source / drain regions are in contact with the first impurity region.

19. An integrated circuit device, comprising: The semiconductor-on-insulator (SOI) substrate layer includes a base substrate layer, an insulating substrate layer, and a cover substrate layer in a first region. A semiconductor substrate layer, in a second region different from the first region; The first impurity region, in a portion of the SOI substrate layer, includes a first impurity type; The second impurity region, in a portion of the semiconductor substrate layer, includes a second impurity type; Multiple first fin-shaped active regions and multiple second fin-shaped active regions are defined by multiple trenches on the SOI substrate layer and the semiconductor substrate layer, respectively, and extend in a first horizontal direction. Multiple nanosheet stacked structures, each nanosheet stacked structure comprising multiple nanosheets extending parallel to each other and spaced apart from the upper surfaces of the multiple first fin active regions and the multiple second fin active regions; A plurality of first source / drain regions are connected to the ends of the plurality of nanosheets adjacent to each other on the plurality of first fin active regions, the plurality of first source / drain regions extending through the cover substrate layer and into the insulating substrate layer, and including a lower surface located at a first vertical horizontal position; Multiple second source / drain regions extend over multiple second fin active regions into a semiconductor substrate layer and contact a second impurity region, the multiple second source / drain regions including a lower surface located at a second vertical level, the second vertical level being higher than the first vertical level; Multiple gate electrodes extend in a second horizontal direction intersecting the first horizontal direction. The multiple gate electrodes extend over the multiple first fin active regions and the multiple second fin active regions. Each of the multiple gate electrodes includes a main gate unit and multiple sub-gate units, wherein the main gate unit is above a corresponding nanosheet stack in the multiple nanosheet stacked structures, and each sub-gate unit is below a corresponding nanosheet in the multiple nanosheets of the corresponding nanosheet stacked structure. as well as A gate dielectric layer is disposed between the plurality of gate electrodes and the plurality of nanosheets; as well as Multiple insulating spacers are located in a first region between the multiple first fin active regions and the multiple nanosheets, the multiple insulating spacers covering the first and second ends of each of the multiple sub-gate units, wherein the gate dielectric layer is located between the multiple insulating spacers and the multiple sub-gate units.

20. The integrated circuit device of claim 19, wherein the insulating substrate layer has a thickness of about 10 nm to about 20 nm. in, The lower surfaces of the plurality of first source / drain regions contact the insulating substrate layer, and The first impurity region does not contact the lower surface of the plurality of first source / drain regions.

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