Method for preparing SOI substrate

Abstract

Provided in the present application is a method for preparing an SOI substrate. The method comprises: providing a device substrate and a support substrate; forming an oxide layer on a surface of at least one of the device substrate and the support substrate; implanting blistering ions into the device substrate; implanting modifying ions above a region of the device substrate in which the blistering ions are implanted, wherein the modifying ions are Ar ions; bonding the device substrate to the support substrate; and performing annealing to strip the device substrate at the position where the blistering ions are implanted, so as to form an SOI substrate. In the present application, Ar ions are used as modifying ions and are implanted into a device layer, such that an effective bonding area between a device substrate and a support substrate can be increased, and the size of a suspended portion on the edge of the device layer can be relatively reduced, thereby reducing the risks of subsequent edge breakage and fragmentation.

Description

SOI substrate preparation method

[0001] Related application citation instructions

[0002] This application claims priority to Chinese Patent Application No. 202411890717.8, filed on December 20, 2024, entitled "Method for Preparing SOI Substrate", the entire contents of which are appended herein by reference. Technical Field

[0003] This application relates to the field of semiconductor processes, and more particularly to a method for preparing an SOI substrate. Background Technology

[0004] With the development of semiconductor manufacturing technology, integrated circuits have been widely used in many fields. Among them, devices based on silicon-on-insulator (SOI) technology have the characteristics of high temperature resistance and radiation resistance, making them suitable for traditional fields such as aerospace. At the same time, the advantages of SOI technology, such as low power consumption, high speed, and high integration, are the foundation for the design and fabrication of high-speed, low-power integrated circuits, which can be applied to emerging fields such as autonomous driving and the Internet of Things.

[0005] Bonding is the most common method for preparing SOI materials. After bonding, the chamfer of the wafer creates a suspended region around the perimeter. Controlling the size of this region is a key factor in improving the quality of SOI crystals. Summary of the Invention

[0006] The technical problem to be solved by this application is to provide a method for fabricating SOI substrates that can suppress the size of the surrounding suspended regions.

[0007] To address the aforementioned problems, this application provides a method for preparing an SOI substrate, comprising: providing a device substrate and a support substrate; forming an oxide layer on the surface of at least one of the device substrate and the support substrate; implanting bubble-forming ions into the device substrate; implanting modified ions, wherein the modified ions are Ar ions, above the implanted region of the bubble-forming ions in the device substrate; bonding the device substrate and the support substrate; and annealing to peel off the device substrate at the location where the bubble-forming ions were implanted, thereby forming an SOI substrate.

[0008] Optionally, the energy range of the Ar ion implantation is 50-150 keV, and the dose range is 1E14-1E16 cm⁻¹. -2 .

[0009] Optionally, the foaming ion is selected from one or a combination of H ions and He ions.

[0010] Optionally, the device substrate is a single-crystal silicon substrate.

[0011] Optionally, a high-temperature reinforcement process is performed after bonding to enhance the bonding strength.

[0012] This application uses Ar ions implanted as modified ions into the device layer, which can expand the effective bonding area between the device substrate and the support substrate, and relatively reduce the size of the suspended part at the edge of the device layer, thereby reducing the risk of subsequent edge chipping and breakage. Attached Figure Description

[0013] Figure 1 shows a schematic diagram of the implementation steps of the SOI substrate preparation method according to a specific embodiment of this application.

[0014] Figures 2A to 2E show the process flow diagram of the SOI substrate preparation method according to a specific embodiment of this application.

[0015] Figure 3 is a top view of the wafer obtained by the SOI substrate fabrication method described in a specific embodiment of this application.

[0016] Figure 4 shows the comparison results of edge overhang dimension tests of wafers obtained by the SOI substrate preparation method described in a specific embodiment of this application. Detailed Implementation

[0017] The specific implementation methods of the bonding method and SOI substrate preparation method provided in this application will be described in detail below with reference to the accompanying drawings.

[0018] Figure 1 shows a schematic diagram of the implementation steps of the SOI substrate preparation method according to a specific embodiment of this application, including: step S10, providing a device substrate and a support substrate; step S11, forming an oxide layer on the surface of at least one of the device substrate and the support substrate; step S12, implanting foaming ions into the device substrate; step S13, implanting modified ions, wherein the modified ions are Ar ions, above the implanted region of the foaming ions in the device substrate; step S14, bonding the device substrate and the support substrate; and step S15, annealing to peel off the device substrate at the implanted location of the foaming ions to form an SOI substrate.

[0019] Figures 2A to 2E show the process flow diagram of the SOI substrate preparation method according to a specific embodiment of this application.

[0020] As shown in Figure 2A, referring to step S10, a device substrate 10 and a support substrate 20 are provided. The device substrate 10 and the support substrate 20 can be wafers of any common semiconductor material, including silicon, germanium, silicon carbide, GaAs, and GaN. In this specific embodiment, both the device substrate 10 and the support substrate 20 are single-crystal silicon substrates.

[0021] As shown in Figure 2B, referring to step S11, an oxide layer is formed on the surface of at least one of the device substrate 10 and the support substrate 20. The purpose of forming the oxide layer is for subsequent formation of the buried oxide layer of the SOI structure. In this specific embodiment, oxide layers are formed on the surfaces of both the device substrate 10 and the support substrate 20; specifically, oxide layer 11 is formed on the surface of the device substrate 10, and oxide layer 21 is formed on the surface of the support substrate 20. The method for forming the oxide layer can be epitaxy or thermal oxidation. In this specific embodiment, both the device substrate 10 and the support substrate 20 are single-crystal silicon substrates, therefore, thermal oxidation can be used to form the oxide layer. The thermal oxidation includes dry oxidation and wet oxidation.

[0022] As shown in Figure 2C, referring to step S12, bubbling ions are implanted into the device substrate 10. The implanted region 12 formed by the implanted bubbling ions is used for subsequent stripping operations. The bubbling ions are selected from one or a combination of H ions and He ions, and an appropriate energy and dose range is selected according to the implantation depth. A portion of the surface of the implanted region 12 is retained after stripping as the device layer of the final SOI substrate.

[0023] Referring to step S13, modified ions, specifically Ar ions, are implanted above the bubbling ion implantation region 12 of the device substrate 10. The area above the bubbling ion implantation region 12 of the device substrate 10 is used as the device layer for the final SOI substrate. Using Ar ions as modified ions helps reduce the size of the overhanging portion at the edge of the top device layer after the subsequent lift-off process. In this specific embodiment, the Ar ion implantation energy range is 50-150 keV, and the dose range is 1E14-1E16 cm⁻¹. -2 .

[0024] As shown in Figure 2D, referring to step S14, the device substrate 10 and the support substrate 20 are bonded. Bonding can employ any common bonding process, such as atmospheric pressure bonding or vacuum bonding. Before bonding, the bonding surfaces are treated using methods such as plasma activation to improve the bonding process quality. After bonding, high-temperature hardening processes can be implemented to enhance the bonding strength.

[0025] As shown in Figure 2E, referring to step S15, annealing is performed to peel off the device substrate 10 at the location where the bubbling ions were implanted, forming an SOI substrate. The SOI substrate formed after peeling includes the support substrate 20, an oxide buried layer 30 formed by the bonding of oxide layers 11 and 21 on the surface of the support substrate 20, and the device layer 40 retained after peeling. Since wafers have inwardly chamfered edges, the edge of the device layer 40 of the bonded SOI substrate is suspended, i.e., the dashed frame portion on the left and right sides of Figure 2E. This portion is an annular shape in the three-dimensional structure of the wafer. Figure 3 shows the annular shape of the suspended portion in a top view of the wafer. The suspended portion will affect subsequent processes and may cause the device layer 40 to chip or even break. In step S13, Ar ions are injected as modified ions into the device layer 40, which can increase the effective bonding area between the device substrate 10 and the support substrate 20, and relatively reduce the size of the suspended portion at the edge of the device layer 40, thereby reducing the risk of subsequent edge chipping and breakage.

[0026] Figure 4 shows the test results after adopting the scheme described in the above specific embodiment. Obviously, the size of the suspended part at the edge of the device layer 40 has been significantly reduced.

[0027] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for preparing an SOI substrate, wherein, include: Provide device substrate and support substrate; An oxide layer is formed on the surface of at least one of the device substrate and the support substrate; Bubbling ions are implanted into the substrate of the device. Modified ions, namely Ar ions, are implanted above the implantation region of the bubbling ions on the device substrate. Bond the device substrate and the support substrate together; Annealing is performed to peel off the device substrate at the site where the bubbling ions were implanted, forming an SOI substrate.

2. The method as described in claim 1, wherein, The energy range of the Ar ion implantation is 50-150 keV, and the dose range is 1E14-1E16 cm⁻¹. -2 .

3. The method as described in claim 1, wherein, The bubbling ions are selected from one or a combination of H ions and He ions.

4. The method of claim 1, wherein, The device substrate is a single-crystal silicon substrate.

5. The method of claim 1, wherein, The bonding process is followed by a high-temperature reinforcement process to enhance the bonding strength.

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