Integrated circuit device

Abstract

An integrated circuit device includes a fin-type active region on a substrate and including a fin top surface at a first level, a gate line on the fin-type active region, and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes a first insulating liner in contact with the sidewall of the fin-type active region, a second insulating liner on the first insulating liner and including an uppermost portion at a second level lower than the first level, a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level, and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0183522, filed on December 24, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to integrated circuit devices, and more specifically, to integrated circuit devices including field-effect transistors. Background Technology

[0004] Recently, with the rapid miniaturization of integrated circuit devices, it is beneficial to ensure not only fast operating speed but also accurate operation. Furthermore, as the integration density and size of integrated circuit devices increase, there is a need to develop new structures that can improve the performance and reliability of nanosheet field-effect transistors. Summary of the Invention

[0005] The present invention provides an integrated circuit device having a structure that can improve transistor performance and reduce power consumption by reducing the parasitic capacitance between adjacent conductive regions.

[0006] According to one aspect of the present invention, an integrated circuit device is provided, comprising: a fin-type active region extending in a first horizontal direction on a substrate and including a fin top surface at a first horizontal height; a gate line extending in a second horizontal direction intersecting the first horizontal direction on the fin-type active region; and an insulating structure located between the substrate and the gate line and on a sidewall of the fin-type active region, wherein the insulating structure includes: a first insulating pad contacting the sidewall of the fin-type active region; a second insulating pad located on the sidewall of the fin-type active region and including an uppermost portion at the second horizontal height, the first insulating pad being located between the second insulating pad and the fin-type active region. Between the sidewalls, the second horizontal height is closer to the bottom surface of the substrate than the first horizontal height; a lower buried insulating layer, the lower buried insulating layer being located on the sidewall of the fin active region and including a first top surface facing the gate line at a third horizontal height, the first insulating pad and the second insulating pad being located between the lower buried insulating layer and the sidewall of the fin active region, the third horizontal height being closer to the bottom surface of the substrate than the second horizontal height; and an upper buried insulating layer, the upper buried insulating layer being located between the lower buried insulating layer and the gate line, and including a second top surface located at a fourth horizontal height, the fourth horizontal height and the second horizontal height being at the same distance from the bottom surface of the substrate or the fourth horizontal height being farther from the bottom surface of the substrate than the second horizontal height.

[0007] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a substrate including a device region and an inter-device isolation region defining the device region; a fin active region extending in the device region in a first horizontal direction and including a fin top surface located at a first horizontal height; a nanosheet stack including at least one nanosheet located on the fin top surface and spaced apart from the fin top surface in a vertical direction, each nanosheet in the nanosheet stack having a different vertical distance from the fin top surface; a gate line located on the at least one nanosheet in the fin active region and extending in the device region and the inter-device isolation region in a second horizontal direction intersecting the first horizontal direction; a first insulating structure located in the device region between the substrate and the gate line, and located on a sidewall of the fin active region; and a second insulating structure located in the inter-device isolation region between the substrate and the gate line, wherein the first insulating structure includes: a first insulating pad, the first insulating pad... The first insulating pad contacts the sidewall of the finned active region; a second insulating pad is located on the sidewall of the finned active region and includes an uppermost portion at a second horizontal height, the first insulating pad being located between the second insulating pad and the sidewall of the finned active region, the second horizontal height being closer to the bottom surface of the substrate than the first horizontal height; a first lower buried insulating layer is located on the sidewall of the finned active region and includes a first top surface facing the gate line at a third horizontal height, the first insulating pad and the second insulating pad being located between the first lower buried insulating layer and the sidewall of the finned active region, the third horizontal height being closer to the bottom surface of the substrate than the second horizontal height; and a first upper buried insulating layer is located between the first lower buried insulating layer and the gate line and includes a second top surface at a fourth horizontal height, the fourth horizontal height and the second horizontal height being at the same distance from the bottom surface of the substrate or the fourth horizontal height being farther from the bottom surface of the substrate than the second horizontal height.

[0008] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a substrate including a first region and a second region spaced apart from each other, and further including a first device isolation trench disposed in the first region and a second device isolation trench disposed in the second region; a first fin active region defined in the first region by the first device isolation trench; at least one nanosheet located on a first fin top surface of the first fin active region and spaced apart from the first fin top surface in a vertical direction; a second fin active region defined in the second region by the second device isolation trench, and including a second fin top surface higher than the first fin top surface relative to a bottom surface of the substrate; a first insulating structure located on a sidewall of the first fin active region in the first region; and a second insulating structure located in the second region. Located on the sidewall of the second fin-type active region, each of the first and second insulating structures includes: a first insulating pad that contacts the substrate; a second insulating pad located on the first insulating pad and including an uppermost portion at a second horizontal height, the second horizontal height being lower than a first horizontal height relative to the bottom surface of the substrate and the top surface of the first fin; a lower buried insulating layer located on the second insulating pad and including a first top surface at a third horizontal height, the third horizontal height being lower than the bottom surface of the substrate and the second horizontal height; and an upper buried insulating layer located on the uppermost portion of the second insulating pad and the first top surface of the lower buried insulating layer, and including a second top surface at a fourth horizontal height, the fourth horizontal height being equal to or higher than the second horizontal height relative to the bottom surface of the substrate. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a plan view of some components of an integrated circuit device according to an embodiment of the present invention.

[0011] Figure 2A It shows along Figure 1 A cross-sectional view of the partial structure of the cross section intercepted by line X1-X1'. Figure 2B It shows along Figure 1 A cross-sectional view of the partial structure of the cross section intercepted by line X2-X2'. Figure 2C It shows along Figure 1A cross-sectional view of the partial structure of the cross section intercepted by line Y1-Y1', and Figure 2D yes Figure 2C An enlarged cross-sectional view of some components included in the area designated as "EQ" in the middle;

[0012] Figure 3 This is a cross-sectional view illustrating an integrated circuit device according to an embodiment of the concept of the present invention;

[0013] Figure 4 This is a cross-sectional view illustrating an integrated circuit device according to an embodiment of the concept of the present invention;

[0014] Figure 5 This is a cross-sectional view illustrating an integrated circuit device according to an embodiment of the concept of the present invention;

[0015] Figure 6 This is a cross-sectional view illustrating an integrated circuit device according to an embodiment of the concept of the present invention;

[0016] Figure 7 This is a cross-sectional view illustrating an integrated circuit device according to an embodiment of the concept of the present invention;

[0017] Figure 8 This is a block diagram of an integrated circuit device according to an embodiment of the present invention.

[0018] Figure 9 It is shown Figure 8 A plan view of the partial structure of the second region of the integrated circuit device shown;

[0019] Figure 10 It shows along Figure 9 A cross-sectional view of the partial structure of the cross section intercepted by line Y4-Y4'; and

[0020] Figures 11A to 20D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention, wherein, Figure 11A , Figure 12A ,……,and Figure 20A It is shown along Figure 1 A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line X1-X1'. Figure 11B , Figure 12B ,……,and Figure 20B It is shown along Figure 1 A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line X2-X2'. Figure 11C , Figure 12C ,……,and Figure 20C It is shown along Figure 1A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line Y1-Y1', and Figure 11D , Figure 12D ,……,and Figure 20D It is shown along Figure 9 A cross-sectional view of the local structure corresponding to the cross section intercepted by line Y4-Y4'. Detailed Implementation

[0021] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements, and redundant descriptions of them are omitted.

[0022] Figure 1 This is a planar layout diagram of some components of an integrated circuit device according to an embodiment of the present invention. Figure 2A It shows along Figure 1 A cross-sectional view of the partial structure of the cross section intercepted by line X1-X1'. Figure 2B It shows along Figure 1 A cross-sectional view of the partial structure of the cross section intercepted by line X2-X2'. Figure 2C It shows along Figure 1 A cross-sectional view of the partial structure of the cross section intercepted by line Y1-Y1', and Figure 2D Is included Figure 2C An enlarged cross-sectional view of some components in the area designated as "EQ".

[0023] refer to Figure 1 and Figures 2A to 2D The integrated circuit device 100 may include a substrate 102, which includes a first device region RX1 and a second device region RX2, and an inter-device isolation region DTA located therebetween. A deep trench DTR may be formed in the inter-device isolation region DTA in the substrate 102. The first device region RX1 and the second device region RX2 may be defined by the deep trench DTR.

[0024] Substrate 102 may include semiconductors such as Si or Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. As used herein, the terms “SiGe,” “SiC,” “GaAs,” “InAs,” “InGaAs,” and “InP” refer to materials including the elements contained in the respective terms, rather than equations expressing stoichiometric relationships. Substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0025] In the first device region RX1 and the second device region RX2, a plurality of fin-type active regions F1 and F2 may protrude from the substrate 102 in a vertical direction (e.g., the Z direction). The plurality of fin-type active regions F1 and F2 may extend parallel to each other in a first horizontal direction (e.g., the X direction). The plurality of fin-type active regions F1 and F2 may be defined by device isolation trenches STR formed in the substrate 102 in the first device region RX1 and the second device region RX2, respectively.

[0026] The plurality of finned active regions F1 and F2 may include a plurality of first finned active regions F1 disposed in a first device region RX1 and a plurality of second finned active regions F2 disposed in a second device region RX2. Each of the plurality of finned active regions F1 and F2 may have a fin top surface FT with a first horizontal height LV1. The term “horizontal height” as used herein refers to the height from the bottom surface of the substrate 102 in the vertical direction (e.g., the Z direction or the -Z direction). Figure 1 The diagram shows two first finned active regions F1 disposed in the first device region RX1 and two second finned active regions F2 disposed in the second device region RX2, but one or three or more finned active regions F1 and F2 may be disposed in the first device region RX1 and the second device region RX2 respectively.

[0027] On the multiple finned active regions F1 and F2, the gate line 160 extends longitudinally in a second horizontal direction (e.g., the Y direction) that intersects the first horizontal direction (X direction). Figure 1 A configuration is shown in which a gate line 160 is disposed on a plurality of finned active regions F1 and F2, but the number of gate lines 160 on the plurality of finned active regions F1 and F2 is not limited thereto. For example, a plurality of gate lines 160 may be disposed on each of the plurality of finned active regions F1 and F2.

[0028] The first insulating structure ST1 can fill the device isolation trench STR in the first device region RX1 and the second device region RX2. The first insulating structure ST1 can be disposed between the substrate 102 and the gate line 160, and can cover the sidewalls of each of the plurality of fin active regions F1 and F2.

[0029] The first insulating structure ST1 may include a first insulating pad 112A, a second insulating pad 112B, a first lower buried insulating layer 112C, a first upper insulating pad 114S, and a first upper buried insulating layer 116S, which are sequentially stacked on the substrate 102.

[0030] The first insulating pad 112A may contact the sidewall of each of the plurality of finned active regions F1 and F2. The uppermost portion of the first insulating pad 112A may be equal to or lower than (e.g., closer to the substrate 102) a first horizontal height LV1 of the fin top surface FT. The second insulating pad 112B may be located on and / or facing the sidewall of each of the plurality of finned active regions F1 and F2, with the first insulating pad 112A located between the second insulating pad 112B and the sidewall of each of the plurality of finned active regions F1 and F2. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The second insulating pad 112B may have an uppermost portion of a second horizontal height LV2 that is lower than the first horizontal height LV1 (e.g., closer to the substrate 102).

[0031] A first lower buried insulating layer 112C may be located on and / or facing the sidewalls of each of the plurality of finned active regions F1 and F2, with a first insulating pad 112A and a second insulating pad 112B located between the first lower buried insulating layer 112C and the sidewalls of each of the plurality of finned active regions F1 and F2. The top surface of the first lower buried insulating layer 112C facing the gate line 160 may extend non-linearly in a second horizontal direction (e.g., the Y direction) at a level below the second horizontal height LV2. The top surface of the first lower buried insulating layer 112C facing the gate line 160 may have a recessed shape toward the gate line 160. The lowermost portion of the top surface of the first lower buried insulating layer 112C may be located at a third horizontal height LV3 below the second horizontal height LV2.

[0032] A first height H1 can be greater than zero. This first height is the distance in the vertical direction (e.g., the Z-direction) from the fin-top surface FT of each of the plurality of fin-type active regions F1 and F2 to a second horizontal height LV2, which is the horizontal height of the uppermost part of the second insulating liner 112B. A second height H2 can be greater than the first height H1. This second height is the distance in the vertical direction (e.g., the Z-direction) from the fin-top surface FT of each of the plurality of fin-type active regions F1 and F2 to a third horizontal height LV3, which is the horizontal height of the lowermost part of the top surface of the first lower buried insulating layer 112C.

[0033] The first upper insulating pad 114S may be located between the second insulating pad 112B and the first upper buried insulating layer 116S, and between the first lower buried insulating layer 112C and the first upper buried insulating layer 116S. The first upper insulating pad 114S may include a portion that contacts the uppermost part of the second insulating pad 112B and a portion that contacts the top surface of the first lower buried insulating layer 112C.

[0034] The first upper buried insulating layer 116S may be located between the first lower buried insulating layer 112C and the gate line 160. The first upper insulating pad 114S may be located between the top surface of the first lower buried insulating layer 112C and the bottom surface of the first upper buried insulating layer 116S.

[0035] The top surface of the first upper buried insulating layer 116S may extend flat in the horizontal direction (e.g., in the X and Y directions) at a fourth horizontal height LV4, which is higher than the second horizontal height LV2 (e.g., farther from the substrate 102). The bottom surface of the first upper buried insulating layer 116S may face the top surface of the first lower buried insulating layer 112C (with the first upper insulating pad 114S located therebetween) and has a convex shape facing the substrate 102 corresponding to the concave shape of the top surface of the first lower buried insulating layer 112C.

[0036] The third height H3 can be greater than or equal to zero. This third height H3 is the distance in the vertical direction (e.g., the Z-direction) from the fin top surface FT of each of the plurality of fin-type active regions F1 and F2 to a fourth horizontal height LV4, which is the horizontal height of the top surface of the first upper buried insulating layer 116S. In some embodiments, the third height H3 can be equal to or less than the first height H1. That is, the horizontal height of the top surface of the first upper buried insulating layer 116S can be equal to or higher than the horizontal height of the uppermost part of the second insulating pad 112B.

[0037] In some embodiments, the first insulating pad 112A and the second insulating pad 112B may comprise different materials. For example, the first insulating pad 112A may comprise a silicon oxide layer, and the second insulating pad 112B may comprise a silicon nitride layer.

[0038] In some embodiments, each of the first lower buried insulating layer 112C and the first upper insulating liner 114S may comprise a silicon oxide layer. The first upper buried insulating layer 116S may comprise a silicon oxide layer containing at least one impurity element selected from nitrogen (N) atoms and / or fluorine (F) atoms. Expressions such as "at least one" used before the list of elements modify the entire list of elements, not a single element in the list. In some embodiments, the density of the silicon oxide layer constituting the first lower buried insulating layer 112C may be lower than the density of each of the first upper insulating liner 114S and the first upper buried insulating layer 116S.

[0039] The second insulating structure ST2 can be disposed between the substrate 102 and the gate line 160 in the inter-device isolation region DTA. The second insulating structure ST2 can be filled in the deep trench DTR. The second insulating structure ST2 can be spaced apart from the plurality of fin active regions F1 and F2 in a second horizontal direction (e.g., the Y direction).

[0040] The second insulating structure ST2 may include a second lower buried insulating layer 113, a second upper insulating pad 114D, and a second upper buried insulating layer 116D sequentially stacked on the substrate 102.

[0041] At least a portion of the top surface of the second lower buried insulation layer 113 may be at a higher horizontal level than the top surface of the first lower buried insulation layer 112C. The top surface of the first lower buried insulation layer 112C may have an uppermost portion at a fifth horizontal level LV5, which is higher than the third horizontal level LV3.

[0042] The second upper buried insulating layer 116D may be located between the second lower buried insulating layer 113 and the gate line 160. The second upper insulating pad 114D may be located between the top surface of the second lower buried insulating layer 113 and the bottom surface of the second upper buried insulating layer 116D.

[0043] The second upper buried insulation layer 116D may have a top surface that extends flat in the horizontal direction (e.g., the X and Y directions) at a sixth horizontal height LV6, which is higher than the fourth horizontal height LV4, and the fourth horizontal height LV4 is the horizontal height of the top surface of the first upper buried insulation layer 116S.

[0044] The top surface of the second lower buried insulating layer 113 may have a protruding shape toward the gate line 160. The bottom surface of the second upper buried insulating layer 116D may face the top surface of the second lower buried insulating layer 113 (with the second upper insulating pad 114D located therebetween), and has a recessed shape toward the substrate 102 corresponding to the protruding shape of the top surface of the second lower buried insulating layer 113.

[0045] Each of the second lower buried insulating layer 113 and the second upper insulating pad 114D may include a silicon oxide layer. In some embodiments, the density of the silicon oxide layer constituting each of the second lower buried insulating layer 113 and the second upper insulating pad 114D may be higher than the density of the silicon oxide layer constituting the first lower buried insulating layer 112C. The second upper buried insulating layer 116D may include a silicon oxide layer containing at least one impurity element selected from nitrogen (N) atoms and fluorine (F) atoms. In some embodiments, the first upper insulating pad 114S and the second upper insulating pad 114D may include the same material, and the first upper buried insulating layer 116S and the second upper buried insulating layer 116D may include the same material. In some embodiments, the content of the impurity element in each of the first upper buried insulating layer 116S and the second upper buried insulating layer 116D may be from about 0.1 atomic% to about 20 atomic%, but is not limited thereto.

[0046] Gate line 160 may extend in a second horizontal direction (e.g., Y direction) over multiple fin active regions F1 and F2, a first insulating structure ST1, and a second insulating structure ST2. In regions where the multiple fin active regions F1 and F2 intersect with gate line 160, multiple nanosheet stacks NSS may be disposed on the fin top surface FT of each of the multiple fin active regions F1 and F2. The multiple nanosheet stacks NSS may face the fin top surface FT at locations spaced apart from the multiple fin active regions F1 and F2 in a vertical direction (e.g., Z direction).

[0047] A stack of multiple nanosheets (NSS) may comprise multiple nanosheets N1, N2, and N3 overlapping each other in a vertical direction (e.g., the Z-direction) on the fin top surfaces FT of each fin-type active region F1 and F2. As used herein, the term "nanosheet" refers to a conductive structure whose cross-section is substantially perpendicular to the direction of current flow within the conductive structure. It should be understood that nanosheets may comprise nanowires. The multiple nanosheets N1, N2, and N3 may have different vertical distances (e.g., Z-direction distances) from the fin top surfaces FT. The multiple nanosheets N1, N2, and N3 may comprise a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 sequentially stacked on the fin top surfaces FT of the fin-type active regions F1 and F2.

[0048] The number of nanosheet stacks NSS and gate lines 160 disposed on a fin-type active region F1 or F2 is not limited to the number shown in the figure. For example, one or more nanosheet stacks NSS and one or more gate lines 160 may be disposed on a fin-type active region F1 or F2.

[0049] Figures 2A to 2D The illustration shows a scenario where each of a plurality of nanosheet stacked NSSs comprises three nanosheets N1, N2, and N3, but embodiments of the inventive concept are not limited thereto. The number of nanosheets constituting the nanosheet stacked NSS is not particularly limited. For example, each of the plurality of nanosheet stacked NSSs may comprise one, two, four, or more nanosheets. Each of the plurality of nanosheets N1, N2, and N3 may have a channel region. For example, each of the plurality of nanosheets N1, N2, and N3 may have a thickness selected in the range of about 4 nm to about 6 nm, but is not limited thereto. Here, the thickness of the plurality of nanosheets N1, N2, and N3 means the dimension along the vertical direction (e.g., the Z direction). In some embodiments, the plurality of nanosheets N1, N2, and N3 may have substantially the same thickness in the vertical direction (e.g., the Z direction). In some embodiments, at least some of the plurality of nanosheets N1, N2, and N3 may have different thicknesses along the vertical direction (e.g., the Z direction).

[0050] like Figure 2A and Figure 2BAs shown, each of the plurality of nanosheets N1, N2, and N3 included in a nanosheet stack NSS can have the same size in a first horizontal direction (e.g., the X direction). In some embodiments, at least some of the nanosheets N1, N2, and N3 included in a nanosheet stack NSS can have different sizes in the first horizontal direction (e.g., the X direction). For example, among the plurality of nanosheets N1, N2, and N3 in the first horizontal direction (e.g., the X direction), the length of each of the first nanosheet N1 and the second nanosheet N2 that is relatively close to the fin tip surface FT can be less than the length of the third nanosheet N3 that is furthest from the fin tip surface FT.

[0051] like Figure 2A As shown, multiple first recesses R1 can be formed in the top surface of the first fin-shaped active region F1 in the first device region RX1, and as... Figure 2B As shown, multiple second recesses R2 can be formed in the top surface of the second fin-shaped active region F2 in the second device region RX2. Figure 2A and Figure 2B The illustration shows a case where the lowest surface of each of the plurality of first recesses R1 and the plurality of second recesses R2 is at a lower level than the fin tip surface FT of the plurality of fin active regions F1 and F2; however, embodiments of the present invention are not limited thereto. The lowest surface of each of the plurality of first recesses R1 and the plurality of second recesses R2 may be the same as or similar to the fin tip surface FT of the plurality of fin active regions F1 and F2.

[0052] like Figure 2A and Figure 2B As shown, multiple first source / drain regions SD1 can be formed on multiple first recesses R1 in the first device region RX1, and multiple second source / drain regions SD2 can be formed on multiple second recesses R2 in the second device region RX2.

[0053] Gate line 160 can surround each of the plurality of nanosheets N1, N2, and N3 while covering the plurality of nanosheet stacked NSSs on the plurality of fin active regions F1 and F2. A plurality of transistors can be formed on the portions of the plurality of fin active regions F1 and F2 of substrate 102 where they intersect with gate line 160. In some embodiments, the first device region RX1 can be an NMOS transistor region, and the second device region RX2 can be a PMOS transistor region. A plurality of NMOS transistors TR1 can be formed in the portions of the first fin active region F1 of the first device region RX1 where it intersects with gate line 160, and a plurality of PMOS transistors TR2 can be formed in the portions of the second device region RX2 where it intersects with active region F2 of ...

[0054] Gate line 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the top surface of the nanosheet stack NSS and extend longitudinally in a second horizontal direction (e.g., the Y direction) (e.g., having a longitudinal axis extending in the second horizontal direction (e.g., the Y direction)). The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M and disposed between the plurality of nanosheets N1, N2 and N3, and between the fin active regions F1 and F2 and the first nanosheet N1.

[0055] Gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. The metal nitride may be selected from TiN and / or TaN. The metal carbide may be TiAlC. In some embodiments, gate line 160 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and / or Hf. The gap-filling metal layer may include a W layer and / or an Al layer. Multiple gate lines 160 may include at least one layer of a metal with a work function. The at least one layer of a metal with a work function may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. In some embodiments, the gate line 160 may have a TiAlC / TiN / W stacked structure, a TiN / TaN / TiAlC / TiN / W stacked structure, or a TiN / TaN / TiN / TiAlC / TiN / W stacked structure, but is not limited to the examples described above. In some embodiments, the gate line 160 may have different stacked structures in the first device region RX1 and the second device region RX2.

[0056] The gate dielectric layer 152 may be located between the plurality of nanosheets N1, N2 and N3 and the gate line 160. The gate dielectric layer 152 may include portions covering the surfaces of the plurality of nanosheets N1, N2 and N3 respectively, portions covering the sidewalls of the main gate portion 160M, portions covering the top surfaces FT of the plurality of fin active regions F1 and F2 respectively, portions covering the top surface of the first insulating structure ST1, and portions covering the top surface of the second insulating structure ST2.

[0057] In some embodiments, the gate dielectric layer 152 may include a material different from the material of each of the first upper insulating pad 114S, the second upper insulating pad 114D, the first upper buried insulating layer 116S, and the second upper buried insulating layer 116D. For example, the gate dielectric layer 152 may include a high dielectric layer. The high dielectric layer may include a material with a dielectric constant higher than that of the silicon oxide layer. For example, the high dielectric layer may have a dielectric constant of about 10 to about 25. The high dielectric layer may include, but is not limited to, hafnium oxide.

[0058] Multiple nanosheets N1, N2, and N3 may comprise semiconductor layers of the same element. In the example, each of the multiple nanosheets N1, N2, and N3 may comprise a Si layer. In the first device region RX1, the multiple nanosheets N1, N2, and N3 may be doped with dopants of the same conductivity type as the first source / drain region SD1. In the second device region RX2, the multiple nanosheets N1, N2, and N3 may be doped with dopants of the same conductivity type as the second source / drain region SD2. For example, the multiple nanosheets N1, N2, and N3 in the first device region RX1 may comprise a Si layer doped with an n-type dopant, and the multiple nanosheets N1, N2, and N3 in the second device region RX2 may comprise a Si layer doped with a p-type dopant.

[0059] In each of the multiple finned active regions F1 and F2, the first insulating structure ST1, and the second insulating structure ST2, the two sidewalls of the gate line 160 may be covered by multiple external insulating spacers 118 (see [link]). Figure 2A and Figure 2B Multiple external insulating spacers 118 may cover the two sidewalls of the main gate portion 160M on the top surface of the multiple nanosheet stacked NSS. Each of the multiple external insulating spacers 118 may be spaced apart from the gate line 160, with the gate dielectric layer 152 located therebetween. The multiple external insulating spacers 118 may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. As used herein, the terms “SiCN,” “SiBN,” “SiON,” “SiOCN,” “SiBCN,” and “SiOC” refer to materials including the elements contained in the respective terms, rather than equations representing stoichiometric relationships.

[0060] like Figure 2A As shown, multiple internal insulating spacers 120 may be located between multiple nanosheets N1, N2, and N3 in the first device region RX1, and between the fin top surface FT of the first fin active region F1 and the first nanosheet N1. The multiple internal insulating spacers 120 may also be located between multiple sub-gate portions 160S and the first source / drain region SD1 in a first horizontal direction (e.g., the X direction).

[0061] In a first horizontal direction (e.g., the X direction), the two sidewalls of each of the plurality of sub-gate portions 160S in the first device region RX1 may be covered by inner insulating spacers 120, with the gate dielectric layer 152 located therebetween. Each of the plurality of sub-gate portions 160S in the first device region RX1 may be spaced apart from the first source / drain region SD1, with the gate dielectric layer 152 and the inner insulating spacers 120 located therebetween. Each of the plurality of inner insulating spacers 120 may contact the first source / drain region SD1. At least some of the plurality of inner insulating spacers 120 may overlap with the outer insulating spacer 118 in a vertical direction (e.g., the Z direction). The inner insulating spacer 120 may comprise silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. The inner insulating spacer 120 may also include an air gap. In some embodiments, the inner insulating spacer 120 and the outer insulating spacer 118 may comprise the same material. In some embodiments, the outer insulating spacer 118 and the inner insulating spacer 120 may comprise different materials.

[0062] In a first horizontal direction (e.g., the X direction), a plurality of first source / drain regions SD1 in the first device region RX1 may each face a plurality of sub-gate portions 160S, with an inner insulating spacer 120 located therebetween. The plurality of first source / drain regions SD1 may not include portions that contact the gate dielectric layer 152.

[0063] like Figure 2B As shown, each of the plurality of sub-gate portions 160S in the second device region RX2 may have two sidewalls spaced apart from the second source / drain region SD2 in a first horizontal direction (e.g., the X direction), with the gate dielectric layer 152 located therebetween. In the second device region RX2, the gate dielectric layer 152 may include portions that contact the second source / drain region SD2. In the first horizontal direction (e.g., the X direction), the plurality of second source / drain regions SD2 may respectively face the nanosheet stack NSS and the plurality of sub-gate portions 160S.

[0064] like Figures 2A to 2C As shown, the gate line 160 and the gate dielectric layer 152 can be covered by an insulating pattern 164. The insulating pattern 164 may include a silicon nitride layer.

[0065] In the first device region RX1, the main gate portion 160M of the gate line 160 can be spaced apart from the first source / drain region SD1, with an external insulating spacer 118 located therebetween. In the second device region RX2, the main gate portion 160M of the gate line 160 can be spaced apart from the second source / drain region SD2, with an external insulating spacer 118 located therebetween.

[0066] When the first device region RX1 is an NMOS transistor region and the second device region RX2 is a PMOS transistor region, the plurality of first source / drain regions SD1 in the first device region RX1 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant, and the plurality of second source / drain regions SD2 in the second device region RX2 may include a SiGe layer doped with a p-type dopant. The n-type dopant may be selected from P (phosphorus), As (arsenic), and Sb (antimony). The p-type dopant may be selected from B (boron) and Ga (gallium).

[0067] The plurality of first source / drain regions SD1 in the first device region RX1 and the plurality of second source / drain regions SD2 in the second device region RX2 can have different shapes and sizes. However, embodiments of the present invention are not limited thereto, and the plurality of first source / drain regions SD1 and the plurality of second source / drain regions SD2 having various shapes and sizes can be formed in the first device region RX1 and the second device region RX2.

[0068] like Figure 2A and Figure 2B As shown, multiple first source / drain regions SD1 and multiple second source / drain regions SD2 can be covered by an insulating pad 142. The insulating pad 142 can conformally cover the surfaces of the multiple first source / drain regions SD1 and multiple second source / drain regions SD2, as well as the outer insulating spacer 118. The insulating pad 142 may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or combinations thereof.

[0069] In the first device region RX1 and the second device region RX2, the first source / drain region SD1 and the second source / drain region SD2 can be covered by the inter-gate insulating layer 144. An insulating pad 142 can be located between the inter-gate insulating layer 144 and the first source / drain region SD1 and the second source / drain region SD2. The inter-gate insulating layer 144 can be formed of a silicon nitride layer, a silicon oxide layer, SiON, SiOCN, or a combination thereof. The inter-gate insulating layer 144 between the plurality of covering insulating patterns 164 can be covered by an interlayer insulating layer 190. The interlayer insulating layer 190 can include an etch stop layer 190A and an insulating layer 190B. The etch stop layer 190A can include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The insulating layer 190B may include an oxide layer, a nitride layer, an ultra-low K (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, the insulating layer 190B may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or combinations thereof.

[0070] like Figure 2A and Figure 2B As shown, multiple source / drain contacts 174 and multiple source / drain path contacts 192 can be formed on multiple first source / drain regions SD1 and multiple second source / drain regions SD2 in the first device region RX1 and the second device region RX2. The multiple first source / drain regions SD1 and multiple second source / drain regions SD2 can be connected to the upper conductor (not shown) through the multiple source / drain contacts 174 and multiple source / drain path contacts 192.

[0071] A metal silicide layer 172 may be formed between the first source / drain region SD1 and the second source / drain region SD2 and the source / drain contact 174. In some embodiments, the metal silicide layer 172 may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. For example, the metal silicide layer 172 may include titanium silicide.

[0072] Multiple source / drain contacts 174 may penetrate the inter-gate insulating layer 144 and the insulating pad 142 in a vertical direction (e.g., the Z direction) to contact the metal silicide layer 172. Multiple source / drain path contacts 192 may penetrate the interlayer insulating layer 190 in a vertical direction (e.g., the Z direction) to contact the top surface of the source / drain contacts 174. The multiple source / drain contacts 174 may include a conductive barrier layer 174A and a metal plug 174B. The multiple source / drain path contacts 192 may include a conductive barrier layer 192A and a metal plug 192B.

[0073] like Figure 2C As shown, gate contact 184 and gate path contact 194 can be formed on gate line 160. Gate line 160 can be connected to an upper conductive line (not shown) through gate contact 184 and gate path contact 194. Gate contact 184 may include a conductive barrier layer 184A and a metal plug 184B. Gate path contact 194 may include a conductive barrier layer 194A and a metal plug 194B.

[0074] The conductive barrier layers 174A, 184A, 192A and 194A may comprise Ti, Ta, TiN, TaN or combinations thereof, and the metal plugs 174B, 184B, 192B and 194B may comprise W, Co, Cu, Ru, Mn or combinations thereof, but the inventive concept is not limited thereto.

[0075] Gate contact 184 and gate path contact 194 may be disposed in the inter-device isolation region DTA and configured to connect to the main gate portion 160M of gate line 160. However, embodiments of the present invention are not limited thereto. For example, gate contact 184 and gate path contact 194 may be disposed in at least one of the first device region RX1 and the second device region RX2 and may be configured to connect to the main gate portion 160M.

[0076] Gate contact 184 may penetrate the overlay insulating pattern 164 in the vertical direction (e.g., the Z direction) to contact the top surface of gate line 160. Gate via contact 194 may penetrate the interlayer insulating layer 190 in the vertical direction (e.g., the Z direction) to contact the top surface of gate contact 184.

[0077] In some embodiments, the sidewalls of each of the plurality of source / drain contacts 174, the plurality of source / drain path contacts 192, the gate contact 184, and the gate path contact 194 may be surrounded by a contact insulating spacer (not shown). The contact insulating spacer may include, but is not limited to, SiCN, SiCON, silicon nitride (SiN), or combinations thereof.

[0078] Figure 1 and Figures 2A to 2DThe integrated circuit device 100 shown may include a first insulating structure ST1 that fills the device isolation trench STR in each of the first device region RX1 and the second device region RX2, and covers the sidewalls of each of the plurality of fin active regions F1 and F2. The first insulating structure ST1 may include a first upper insulating pad 114S and a first upper buried insulating layer 116S covering the top surface of the first lower buried insulating layer 112C. The horizontal height of the top surface of the first upper buried insulating layer 116S may be equal to or higher than the uppermost horizontal height of the second insulating pad 112B. Therefore, even in the manufacturing process of the integrated circuit device 100, when the horizontal height of the top surface of the first lower buried insulating layer 112C is lower than the uppermost horizontal height of the second insulating pad 112B, the space on the top surface of the first lower buried insulating layer 112C that is lower than the uppermost horizontal height of the second insulating pad 112B can be filled by the first upper insulating pad 114S and the first upper buried insulating layer 116S. Therefore, sufficient insulation space can be ensured between the fin active regions F1 and F2 and the gate line 160 through the first insulating structure ST1, and thus the parasitic capacitance generated by the coupling between the fin active regions F1 and F2 and the gate line 160 can be reduced. Consequently, the on-current and off-current characteristics of each of the plurality of transistors formed in the first device region RX1 and the second device region RX2 can be improved, which can help improve transistor performance and reliability.

[0079] Figure 3 This is a cross-sectional view showing an integrated circuit device 100A according to an embodiment of the present invention. Figure 3 It shows the corresponding to in Figure 2C The local structure of the region indicated as "EQ".

[0080] refer to Figure 3 Integrated circuit device 100A can have the same characteristics as the reference. Figure 1 and Figures 2A to 2D The integrated circuit device 100A described has a substantially the same construction. However, the integrated circuit device 100A may include a first insulating structure ST1A and a second insulating structure ST2A, instead of a first insulating structure ST1 and a second insulating structure ST2.

[0081] The first insulating structure ST1A can have the same characteristics as the reference. Figure 2C and Figure 2DThe first insulating structure ST1 has a substantially the same construction as described. However, the first insulating structure ST1A may include a first upper buried insulating layer 116SA instead of a first upper buried insulating layer 116S. The first upper buried insulating layer 116SA may include a first silicon oxide layer S1 and a second silicon oxide layer S2 sequentially stacked on a first upper insulating pad 114S. The second silicon oxide layer S2 may be located between the first silicon oxide layer S1 and the gate line 160. The first silicon oxide layer S1 may include at least one impurity element selected from nitrogen (N) atoms and fluorine (F) atoms, and the second silicon oxide layer S2 may not include any impurity elements.

[0082] The second insulation structure ST2A can have the same characteristics as the reference. Figure 2C and Figure 2D The second insulating structure ST2 has a substantially the same construction as described. However, the second insulating structure ST2A may include a second upper buried insulating layer 116DA instead of a second upper buried insulating layer 116D. The second upper buried insulating layer 116DA may include a first silicon oxide layer D1 and a second silicon oxide layer D2 sequentially stacked on a second upper insulating pad 114D. The second silicon oxide layer D2 may be located between the first silicon oxide layer D1 and the gate line 160. The first silicon oxide layer D1 may include at least one impurity element selected from nitrogen (N) atoms and fluorine (F) atoms, and the second silicon oxide layer D2 may not include any impurity elements.

[0083] The uppermost second silicon oxide layers S2 and D2, which constitute the first insulating structure ST1A and the second insulating structure ST2A respectively, have a denser structure than the first silicon oxide layers S1 and D1, which contain impurity elements. Therefore, during the manufacturing process of the integrated circuit device 100A, after the formation of the first insulating structure ST1A and the second insulating structure ST2A, when the first insulating structure ST1A and the second insulating structure ST2A are exposed to a cleaning or etching atmosphere for subsequent processes, the relatively dense structure of the first silicon oxide layers S1 and D1 can prevent the first insulating structure ST1A and the second insulating structure ST2A from being consumed or damaged in the cleaning or etching atmosphere.

[0084] Figure 4 This is a cross-sectional view showing an integrated circuit device 200 according to an embodiment of the present invention. Figure 4 It shows the corresponding to in Figure 2C The local structure of the region indicated as "EQ".

[0085] refer to Figure 4 The integrated circuit device 200 may have the same characteristics as the reference. Figure 1 and Figures 2A to 2DThe integrated circuit device 100 described has a substantially the same construction. However, the integrated circuit device 200 may include a first insulating structure ST21 and a second insulating structure ST22, instead of a first insulating structure ST1 and a second insulating structure ST2.

[0086] The first insulating structure ST21 can have the same as the reference. Figure 2C and Figure 2D The first insulating structure ST1 has a substantially the same construction as described. However, the first insulating structure ST21 may include a first upper buried insulating layer 216S instead of a first upper buried insulating layer 116S. The top surface of the first upper buried insulating layer 216S may have a protruding shape toward the gate line 160. The horizontal height of the lowest part of the top surface of the first upper buried insulating layer 216S may be equal to or higher than the second horizontal height LV2. The horizontal height LV24 of the uppermost part of the top surface of the first upper buried insulating layer 216S may be higher than the second horizontal height LV2.

[0087] The third height H23 can be equal to or greater than zero. The third height H23 is the distance in the vertical direction (e.g., the Z direction) from the top surface of the fin FT to the uppermost horizontal height LV24 of the top surface of the first upper buried insulating layer 216S. In some embodiments, the third height H23 can be equal to or less than the first height H1.

[0088] The second insulation structure ST22 can have the same characteristics as the reference. Figure 2C and Figure 2D The second insulating structure ST2 has a substantially the same construction as described. However, the second insulating structure ST22 may include a second upper buried insulating layer 216D instead of a second upper buried insulating layer 116D. The second upper buried insulating layer 216D may have a top surface with a convex shape toward the gate line 160. The uppermost horizontal height LV26 of the top surface of the second upper buried insulating layer 216D may be higher than the uppermost horizontal height LV24 of the top surface of the first upper buried insulating layer 216S.

[0089] Figure 5 This is a cross-sectional view showing an integrated circuit device 200A according to an embodiment of the present invention. Figure 5 It shows the corresponding to in Figure 2C The local structure of the region indicated as "EQ".

[0090] refer to Figure 5 The integrated circuit device 200A can have the same characteristics as the reference. Figure 4 The integrated circuit device 200A described has a substantially the same construction. However, the integrated circuit device 200A may include a first insulating structure ST21A and a second insulating structure ST22A, instead of a first insulating structure ST21 and a second insulating structure ST22.

[0091] The first insulation structure ST21A can have the same as the reference. Figure 4 The first insulating structure ST21A has a substantially the same construction as described. However, the first insulating structure ST21A may include a first upper buried insulating layer 216SA instead of a first upper buried insulating layer 216S. The first upper buried insulating layer 216SA may include a first silicon oxide layer S1 and a second silicon oxide layer S2 sequentially stacked on the first upper insulating pad 114S. The second insulating structure ST22A may have the same construction as the referenced... Figure 4 The second insulating structure ST22 has a substantially the same construction as described. However, the second insulating structure ST22A may include a second upper buried insulating layer 216DA instead of a second upper buried insulating layer 216D. The second upper buried insulating layer 216DA may include a first silicon oxide layer D1 and a second silicon oxide layer D2 sequentially stacked on the second upper insulating pad 114D. A more detailed description of the construction and effects of the first silicon oxide layers S1 and D1 and the second silicon oxide layers S2 and D2 is available in the reference. Figure 3 The descriptions are the same.

[0092] Figure 6 This is a cross-sectional view showing an integrated circuit device 300 according to an embodiment of the present invention. Figure 6 It shows the corresponding to in Figure 2C The local structure of the region indicated as "EQ".

[0093] refer to Figure 6 The integrated circuit device 300 can have the same characteristics as the reference. Figure 1 and Figures 2A to 2D The integrated circuit device 100 described has a substantially the same construction. However, the integrated circuit device 300 may include a first insulating structure ST31 and a second insulating structure ST32, instead of a first insulating structure ST1 and a second insulating structure ST2.

[0094] The first insulation structure ST31 can have the same as the reference. Figure 2C and Figure 2D The first insulating structure ST1 has a substantially the same construction as described. However, the first insulating structure ST31 may include a first upper buried insulating layer 316S instead of a first upper buried insulating layer 116S. The top surface of the first upper buried insulating layer 316S may have a recessed shape toward the gate line 160. The horizontal height of the top surface of the first upper buried insulating layer 316S may be equal to or higher than a second horizontal height LV2. In particular, the horizontal height LV34 of the lowest part of the top surface of the first upper buried insulating layer 316S may be equal to or higher than the second horizontal height LV2.

[0095] The third height H33 can be equal to or greater than zero. The third height H33 is the distance in the vertical direction (e.g., the Z direction) from the top surface of the fin FT to the lowest horizontal height LV34 of the top surface of the first upper buried insulating layer 316S. In some embodiments, the third height H33 can be equal to or less than the first height H1.

[0096] The second insulation structure ST32 can have the same characteristics as the reference. Figure 2C and Figure 2D The second insulating structure ST2 has a substantially the same construction as described. However, the second insulating structure ST32 may include a second upper buried insulating layer 316D instead of a second upper buried insulating layer 116D. The second upper buried insulating layer 316D may have a top surface with a recessed shape facing the gate line 160. The horizontal height LV36 of the lowest point of the top surface of the second upper buried insulating layer 316D may be higher than the horizontal height LV34 of the lowest point of the top surface of the first upper buried insulating layer 316S.

[0097] Figure 7 This is a cross-sectional view showing an integrated circuit device 300A according to an embodiment of the present invention. Figure 7 It shows the corresponding to in Figure 2C The local structure of the region indicated as "EQ".

[0098] refer to Figure 7 The integrated circuit device 300A can have the same characteristics as the reference. Figure 6 The integrated circuit device 300 described has a substantially the same construction. However, the integrated circuit device 300A may include a first insulating structure ST31A and a second insulating structure ST32A, instead of a first insulating structure ST31 and a second insulating structure ST32.

[0099] The first insulation structure ST31A can have the same as the reference. Figure 6 The first insulating structure ST31 has a substantially the same construction as described. However, the first insulating structure ST31A may include a first upper buried insulating layer 316SA instead of a first upper buried insulating layer 316S. The first upper buried insulating layer 316SA may include a first silicon oxide layer S1 and a second silicon oxide layer S2 sequentially stacked on the first upper insulating pad 114S. The second insulating structure ST32A may have the same construction as the referenced... Figure 6 The second insulating structure ST32 has a substantially the same construction as described. However, the second insulating structure ST32A may include a second upper buried insulating layer 316DA instead of a second upper buried insulating layer 316D. The second upper buried insulating layer 316DA may include a first silicon oxide layer D1 and a second silicon oxide layer D2 sequentially stacked on the second upper insulating pad 114D. A more detailed description of the construction and effects of the first silicon oxide layers S1 and D1 and the second silicon oxide layers S2 and D2 is available in the reference. Figure 3 The descriptions are the same.

[0100] although Figures 3 to 7 Only the first fin-type active region F1 and its peripheral components in the first device region RX1 are shown, but reference is needed. Figures 3 to 7 The descriptions of the integrated circuit devices 100A, 200, 200A, 300 and 300A given can be applied in the same way to the second fin active region F2 and its peripheral components in the second device region RX2.

[0101] Figure 8 This is a block diagram of an integrated circuit device 400 according to an embodiment of the present invention.

[0102] refer to Figure 8 The integrated circuit device 400 may include a substrate 102, which includes a first region I and a second region II. The first region I and the second region II of the substrate 102 refer to different regions of the substrate 102 and may be regions on the substrate 102 that perform different operations. The first region I and the second region II may be regions that are spaced apart from each other in the horizontal direction.

[0103] In some embodiments, the first device region 1 may be a region where devices are formed to operate in a low-power mode, and the second device region 2 may be a region where devices are formed to operate in a high-power mode. In some embodiments, the first device region 1 may be a region where memory devices or non-memory devices are formed, and the second device region 2 may be a region where peripheral circuitry such as input / output devices (I / O) is formed.

[0104] In some embodiments, the first region I may be a region constituting a volatile memory device such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), or a non-volatile memory device such as Read-Only Memory (ROM), Mask ROM (MROM), Programmable Memory Device (PROM), Erasable ROM (EPROM), Electrically Erasable ROM (EEPROM), Ferroelectric ROM (FRAM), Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash Memory, etc. In some embodiments, the first region I may be a region where non-memory devices such as logic devices are formed. Logic devices may include standard cells that perform desired logic functions such as counters and buffers. Standard cells may include various types of logic units, including multiple circuit elements such as transistors and resistors. Logic units can be configured as follows: AND, NAND, OR, NOR, XOR, XNOR, inverter INV, adder ADD, buffer BUF, delay DLY, filter FIL, multiplexer MXT / MXIT, OR / AND / INVERTER (OAI), AND / OR (AO), AND / OR / INVERTER (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, latch, etc.

[0105] In the integrated circuit device 400, the pattern formation density in the second device region II can be less than the pattern formation density in the first device region I.

[0106] In some embodiments, the first region I may include a reference Figures 1 to 7 At least one of the structures described for integrated circuit devices 100, 100A, 200, 200A, 300, and 300A.

[0107] Figure 9 It is shown Figure 8 The plan view shows a partial structure of the second region II of the integrated circuit device 400. Figure 10 It shows along Figure 9 A cross-sectional view of the partial structure of the cross section intercepted by line Y4-Y4'.

[0108] refer to Figure 9 and Figure 10 The integrated circuit device 400 may include a plurality of finned active regions F3 protruding from the substrate 102 in a vertical direction (e.g., the Z direction) in a second region II. The plurality of finned active regions F3 may extend parallel to each other in a first horizontal direction (e.g., the X direction). Each of the plurality of finned active regions F3 may be defined by a device isolation trench STR4 formed in the substrate 102.

[0109] Multiple fin-type active regions F3 may have a fin top surface FT4 with a first horizontal height LV41. Gate line 162 may extend longitudinally in a second horizontal direction (e.g., Y direction) on the multiple fin-type active regions F3 (e.g., having a longitudinal axis extending in the second horizontal direction (e.g., Y direction)). Figure 9 and Figure 10 Two finned active regions F3 and a gate line 162 disposed on the two finned active regions F3 are shown, but the number of each of the finned active regions F3 and the gate line 162 is not limited to the example shown, and can be selected differently.

[0110] The device isolation trench STR4 in the second region II can be filled with a third insulating structure ST43. The third insulating structure ST43 can be located between the substrate 102 and the gate line 162, and can be located on the sidewall of the fin active region F3.

[0111] The third insulating structure ST43 may include a first insulating pad 112A, a second insulating pad 112B, a first lower buried insulating layer 112C, a third upper insulating pad 114E, and a third upper buried insulating layer 116E, which are sequentially stacked on a substrate 102 in the second region II.

[0112] Detailed construction and reference of the first insulating pad 112A, the second insulating pad 112B, and the first lower buried insulating layer 112C Figures 2A to 2D The descriptions are essentially the same. However, in the second region II, the first insulating pad 112A may contact the sidewall of the fin-type active region F3. The uppermost part of the first insulating pad 112A may be lower than the first horizontal height LV41 of the fin top surface FT4. The second insulating pad 112B may face the sidewall of the fin-type active region F3, with the first insulating pad 112A located therebetween. The second insulating pad 112B may have an uppermost part at a second horizontal height LV42 lower than the first horizontal height LV41.

[0113] The first lower buried insulating layer 112C may face the sidewall of the fin-type active region F3, with the first insulating pad 112A and the second insulating pad 112B located therebetween. The top surface of the first lower buried insulating layer 112C facing the gate line 162 may extend non-linearly in a second horizontal direction (e.g., the Y direction) at a level below the second horizontal height LV42. The top surface of the first lower buried insulating layer 112C facing the gate line 162 may have a recessed shape toward the gate line 162. The lowermost part of the top surface of the first lower buried insulating layer 112C may be at a third horizontal height LV43 below the second horizontal height LV42.

[0114] The distance from the fin top surface FT4 of the fin-type active region F3 to the third horizontal height LV43 in the vertical direction (e.g., the Z direction) can be greater than the vertical height H41 from the fin top surface FT4 of the fin-type active region F3 to the second horizontal height LV42. The third horizontal height LV43 is the horizontal height of the lowest part of the top surface of the first lower buried insulation layer 112C, and the second horizontal height LV42 is the horizontal height of the uppermost part of the second insulating pad 112B.

[0115] The third upper insulating pad 114E may be located between the second insulating pad 112B and the third upper buried insulating layer 116E, and between the first lower buried insulating layer 112C and the third upper buried insulating layer 116E. The third upper insulating pad 114E may include a portion that contacts the uppermost part of the second insulating pad 112B and a portion that contacts the top surface of the first lower buried insulating layer 112C.

[0116] The third upper buried insulating layer 116E may be located between the first lower buried insulating layer 112C and the gate line 162. The third upper insulating pad 114E may be located between the top surface of the first lower buried insulating layer 112C and the bottom surface of the third upper buried insulating layer 116E.

[0117] The third upper buried insulating layer 116E may have a top surface that extends flat in the horizontal direction (e.g., the X and Y directions) at a fourth horizontal height LV44, which is higher than the second horizontal height LV42. The bottom surface of the third upper buried insulating layer 116E may face the top surface of the first lower buried insulating layer 112C (with the third upper insulating pad 114E located therebetween) and has a convex shape toward the substrate 102 corresponding to the concave shape of the top surface of the first lower buried insulating layer 112C.

[0118] The vertical height H43 from the top surface FT4 of the fin-type active region F3 to the fourth horizontal height LV44, which is the top surface of the third upper buried insulation layer 116E, can be equal to or less than the vertical height H41 from the top surface FT4 to the second horizontal height LV42. That is, the horizontal height of the top surface of the third upper buried insulation layer 116E can be equal to or higher than the uppermost horizontal height of the second insulating pad 112B.

[0119] In some embodiments, the fourth horizontal height LV44, which is the horizontal height of the top surface of the third upper buried insulation layer 116E in the second region II, may be higher than the fourth horizontal height LV4, which is the horizontal height of the top surface of the first upper insulating pad 114S in the first region I (see [reference]). Figure 2D ), and can be below the sixth horizontal height LV6 (see) of the top surface of the second upper buried insulation layer 116D in the first region I. Figure 2DHowever, the embodiments of the present invention are not limited thereto.

[0120] The material of the third insulating pad 114E can be compared with the reference. Figures 2A to 2D The material of the first upper insulating pad 114S described is the same as that of the third upper buried insulating layer 116E. Figures 2A to 2D The first upper buried insulating layer 116S described is made of the same material. In some embodiments, the first upper insulating pad 114S and the third upper insulating pad 114E may comprise a silicon oxide layer, and the first upper buried insulating layer 116S and the third upper buried insulating layer 116E may comprise a silicon oxide layer containing at least one impurity element selected from nitrogen (N) atoms and fluorine (F) atoms. In some embodiments, the content of the impurity element in each of the first upper buried insulating layer 116S and the third upper buried insulating layer 116E may be from about 0.1 atomic% to about 20 atomic% but is not limited thereto. A more detailed construction of the third upper insulating pad 114E and the third upper buried insulating layer 116E is described in reference. Figures 2A to 2D The first upper insulating pad 114S and the first upper buried insulating layer 116S are described in the same way.

[0121] In some embodiments, similar to the reference Figure 3 Regarding the description of the first upper buried insulating layer 116SA, the third upper buried insulating layer 116E may include a first silicon oxide layer S1 and a second silicon oxide layer S2 sequentially stacked on the third upper insulating pad 114E. In some embodiments, similar to the reference... Figure 4 Regarding the description of the first upper buried insulating layer 216S, the third upper buried insulating layer 116E may have a top surface with a convex shape facing the gate line 162. In some embodiments, similar to the reference... Figure 6 In the description of the first upper buried insulating layer 316S, the third upper buried insulating layer 116E may have a top surface with a recessed shape facing the gate line 162.

[0122] In the second region II, gate line 162 can extend longitudinally in the second horizontal direction (e.g., the Y direction) on both sidewalls of the fin top surface FT4 and the fin active region F3, while simultaneously covering the fin active region F3 and the third insulating structure ST43. Figure 9 As shown, in the first horizontal direction (e.g., the X direction), the width of the gate line 162 in the second region II can be greater than the width of the gate line 160 in the first region I.

[0123] In the second region II, the gate dielectric layer 450 may be located between the fin active region F3 and the gate line 162. The gate dielectric layer 450 may include a lower gate dielectric layer 114G that contacts the fin active region F3, and an upper gate dielectric layer 452 that covers the lower gate dielectric layer 114G and contacts the bottom surface of the gate line 162.

[0124] The lower gate dielectric layer 114G may be integrally connected to the third upper insulating pad 114E and may comprise the same material as the third upper insulating pad 114E. For example, each of the lower gate dielectric layer 114G and the third upper insulating pad 114E may comprise a silicon oxide layer.

[0125] The upper gate dielectric layer 452 may contact the lower gate dielectric layer 114G on the finned active region F3, and may be spaced apart from the third upper insulating pad 114E in the vertical direction (e.g., the Z direction) on the device isolation trench STR4, with the third upper buried insulating layer 116E located therebetween. Figures 2A to 2D The material is the same. For example, the upper gate dielectric layer 452 may include a high dielectric layer. A detailed description of the high dielectric layer is provided in the reference. Figures 2A to 2D The descriptions are the same.

[0126] The top surface of gate line 162 can be covered by an insulating pattern 166. The insulating pattern 166 can have the same characteristics as the reference pattern. Figures 2A to 2C The basic construction is the same as that described for the covering insulation pattern 164. The covering insulation pattern 166 can be covered by the interlayer insulation layer 190.

[0127] refer to Figures 8 to 10The described integrated circuit device 400 may include a first insulating structure ST1 and a third insulating structure ST43 covering the sidewalls of each of the finned active regions F1, F2, and F3 between the substrate 102 and the gate lines 160 and 162 in the first region I and the second region II. The first insulating structure ST1 and the third insulating structure ST43 may respectively include a first upper insulating pad 114S and a third upper insulating pad 114E covering the top surface of the first lower buried insulating layer 112C, and a first upper buried insulating layer 116S and a third upper buried insulating layer 116E, and the horizontal height of the top surface of each of the first upper buried insulating layer 116S and the third upper buried insulating layer 116E may be equal to or higher than the horizontal height of the uppermost part of the second insulating pad 112B. Therefore, even when the horizontal height of the top surface of the first lower buried insulating layer 112C is lower than the horizontal height of the uppermost part of the second insulating pad 112B, the space on the top surface of the first lower buried insulating layer 112C that is lower than the horizontal height of the uppermost part of the second insulating pad 112B can be filled by the first upper insulating pad 114S and the third upper insulating pad 114E, as well as the first upper buried insulating layer 116S and the third upper buried insulating layer 116E. Therefore, through the first insulating structure ST1 and the third insulating structure ST43 in the first region I and the second region II, sufficient insulation space can be ensured between the fin active regions F1, F2, and F3 and the gate lines 160 and 162, thus reducing undesirable parasitic capacitances between the fin active regions F1, F2, and F3 and the gate lines 160 and 162. Therefore, the performance and reliability of the transistors included in the integrated circuit device 400 can be improved.

[0128] Figures 11A to 20D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment of the present invention. Figure 11A , Figure 12A ,……,and Figure 20A It is shown along Figure 1 A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line X1-X1'. Figure 11B , Figure 12B ,……,and Figure 20B It is shown along Figure 1 A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line X2-X2'. Figure 11C , Figure 12C ,……,and Figure 20C It is shown along Figure 1 A cross-sectional view of the local structure of the portion corresponding to the cross section intercepted by line Y1-Y1', and Figure 11D , Figure 12D ,……,and Figure 20D It is shown along Figure 9A cross-sectional view of the local structure corresponding to the cross section intercepted by line Y4-Y4'. (Refer to...) Figures 11A to 20D Description of manufacturing Figures 8 to 10 The method of the integrated circuit device 400 shown is illustrated here. As an example, the first region I of the integrated circuit device 400 is described as including, as referenced... Figures 1 to 2D The construction of the integrated circuit device 100 is described. Figures 11A to 20D In, with Figures 1 to 10 The same reference numerals in the figures denote the same components, and their detailed descriptions are omitted here.

[0129] refer to Figures 11A to 11D By alternately stacking a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS on a substrate 102 in the first region I, and then etching a portion of each of the sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the substrate 102, a device isolation trench STR is formed in the substrate 102. As a result, a plurality of fin-type active regions F1 and F2 protruding upward from the substrate 102 can be formed in the first device region RX1 and the second device region RX2 in the first region I in the vertical direction (e.g., the Z direction). The stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS can be retained on the fin top surface FT of each of the plurality of fin-type active regions F1 and F2.

[0130] The plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may comprise semiconductor materials with different etch selectivity. In some embodiments, the plurality of nanosheet semiconductor layers NS may comprise a Si layer, and the plurality of sacrificial semiconductor layers 104 may comprise a SiGe layer. In some embodiments, the Ge content in the plurality of sacrificial semiconductor layers 104 may be constant. The SiGe layer constituting the plurality of sacrificial semiconductor layers 104 may have a constant Ge content selected in the range of about 5 atomic percent to about 60 atomic percent (e.g., about 10 atomic percent to about 40 atomic percent). The Ge content in the SiGe layer constituting the plurality of sacrificial semiconductor layers 104 may be selected differently as needed.

[0131] A portion of the substrate 102 is etched in the second region II to form a device isolation trench STR4 in the substrate 102. As a result, a plurality of fin-type active regions F3 can be formed in the second region II, protruding upward from the substrate 102 in a vertical direction (e.g., the Z direction) and extending parallel to each other in a first horizontal direction (e.g., the X direction).

[0132] refer to Figures 12A to 12D Through the first region I and the second region II Figures 11A to 11DA composite insulating layer 112 is formed on the product, and then a portion of the composite insulating layer 112 in the inter-device isolation region DTA of the first region I is etched. As a result, a portion of the substrate 102 is exposed by etching. A deep trench DTR defining a first device region RX1 and a second device region RX2 can be formed in the first region I, and the deep trench DTR can be filled with a second lower buried insulating layer 113.

[0133] In some embodiments, the process of forming the composite insulating layer 112 may include forming a conformal overlay. Figures 11A to 11D The product has an exposed surface of a first insulating pad 112A, a second insulating pad 112B that conformally covers the top surface of the first insulating pad 112A, and a first lower buried insulating layer 112C formed in the space between a plurality of finned active regions F1, F2, and F3 on the second insulating pad 112B. The first lower buried insulating layer 112C may be formed to have a top surface that extends flatly at a horizontal height higher than the horizontal height of the plurality of finned active regions F1, F2, and F3.

[0134] In some embodiments, the first insulating pad 112A may include a silicon oxide layer, and the second insulating pad 112B may include a silicon nitride layer. The first lower buried insulating layer 112C may include a silicon oxide layer formed using a flowable chemical vapor deposition (FCVD) process or a spin-coating process. The second lower buried insulating layer 113 may include a silicon oxide layer formed using a plasma deposition method. The density of the silicon oxide layer constituting the second lower buried insulating layer 113 may be greater than the density of the silicon oxide layer constituting the first lower buried insulating layer 112C.

[0135] refer to Figures 13A to 13D , Figures 12A to 12D The composite insulating layer 112 and the second buried insulating layer 113 in the product can be etched back in the first region I and the second region II, such that the sidewalls of each of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS are exposed in the first region I, and the fin top surface FT4 of each of the plurality of fin active regions F3 and the two sidewalls of the upper part of each of the plurality of fin active regions F3 are exposed in the second region II.

[0136] In this respect, the density of the second buried insulating layer 113 can be higher than that of the first buried insulating layer 112C, so that the top surface of the second buried insulating layer 113 remaining on the substrate 102 after the etch-back composite insulating layer 112 and the second buried insulating layer 113 can be higher than the top surface of the first buried insulating layer 112C.

[0137] Similar to a reference Figure 2DAs described, after the composite insulating layer 112 and the second lower buried insulating layer 113 in the first region I and the second region II, the second insulating liner 112B may have an uppermost portion of a second horizontal height LV2 that is lower than the first horizontal height LV1 of the fin top surface FT, the top surface of the first lower buried insulating layer 112C may have a lowermost portion of a third horizontal height LV3 that is lower than the second horizontal height LV2, and the top surface of the second lower buried insulating layer 113 may have an uppermost portion of a fifth horizontal height LV5 that is higher than the third horizontal height LV3. In the first region I, the second height H2, which is the distance from the fin top surface FT of each of the plurality of fin active regions F1 and F2 to the third horizontal height LV3 in the vertical direction (e.g., the Z direction), may be greater than the first height H1, which is the distance from the fin top surface FT to the second horizontal height LV2 in the vertical direction (e.g., the Z direction).

[0138] After etching back the composite insulating layer 112 in the second region II, the upper portion of each of the plurality of fin-type active regions F3 can protrude from the upper portion of the composite insulating layer 112. When the composite insulating layer 112 is etched back in the second region II, the upper portion of each of the plurality of fin-type active regions F3 is exposed to the etching atmosphere of the composite insulating layer 112, thus reducing the width and height of each of the plurality of fin-type active regions F3. As a result of etching back the composite insulating layer 112 in the second region II, the horizontal height of the fin tip surface FT4 of each of the plurality of fin-type active regions F3 can be higher than the horizontal height of the fin tip surface FT of each of the plurality of fin-type active regions F1 and F2.

[0139] refer to Figures 14A to 14D It can be in the first region I and the second region II. Figures 13A to 13D A stacked pattern comprising an upper insulating pad 114, a dummy gate pattern DP, and a dummy overlay pattern DC is formed on the product, and an outer insulating spacer 118 may be formed to cover the two sidewalls of the stacked pattern in the second horizontal direction (e.g., the X direction). In the first region I, the stacked pattern may be formed as if... Figure 1 The position corresponding to the gate line 160 shown extends longitudinally in the second horizontal direction (e.g., the Y direction). In the second region II, the stacked pattern can be formed in accordance with... Figure 9 The gate line 162 shown corresponds to a position that extends longitudinally in a second horizontal direction (e.g., the Y direction). In some embodiments, the upper insulating pad 114 may include a silicon oxide layer formed using a plasma deposition method, the dummy gate pattern DP may include a polysilicon layer, and the dummy overlay pattern DC may include a silicon nitride layer. The density of the upper insulating pad 114 may be greater than the density of the first lower buried insulating layer 112C.

[0140] Subsequently, a nanosheet stack NSS comprising first to third nanosheets N1, N2, and N3 can be formed from the multiple nanosheet semiconductor layers NS in the first device region RX1 of the first device region I by selectively removing a portion of each of the multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NS in the product having the stacked pattern and outer insulating spacers 118. By etching a portion of the first fin active region F1 on both sides of the nanosheet stack NSS, multiple first recesses R1 can be formed in the upper part of the first fin active region F1. After providing recessed spaces by selectively removing a portion of the multiple sacrificial semiconductor layers 104 exposed from both sides of the nanosheet stack NSS through the multiple first recesses R1, multiple inner insulating spacers 120 can be formed filling the recessed spaces, and multiple first source / drain regions SD1 filling the multiple first recesses R1 can be formed on both sides of the nanosheet stack NSS.

[0141] To form multiple first source / drain regions SD1, semiconductor material can be epitaxially grown on the surface of a first fin-type active region F1 exposed from the bottom surface of multiple first recesses R1 and on each sidewall of each of the first to third nanosheets N1, N2, and N3. In some embodiments, to form multiple first source / drain regions SD1, a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process can be performed using raw materials including elemental semiconductor precursors. In some embodiments, the multiple first source / drain regions SD1 may include a Si layer doped with an n-type dopant. To form multiple first source / drain regions SD1, silane (SiH4), disilane (Si2H6), propane (Si3H8), dichlorosilane (SiH2Cl2), etc., can be used as the Si source. The n-type dopant can be selected from P (phosphorus), As (arsenic), and Sb (antimony).

[0142] In some embodiments, when a plurality of first source / drain regions SD1 are formed in the first device region RX1 of the first region I, a plurality of third source / drain regions (not shown) may be formed on both sides of the stacked pattern on a portion of a plurality of fin active regions F3 in the second region II.

[0143] Furthermore, a nanosheet stack NSS comprising first to third nanosheets N1, N2, and N3 can be formed from multiple nanosheet semiconductor layers NSS by selectively removing a portion of each of multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NSS from the second device region RX2 of the first region I. By etching the second fin active regions F2 exposed from both sides of the nanosheet stack NSS, multiple second recesses R2 can be formed in the upper part of the second fin active regions F2, and multiple source / drain regions SD2 filled in the multiple second recesses R2 can be formed on both sides of the nanosheet stack NSS. Similar to the description of multiple first source / drain regions SD1, in order to form multiple second source / drain regions SD2, the surface of the second fin active regions F2 exposed from the bottom surface of the multiple second recesses R2 and the semiconductor material from each sidewall of each of the first to third nanosheets N1, N2, and N3 can be epitaxially grown. In some embodiments, the multiple second source / drain regions SD2 may comprise a SiGe layer doped with a p-type dopant. Multiple second source / drain regions SD2 can be formed using Si and Ge sources. As Si sources, silane (SiH4), disilane (Si2H6), propane (Si3H8), dichlorosilane (SiH2Cl2), etc., can be used. As Ge sources, germanane (GeH4), digermanane (Ge2H6), propane (Ge3H8), tetragermanane (Ge4H6), etc., can be used. 10 ), dichlorogermanane (Ge2H2C) l2 p-type dopants can be selected from boron (B) and gallium (Ga).

[0144] In some embodiments, when a plurality of second source / drain regions SD2 are formed in the second device region RX2 of the first region I, a plurality of fourth source / drain regions (not shown) may be formed on both sides of the stacked pattern on a portion of a plurality of fin active regions F3 in the second region II.

[0145] Subsequently, in the first region I, an insulating pad 142 may be formed covering the surface of each of the plurality of first source / drain regions SD1 and second source / drain regions SD2, as well as the surface of each of the plurality of external insulating spacers 118, and an inter-gate insulating layer 144 may be formed on the insulating pad 142. Similar to the first region I, the insulating pad 142 and the inter-gate insulating layer 144 may be formed to cover each of the plurality of third source / drain regions (not shown) and the plurality of fourth source / drain regions (not shown) on both sides of the second horizontal direction (e.g., the X direction) of the stacked pattern in the second region II.

[0146] refer to Figures 15A to 15D It can be obtained from Figures 14A to 14DThe dummy overlay pattern DC is removed from the product to expose the top surface of the dummy gate pattern DP, and the multiple outer insulating spacers 118, insulating pads 142, and inter-gate insulating layer 144 can be planarized. Thereafter, a gate space GS can be provided by removing the dummy gate pattern DP, and the upper insulating pad 114 can be exposed through the gate space GS.

[0147] refer to Figures 16A to 16D ,exist Figures 15A to 15D In the product, an upper buried insulating layer 116 can be formed on the upper insulating pad 114. As the upper buried insulating layer 116 is closer to the substrate 102, the upper buried insulating layer 116 can be formed to have a greater thickness. The upper buried insulating layer 116 may include a silicon oxide layer.

[0148] In some embodiments, in order to form the upper buried insulation layer 116, it can be relative to Figures 15A to 15D The products are alternately processed multiple times using a suppressor plasma exposure process and a vapor deposition process including at least one atomic layer deposition (ALD) cycle. The suppressor plasma exposure process can be performed before and after one ALD cycle, or it can be performed once every certain number of ALD cycles.

[0149] During the inhibitor plasma exposure process, including Figures 15A to 15D The upper portion of the surface of the product structure can be passivated by inhibitor plasma, which can suppress deposition in some regions relatively far from the substrate 102 on the upper side during subsequent deposition processes. In some embodiments, a nitrogen atom source can be used to form the inhibitor plasma. In some embodiments, the nitrogen atom source may include, but is not limited to, NF3, N2, or combinations thereof.

[0150] During the inhibitor plasma exposure process in the first region I and the second region II, the upper region of each of the multiple fin active regions F1, F2 and F3 located relatively far from the substrate 102 can have a significant passivation effect through the inhibitor plasma, and as the upper region gets closer to the substrate 102, the passivation effect of the inhibitor plasma can gradually decrease or have almost no passivation effect.

[0151] During a deposition process including at least one ALD cycle, the upper buried insulating layer 116 can be deposited to a greater thickness in the portion closer to the substrate 102 relative to the upper region which has a relatively significant passivation effect by inhibitory plasma for each of the plurality of fin active regions F1, F2 and F3, thereby improving the bottom-up filling effect when forming the upper buried insulating layer 116.

[0152] After the upper buried insulation layer 116 is formed, the horizontal height of the top surface HV12 of the portion of the upper buried insulation layer 116 covering the second lower buried insulation layer 113 in the first region I can be a first height DHV1 higher than the horizontal height of the top surfaces HV11 and HV13 of each portion covering the first lower buried insulation layer 112C in the first region I and the second region II.

[0153] In some embodiments, when N2 is used as the nitrogen atom source for forming the inhibitor plasma in the formation of the upper buried insulating layer 116, the upper buried insulating layer 116 may include a silicon oxide layer containing impurity elements, including nitrogen (N) atoms. In some embodiments, when NF3 is used as the nitrogen atom source for forming the inhibitor plasma, the upper buried insulating layer 116 may include a silicon oxide layer containing impurity elements, including fluorine (F) atoms. In some embodiments, when a combination of N2 and NF3 is used as the nitrogen atom source for forming the inhibitor plasma, the upper buried insulating layer 116 may include a silicon oxide layer containing impurity elements, including nitrogen (N) atoms and fluorine (F) atoms.

[0154] refer to Figures 17A to 17D , can Figures 16A to 16D A mask pattern MP covering the second region II is formed in the product. In some embodiments, the mask pattern MP may include a photoresist pattern. Subsequently, when the second region II is covered by the mask pattern MP, the sidewalls of each of the plurality of nanosheets N1, N2, and N3 and the plurality of sacrificial semiconductor layers 104 can be exposed in the gate space GS of the first region I by removing a portion of the upper side of each of the upper buried insulating layer 116 and the upper insulating pad 114 in the first region I. As a result, the height of the top surface of each of the upper buried insulating layer 116 and the upper insulating pad 114 can be reduced.

[0155] After a portion of the upper side of each of the upper buried insulation layer 116 and the upper insulating liner 114 is removed in the first region, the horizontal height of the top surface HV22 of the portion of the upper buried insulation layer 116 covering the second lower buried insulation layer 113 in the first region I may be higher than the horizontal height of the top surface HV21 covering each portion of the first lower buried insulation layer 112C.

[0156] refer to Figures 18A to 18D From Figures 17A to 17D After removing the mask pattern MP in the second region II of the product, the multiple sacrificial semiconductor layers 104 retained on the multiple fin active regions F1 and F2 are selectively removed through the gate space GS at the top of the nanosheet stack NSS in the first region I. The gate space GS can extend to the space between the multiple nanosheets N1, N2 and N3 and the space between the first nanosheet N1 and the fin top surface FT.

[0157] In some embodiments, to selectively remove the plurality of sacrificial semiconductor layers 104, the etch selectivity difference between the plurality of nanosheets N1, N2, and N3 and the plurality of sacrificial semiconductor layers 104 can be utilized. Liquid or gaseous etchants can be used to selectively remove the plurality of sacrificial semiconductor layers 104. In some embodiments, to selectively remove the plurality of sacrificial semiconductor layers 104, CH3COOH-based etchants can be used, for example, etchants comprising a mixture of CH3COOH, HNO3, and HF, or etchants comprising a mixture of CH3COOH, H2O2, and HF, but are not limited to the examples described above.

[0158] During the etching process that selectively removes multiple sacrificial semiconductor layers 104, the upper buried insulating layer 116 and the upper insulating pad 114 may also be exposed to the etching atmosphere in the first region I and the second region II. As a result, a small portion of the upper side of each of the upper buried insulating layer 116 and the upper insulating pad 114 may be consumed by the etching atmosphere.

[0159] After removing multiple sacrificial semiconductor layers 104, as referenced Figure 2D The first upper buried insulating layer 116S with a top surface having a fourth horizontal height LV4 and the second upper buried insulating layer 116D with a top surface having a sixth horizontal height LV6 can be obtained from the upper buried insulating layer 116, and the first upper insulating pad 114S and the second upper insulating pad 114D can be obtained from the upper insulating pad 114 in the first region I. In the second region II, as referenced Figure 10 The third upper buried insulating layer 116E, having a top surface with a fourth horizontal height LV44, can be obtained from the upper buried insulating layer 116, and the upper insulating pad 114 can be retained as the third upper insulating pad 114E between the first lower buried insulating layer 112C and the third upper buried insulating layer 116E, and the lower gate dielectric layer 114G in contact with the fin active region F3. The fourth horizontal height LV44 of the top surface of the third upper buried insulating layer 116E in the second region II can be higher than the fourth horizontal height LV4 of the top surface of the first upper buried insulating layer 116S in the first region I, and can be lower than the sixth horizontal height LV6 of the top surface of the second upper buried insulating layer 116D in the first region I.

[0160] refer to Figures 19A to 19D Through Figures 18A to 18D A high dielectric layer is formed on the product. A gate dielectric layer 152 covering the exposed surface of multiple nanosheets N1, N2, N3 and multiple fin active regions F1 can be formed in the first region I. An upper gate dielectric layer 452 covering the upper part of the fin active region F3 can be formed in the second region II. A lower gate dielectric layer 114G is located between the upper part of the fin active region F3 and the upper gate dielectric layer 452.

[0161] In the first region I, the gate dielectric layer 152 may be formed to conformally cover the surfaces of the plurality of external insulating spacers 118 exposed through the gate space GS. In the second region II, the lower gate dielectric layer 114G and the upper gate dielectric layer 452 may form a gate dielectric layer 450.

[0162] refer to Figures 20A to 20D , can Figures 19A to 19D A conductive layer is formed in the product, filling the gate space GS. Then, etch-back occurs, leaving a portion of the upper side of the gate space GS vacated again. As a result, a gate line 160 covering the gate dielectric layer 152 can be formed in the first region I, and a gate line 162 covering the gate dielectric layer 450 can be formed in the second region II. Subsequently, insulating patterns 164 and 166, filling the gate space GS, can be formed on the gate lines 160 and 162 in the first region I and the second region II.

[0163] Subsequently, multiple source / drain contact holes (not shown) can be formed in the first device region RX1 and the second device region RX2 of the first region I, respectively, penetrating the inter-gate insulating layer 144 and the insulating pad 142 in the vertical direction (e.g., the Z direction) and exposing multiple first source / drain regions SD1 and multiple second source / drain regions SD2. Then, multiple metal silicide layers 172 covering the multiple source / drain regions SD1 and SD2 can be formed in the lower part of the multiple source / drain contact holes (see Figure 2A and Figure 2B ) and multiple source / drain contacts 174 filled in multiple source / drain contact vias (see Figure 2A and Figure 2B Furthermore, a gate contact 184 may be formed that penetrates the covering insulating pattern 164 in the vertical direction (e.g., the Z direction) and connects to the gate line 160 (see [link to relevant documentation]). Figure 2C ).

[0164] After that, as Figures 2A to 2D and Figure 10 As shown, an interlayer insulating layer 190 can be formed on the product forming the active / drain contact 174 and the gate contact 184. Thereafter, as... Figures 2A to 2C As shown, multiple source / drain path contacts 192 that penetrate the interlayer insulating layer 190 and are connected to multiple source / drain contacts 174, and gate path contacts 194 that penetrate the interlayer insulating layer 190 and are connected to gate contacts 184 can be formed in the first region I.

[0165] The above describes a method for manufacturing an integrated circuit device 400, which includes a reference in a first region I. Figures 2A to 2D The described structure and references in the second region Figure 9 and Figure 10 The described structure, but it should be understood that, Figures 3 to 7 The integrated circuit devices 100A, 200, 200A, 300, and 300A shown, as well as integrated circuit devices with various structures modified and altered therefrom, can be referenced in the reference. Figures 11A to 20D Various modifications and alterations may be made within the scope of the embodiments of the inventive concept described herein.

[0166] In some embodiments, for manufacturing Figure 4 and Figure 6 The integrated circuit devices 200 and 300 shown are in reference. Figures 17A to 17D In the described process, by controlling the etching atmosphere of the buried insulating layer 116, a structure such as... Figure 4 The first upper buried insulating layer 216S and the second upper buried insulating layer 216D shown have a protruding top surface facing the gate line 160, or can be formed as follows: Figure 6 The diagram shows a first upper buried insulating layer 316S and a second upper buried insulating layer 316D with recessed top surfaces facing the gate line 160. Reference can then be performed. Figures 18A to 20D The following processes are described for manufacturing. Figure 4 and Figure 6 The integrated circuit devices 200 and 300 are shown.

[0167] In some embodiments, for manufacturing Figure 3 , Figure 5 and Figure 7 The integrated circuit devices 100A, 200A, and 300A shown can be executed via reference... Figures 17A to 17D The described process, or implementation reference Figures 18A to 18D The described process involves purifying the product using a gas including H2, N2, Ar, He, or combinations thereof, and removing impurity elements such as nitrogen (N) atoms and / or fluorine (F) atoms from the exposed surface of the upper buried insulating layer 116 or the exposed surface of each of the first upper buried insulating layer 116S and the second upper buried insulating layer 116D, forming a first silicon oxide layer S1 and a second silicon oxide layer S2 from the upper buried insulating layer 116 or the first upper buried insulating layer 116S and the second upper buried insulating layer 116D. Here, the second silicon oxide layer S2 may correspond to the portion of the upper buried insulating layer 116 or the first upper buried insulating layer 116S and the second upper buried insulating layer 116D from which impurity elements have been removed by the purification process, and the first silicon oxide layer S1 may correspond to the remaining portion of the upper buried insulating layer 116 or the first upper buried insulating layer 116S and the second upper buried insulating layer 116D unaffected by the purification process.

[0168] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A fin-shaped active region extends on a substrate in a first horizontal direction and includes a fin top surface located at a first horizontal height; A gate line that extends over the fin-type active region in a second horizontal direction that intersects the first horizontal direction. as well as An insulating structure is provided, located between the substrate and the gate line, and on the sidewall of the finned active region. The insulating structure includes: A first insulating pad is in contact with the sidewall of the fin-shaped active region; A second insulating pad is located on the sidewall of the fin active region and includes an uppermost portion at a second horizontal height. The first insulating pad is located between the second insulating pad and the sidewall of the fin active region. The second horizontal height is closer to the bottom surface of the substrate than the first horizontal height. A lower buried insulating layer, the lower buried insulating layer being located on the sidewall of the fin active region, and including a first top surface facing the gate line at a third horizontal height, the first insulating pad and the second insulating pad being located between the lower buried insulating layer and the sidewall of the fin active region, the third horizontal height being closer to the bottom surface of the substrate than the second horizontal height; and An upper buried insulating layer is located between the lower buried insulating layer and the gate line, and includes a second top surface located at a fourth horizontal height, wherein the fourth horizontal height and the second horizontal height are at the same distance from the bottom surface of the substrate, or the fourth horizontal height is farther from the bottom surface of the substrate than the second horizontal height.

2. The integrated circuit device according to claim 1, wherein, The buried insulating layer includes a silicon oxide layer containing at least one impurity element selected from nitrogen and / or fluorine.

3. The integrated circuit device according to claim 1, wherein, The buried insulating layer includes: A first silicon oxide layer, the first silicon oxide layer comprising nitrogen atoms and / or fluorine atoms; and A second silicon oxide layer is located between the first silicon oxide layer and the gate line.

4. The integrated circuit device according to claim 1, wherein, The insulation structure further includes an upper insulating pad located between the second insulating pad and the upper buried insulating layer, and an upper insulating pad located between the lower buried insulating layer and the upper buried insulating layer. The upper insulating pad includes a first portion that contacts the uppermost part of the second insulating pad and a second portion that contacts the first top surface of the lower buried insulating layer.

5. The integrated circuit device according to claim 1, wherein, The first insulating pad and the second insulating pad are made of different materials.

6. The integrated circuit device according to claim 1, wherein, The first top surface of the lower buried insulating layer has a recessed shape facing the gate line, and The bottom surface of the upper buried insulating layer faces the first top surface and has a convex shape toward the substrate.

7. The integrated circuit device according to claim 1, wherein, The second top surface of the buried insulating layer has a planar shape extending in the second horizontal direction.

8. The integrated circuit device according to claim 1, wherein, The second top surface of the buried insulating layer has a protruding shape toward the gate line.

9. The integrated circuit device according to claim 1, wherein, The second top surface of the buried insulating layer has a recessed shape facing the gate line.

10. The integrated circuit device according to claim 1, wherein, The insulation structure further includes an upper insulating pad, which is located between the second insulating pad and the upper buried insulating layer, and between the lower buried insulating layer and the upper buried insulating layer. The first insulating pad includes a first silicon oxide layer. The second insulating pad includes a silicon nitride layer. The lower buried insulating layer includes a second silicon oxide layer. The upper insulating pad includes a third silicon oxide layer. The upper buried insulating layer includes a fourth silicon oxide layer containing nitrogen and / or fluorine, and The density of the second silicon oxide layer is lower than the density of each of the third and fourth silicon oxide layers.

11. An integrated circuit device, comprising: A substrate, the substrate including a device region and an inter-device isolation region defining the device region; A fin-shaped active region extends in the device region in a first horizontal direction and includes a fin top surface located at a first horizontal height; A nanosheet stack comprising at least one nanosheet located on the top surface of the fin and spaced apart from the top surface of the fin in a vertical direction, each nanosheet in the nanosheet stack having a different vertical distance from the top surface of the fin; A gate line, the gate line being located on at least one nanosheet on the fin active region and extending in a second horizontal direction intersecting the first horizontal direction in the device region and the inter-device isolation region; A first insulating structure is located in the device region between the substrate and the gate line, and on the sidewall of the fin active region; as well as A second insulating structure is located in the inter-device isolation region between the substrate and the gate line. The first insulating structure includes: A first insulating pad is in contact with the sidewall of the fin-shaped active region; A second insulating pad is located on the sidewall of the fin active region and includes an uppermost portion at a second horizontal height. The first insulating pad is located between the second insulating pad and the sidewall of the fin active region. The second horizontal height is closer to the bottom surface of the substrate than the first horizontal height. A first lower buried insulating layer is located on the sidewall of the fin active region and includes a first top surface facing the gate line at a third horizontal height. A first insulating pad and a second insulating pad are located between the first lower buried insulating layer and the sidewall of the fin active region. The third horizontal height is closer to the bottom surface of the substrate than the second horizontal height. A first upper buried insulating layer is located between the first lower buried insulating layer and the gate line, and includes a second top surface located at a fourth horizontal height, wherein the fourth horizontal height and the second horizontal height are at the same distance from the bottom surface of the substrate, or the fourth horizontal height is farther from the bottom surface of the substrate than the second horizontal height.

12. The integrated circuit device according to claim 11, wherein, The second insulation structure includes: A second lower buried insulating layer, located between the substrate and the gate line, and including a third top surface at a fifth horizontal height, the fifth horizontal height being further away from the bottom surface of the substrate than the third horizontal height of the first lower buried insulating layer; and A second upper buried insulating layer is located between the second lower buried insulating layer and the gate line, and includes a fourth top surface located at a sixth horizontal height, the sixth horizontal height being further away from the bottom surface of the substrate than the fourth horizontal height.

13. The integrated circuit device according to claim 12, wherein, Each of the first and second upper buried insulating layers includes a silicon oxide layer containing nitrogen and / or fluorine.

14. The integrated circuit device according to claim 12, wherein, Each of the first upper buried insulation layer and the second upper buried insulation layer includes: A first silicon oxide layer, the first silicon oxide layer comprising nitrogen and / or fluorine; and A second silicon oxide layer is located between the first silicon oxide layer and the gate line.

15. The integrated circuit device according to claim 12, wherein, The first insulation structure further includes a first upper insulating pad, which is located between the second insulating pad and the first upper buried insulation layer, and between the first lower buried insulation layer and the first upper buried insulation layer. The second insulation structure further includes a second upper insulating gasket located between the second lower buried insulation layer and the second upper buried insulation layer, and The first upper insulating pad includes a first portion that contacts the uppermost part of the second insulating pad and a second portion that contacts the first top surface of the first lower buried insulating layer.

16. The integrated circuit device according to claim 12, wherein, The first buried insulating layer includes a first silicon oxide layer having a first density, and The second buried insulating layer includes a second silicon oxide layer having a second density that is greater than that of the first layer.

17. An integrated circuit device, comprising: The substrate includes a first region and a second region spaced apart from each other, and further includes a first device isolation trench located in the first region and a second device isolation trench located in the second region; A first fin-shaped active region, the first fin-shaped active region being defined in the first region by the first device isolation trench; At least one nanosheet, the at least one nanosheet being located on the top surface of the first fin of the first fin active region and spaced apart from the top surface of the first fin in the vertical direction; The second fin-type active region is defined in the second region by the second device isolation trench and includes a second fin top surface that is higher than the first fin top surface relative to the bottom surface of the substrate. A first insulating structure is located on the sidewall of the first fin-shaped active region in the first region; as well as The second insulating structure is located on the sidewall of the second fin-shaped active region in the second region. Each of the first insulating structure and the second insulating structure includes: A first insulating pad, the first insulating pad being in contact with the substrate; A second insulating pad is located on the first insulating pad and includes an uppermost portion at a second horizontal height, which is lower than the first horizontal height of the first fin top surface relative to the bottom surface of the substrate. A lower buried insulating layer, the lower buried insulating layer being located on the second insulating pad, and including a first top surface at a third horizontal height, the third horizontal height being lower than the second horizontal height relative to the bottom surface of the substrate; and An upper buried insulating layer is located on the uppermost part of the second insulating pad and the first top surface of the lower buried insulating layer, and includes a second top surface located at a fourth horizontal height, the fourth horizontal height being equal to or higher than the second horizontal height relative to the bottom surface of the substrate.

18. The integrated circuit device according to claim 17, wherein, The first fin-shaped active region extends in the first horizontal direction, and The integrated circuit device further includes: A first gate line is located on the at least one nanosheet in the first region and extends in a second horizontal direction intersecting the first horizontal direction on the first fin active region and the first insulating structure. A first gate dielectric layer is located between the first fin active region and the first gate line; The second gate line is located on the second fin top surface and sidewall of the second fin active region in the second region, and extends in the second horizontal direction on the second fin active region and the second insulating structure; and A second gate dielectric layer is located between the second fin-type active region and the second gate line, and contacts the second fin top surface and the sidewall of the second fin-type active region. The first insulating structure further includes a first upper insulating pad located between the lower buried insulating layer and the upper buried insulating layer, and includes a first material different from the second material of the first gate dielectric layer. The second insulating structure further includes a second upper insulating pad, and The second upper insulating pad is located between the lower buried insulating layer and the upper buried insulating layer, includes the first material, and is integrally connected to the second gate dielectric layer.

19. The integrated circuit device according to claim 17, wherein, The fifth horizontal height of the first uppermost surface of the upper buried insulating layer of the first insulating structure is located between the sixth horizontal height of the second uppermost surface of the upper buried insulating layer of the second insulating structure and the substrate.

20. The integrated circuit device according to claim 17, wherein, The buried insulating layer includes a silicon oxide layer containing nitrogen and / or fluorine.

Images