A bidirectional detection circuit for charging and discharging current

Abstract

A bidirectional detection circuit for charge and discharge current, comprising a detection isolation circuit and a clamping operational amplifier circuit, characterized in that: the detection isolation circuit is used to receive the positive and negative inputs of the battery current, and the battery voltage isolates the high-level side and the low-level side; the clamping operational amplifier circuit is used to receive the isolation voltage generated by the detection isolation circuit and output a sampling voltage; the bidirectional detection circuit for charge and discharge current further includes an offset cancellation circuit and a bidirectional detection circuit. Among them, the offset cancellation circuit is used to adjust the source-drain current of the first or second NMOS transistor input to the detection isolation circuit to eliminate the offset influence of the detection isolation circuit; the bidirectional detection circuit is used to control the circuit to detect the charge and discharge current based on the charge and discharge state. Based on the detection circuit in the present invention, bidirectional charge and discharge detection can be realized, and at the same time, isolation error can be eliminated.

Description

Technical Field

[0001] The present invention belongs to the field of charging control circuits, and particularly relates to a bidirectional detection circuit for charging and discharging currents. Background Art

[0002] With the progress of society and the continuous improvement of informatization and automation levels, people's dependence on the power industry has further deepened, and higher requirements have also been put forward for the reliability of the power supply system. A charging chip (Charge IC) is made of semiconductor devices and can control the charging and discharging processes of a battery. Currently, the detection of the real-time charging and discharging current magnitude of the battery is one of the key issues of the charging chip.

[0003] First of all, a current sampling circuit is needed to detect the charging and discharging currents of the battery to determine the real-time charging and discharging current magnitudes. After determining the real-time charging and discharging current magnitudes, corresponding loop and logic control circuits can be provided for the charging and discharging currents. When detecting the charging and discharging circuit of the battery, considering the common-mode input range and detection accuracy of the operational amplifier, the detection circuit often needs to be divided into a high-side part and a low-side part to detect the battery current when the battery voltage is relatively high and when the battery voltage is relatively low, respectively. However, in order to implement the technical solution for detecting the high-side and low-side circuits, isolation of the high-side and low-side circuits is required, so PMOS and NMOS field effect transistors are introduced into the circuit as switching transistors to achieve isolation, which leads to an offset problem when the detection circuit works.

[0004] Secondly, in the charging chip, the directions of the charging current and the discharging current are exactly opposite. During charging, the current passes through the current sampling resistor, and the generated voltage is a positive signal; during discharging, the current passes through the current sampling resistor, and the generated voltage is negative. Since bidirectional detection of the charging and discharging currents during the charging and discharging processes cannot be achieved, most current detection schemes are unidirectional current detections at present. The above problems will respectively reduce the detection accuracy and increase the circuit cost.

[0005] Therefore, there is an urgent need for a current detection method that can achieve bidirectional charging and discharging detection and eliminate isolation errors at the same time. Summary of the Invention

[0006] In order to solve the deficiencies existing in the prior art, the purpose of the present invention is to provide a sampling circuit for detecting the charging and discharging currents of a battery, which eliminates offset, improves accuracy, and can achieve bidirectional detection.

[0007] The present invention adopts the following technical solutions. A bidirectional detection circuit for charge and discharge current includes a detection isolation circuit and a clamping operational amplifier circuit. The detection isolation circuit is used to receive the positive and negative inputs of the battery current and isolate the high-level side and the low-level side by the battery voltage; the clamping operational amplifier circuit is used to receive the isolation voltage generated by the detection isolation circuit and output a sampling voltage; the bidirectional detection circuit for charge and discharge current further includes an offset cancellation circuit and a bidirectional detection circuit. Among them, the offset cancellation circuit is used to adjust the source-drain current of the first or second NMOS transistor input to the detection isolation circuit to eliminate the offset influence of the detection isolation circuit; the bidirectional detection circuit is used to detect the charge and discharge current based on the charge and discharge state control circuit.

[0008] Preferably, the offset cancellation circuit includes a drain connection unit and a source connection unit; and the drain connection unit is connected to the drain of the first or second NMOS transistor in the detection isolation circuit and is used to extract the current of the first or second NMOS transistor in the detection isolation circuit based on the charge and discharge current; the source connection unit is connected to the source of the first or second NMOS transistor in the detection isolation circuit and is used to inject current into the first or second NMOS transistor in the detection isolation circuit based on the sampling voltage generated by the clamping operational amplifier circuit.

[0009] Preferably, the drain connection unit includes PMOS transistor MC3, NMOS transistors MC5 and MC6, and the gate of MC3 is connected to the gate of MC1 in the clamping operational amplifier circuit, the source is connected to the power supply voltage, the drain is connected to the drain and the gate of MC5, the source of MC5 is grounded, the gate is connected to the gate of MC6, the drain of MC6 is connected to the drain of the first or second NMOS transistor in the detection isolation circuit, and the source is grounded.

[0010] Preferably, the source connection unit includes PMOS transistor MC2, the gate of MC2 is connected to the gate of MC1 in the clamping operational amplifier circuit, the source is connected to the power supply voltage, and the drain is connected to the source of the first NMOS transistor in the detection isolation circuit.

[0011] Preferably, the detection isolation circuit includes NMOS transistors MS1, MS2, MS3, MS4, detection resistors R P 、R N , ESD resistors R 3 and R 4 , sampling resistor R SR , and one end of the detection resistor R P is connected to SRP to receive the positive input of the battery current, the other end is connected to the drain of NMOS transistor MS1, the source of MS1 is connected to the source of the said MS3, the drain of transistor MS3 is grounded through an ESD resistor R 3 ; one end of the detection resistor R NOne end is connected to the SRN to receive the negative input of the battery current, and the other end is connected to the drain of MS2. The source of MS2 is connected to the source of MS4, and the drain of MS4 is grounded through an ESD resistor R 3 ; The gates of transistors MS1, MS2, MS3, and MS4 are respectively connected to the enable signal EN_LS; The sampling resistor R SR One end is connected to the detection resistor R P and SRP, and the other end is connected to the detection resistor R N and SRN.

[0012] Preferably, the detection isolation circuit further includes a high-level detection unit; And, the high-level detection unit includes an operational amplifier OP_CLAMP, an adjustment transistor MR2, and a switching transistor MS5; The positive and negative input terminals of the operational amplifier OP_CLAMP are respectively connected to the other ends of the detection resistors R P , R N in the detection isolation circuit, that is, connected to the points SRPs and SRNs in the circuit, and the output terminal is connected to the gate of the adjustment transistor MR2; The adjustment transistor MR2 is a PMOS transistor, and the switching transistor MS5 is an NMOS transistor; The source of the adjustment transistor MR2 is respectively connected to the other ends of the detection resistors R P , R N in the circuit through switches SP and SN, that is, connected to the points SRPs and SRNs in the circuit, and the drain is connected to the drain of the switching transistor MS5; The gate of the switching transistor MS5 is connected to the enable signal EN_LS, and the source is connected to the module total output V O connection.

[0013] Preferably, when the detection circuit detects that the voltage at the SRP or SRN point in the circuit is lower than the input threshold, the output of the enable signal EN_LS is high level, and the connection between the high-level detection unit and the module total output V O is truncated; When the detection circuit detects that the voltage at the SRP or SRN point in the circuit is higher than the input threshold, the output of the enable signal EN_LS is low level, and the high-level detection unit is connected to the module total output V O connected.

[0014] Preferably, the output terminal MC1 of the clamping operational amplifier circuit Clamp receives the input current from the PMOS transistor MC4 in the current source circuit; The emitter of the first input terminal Q1 and the source of MR1 feedback the source-drain current to the second NMOS transistor MS2 or the fourth PMOS transistor MS4; The emitter of the second input terminal Q2 feedbacks the source-drain current to the first NMOS transistor MS1 or the third PMOS transistor MS3.

[0015] Preferably, the bidirectional detection circuit includes first and second positive switches SP, and first and second negative switches SN; moreover, one end of the first positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the first negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the source electrode of MR2; one end of the second positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the second negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the drain electrode of the NMOS transistor MC6 in the offset cancellation circuit; when the input direction of the battery current received by the detection circuit is switched, the polarity of the operational amplifier OP_CLAMP is reversed.

[0016] Preferably, the current source circuit includes a switching transistor MC4, a switching transistor MC7, the source electrode of the switching transistor MC4 is connected to the power supply voltage VDD, the drain electrode is connected to the module total output V O is connected, and the source electrode is connected to the clamping operational amplifier unit.

[0017] The beneficial effects of the present invention are that, compared with the prior art, in the present invention, a charge and discharge current bidirectional detection circuit can not only detect the charge and discharge current of a charging chip through a current sampling circuit to eliminate offset, but also realize bidirectional current detection to determine the real-time magnitude of the charge and discharge current, thereby improving the detection accuracy.

[0018] The beneficial effects of the present invention at least include:

[0019] 1. Inject current at one end of the switching transistor MS1 and extract it at the other end, so that the voltage drops at both ends of MS1 and MS2 are equal, thereby eliminating isolation interference;

[0020] 2. Realize bidirectional detection of the charge and discharge current by adding a selection switch. Description of the Drawings

[0021] Figure 1 is a module schematic diagram of a charge and discharge current bidirectional detection circuit of the present invention;

[0022] Figure 2 is a schematic diagram of an offset cancellation circuit in a charge and discharge current bidirectional detection circuit of the present invention;

[0023] Figure 3 is a schematic diagram of a detection isolation circuit in a charge and discharge current bidirectional detection circuit of the present invention;

[0024] Figure 4 is a schematic diagram of a high-level detection unit in a detection isolation circuit of a charge and discharge current bidirectional detection circuit of the present invention;

[0025] Figure 5 is a schematic diagram of a clamping operational amplifier circuit in a charge and discharge current bidirectional detection circuit of the present invention;

[0026] Figure 6 Schematic diagram of the current source circuit in a bidirectional charge and discharge current detection circuit of the present invention;

[0027] Figure 7 Schematic diagram of the overall circuit in a bidirectional charge and discharge current detection circuit of the present invention. Specific embodiments

[0028] The following further describes the present application with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present application.

[0029] Figure 1 Module schematic diagram of a bidirectional charge and discharge current detection circuit of the present invention. As Figure 1 shown, a bidirectional charge and discharge current detection circuit includes a detection isolation circuit and a clamping operational amplifier circuit, characterized in that: the detection isolation circuit is used to receive the positive and negative inputs of the battery current and isolate the high-level side and the low-level side based on the battery voltage; the clamping operational amplifier circuit is used to receive the isolation voltage generated by the detection isolation circuit and output a sampling voltage; the bidirectional charge and discharge current detection circuit further includes an offset cancellation circuit and a bidirectional detection circuit, wherein the offset cancellation circuit is used to adjust the source-drain current of the first or second NMOS transistor input to the detection isolation circuit to eliminate the offset influence of the detection isolation circuit, and the bidirectional detection circuit is used to control the circuit to detect the charge and discharge current based on the charge and discharge state.

[0030] Figure 2 Schematic diagram of the offset cancellation circuit in a bidirectional charge and discharge current detection circuit of the present invention. As Figure 2 shown, preferably, the offset cancellation circuit includes a drain connection unit and a source connection unit; and the drain connection unit is connected to the drain of the first or second NMOS transistor in the detection isolation circuit and is used to extract the current of the first or second NMOS transistor in the detection isolation circuit based on the charge and discharge current; the source connection unit is connected to the source of the first or second NMOS transistor in the detection isolation circuit and is used to inject current into the first or second NMOS transistor in the detection isolation circuit based on the sampling voltage generated by the clamping operational amplifier circuit.

[0031] Preferably, the drain connection unit includes PMOS transistor MC3, NMOS transistors MC5 and MC6, and the gate of MC3 is connected to the gate of MC1 in the clamping operational amplifier circuit, the source is connected to the power supply voltage, the drain is connected to the drain and gate of MC5, the source of MC5 is grounded, the gate is connected to the gate of MC6, the drain of MC6 is connected to the drain of the first or second NMOS transistor in the detection isolation circuit, and the source is grounded.

[0032] In addition, the source connection unit includes a PMOS transistor MC2. The gate of MC2 is connected to the gate of MC1 in the clamping operational amplifier circuit. The source is connected to the power supply voltage, and the drain is connected to the source of the first NMOS transistor in the detection isolation circuit.

[0033] It can be understood that when the positive and negative inputs of the battery current are input from the SRP or SRN points in the circuit, the switches SP and SN will be turned on, and the clamping operational amplifier makes the potentials of the emitters of the two transistors Q1 and Q2 equal. Assume that at this time, the transistors MS1 and MS2 in the circuit are conducting, and the transistors MS3 and MS4 are cut off, and the circuit is in the detection state of the low-side current. Since the source-drain current of MC2 in the source connection unit is injected into the source of MS1, the output currents of the emitters of the two transistors Q1 and Q2 output to the sources of MS1 and MS2 are equal, and further the voltage drops of MS1 and MS2 are equal, eliminating the offset caused by isolation.

[0034] At the same time, MC6 in the drain connection unit is connected to the drain of MS1 or MS2, and the positive feedback current injected into MS1 by MC2 is completely extracted at the drain end of MS1, which makes the new branch have no impact on the stability of the loop.

[0035] Figure 3 It is a schematic diagram of the detection isolation circuit in a bidirectional detection circuit for charging and discharging currents according to the present invention. As Figure 3 shown, preferably, the detection isolation circuit includes MOS transistors MS1, MS2, MS3, MS4, detection resistors R P , R N , ESD resistors R 3 and R 4 , a sampling resistor R SR , and, one end of the detection resistor R P is connected to SRP to receive the positive input of the battery current, and the other end is connected to the drain of MS1. The source of MS1 is connected to the source of the said MS3, and the drain of MS3 is grounded through an ESD resistor R 3 ; one end of the detection resistor R N is connected to SRN to receive the positive input of the battery current, and the other end is connected to the drain of MS2. The source of MS2 is connected to the source of MS4, and the drain of MS4 is grounded through an ESD resistor R 3 ; the gates of MS1, MS2, MS3, and MS4 are respectively connected to the enable signal EN_LS; one end of the sampling resistor R SR is connected to the detection resistor R P and SRP, and the other end is connected to the detection resistor R N and SRN. Among them, the ESD resistor is an Electro-Static Discharge Resistor for grounding.

[0036] Figure 4 This is a schematic diagram of the high - level detection unit in the detection isolation circuit of a charge - discharge current bidirectional detection circuit for the present invention. As Figure 4 shown, preferably, the detection isolation circuit further includes a high - level detection unit. And, the high - level detection unit includes an operational amplifier OP_CLAMP, an adjustment transistor MR2, and a switching transistor MS5; the positive and negative input terminals of the operational amplifier OP_CLAMP are respectively connected to the other ends of the detection resistors R P 、R N in the detection isolation circuit, that is, connected to the points SRPs and SRNs in the circuit, and the output terminal is connected to the gate of the adjustment transistor MR2; the adjustment transistor MR2 is a PMOS transistor, and the switching transistor MS5 is an NMOS transistor; the source of the adjustment transistor MR2 is respectively connected to the other ends of the detection resistors R P 、R N in the circuit through switches SP and SN, that is, connected to the points SRPs and SRNs in the circuit, the drain is connected to the drain of the switching transistor MS5; the gate of the switching transistor MS5 is connected to the enable signal EN_LS, and the source is connected to the module total output V O .

[0037] Preferably, when the detection circuit detects that the voltage at the SRP or SRN point in the circuit is lower than the input threshold, the output of the enable signal EN_LS is at a high level, and the connection between the high - level detection unit and the module total output V O is cut off; when the detection circuit detects that the voltage at the SRP or SRN point in the circuit is higher than the input threshold, the output of the enable signal EN_LS is at a low level, and the high - level detection unit is connected to the module total output V O .

[0038] Specifically, the detection circuit determines whether it is in the high - level detection state or the low - level detection state according to the voltage magnitude at the SRP or SRN point at the input end of the circuit. Usually, an input threshold can be set. When the SRP and SRN voltages are low and less than this input threshold, the external enable signal EN_LS gives a high level. Since the enable signal EN_LS is respectively connected to the gates of the first to fourth MOS transistors MS1 to MS4 and is also connected to the gate of the switching transistor MS5 through a converter. Therefore, when the input of the enable signal EN_LS is at a high level, the PMOS transistors MS3 and MS4, and the NMOS transistor MS5 are cut off, and the NMOS transistors MS1 and MS2 are turned on. It can be seen that at this time, the upper half part of the detection isolation circuit, that is, Figure 3 is turned on and connected to the clamping operational amplifier unit. Figure 3 The lower half part in O is cut off. In addition, the high - level detection unit in the detection isolation circuit is cut off due to the cut - off of the switching transistor MS5 and cannot be connected to the module total output V O to affect the measurement result.

[0039] On the other hand, when the input SRP and SRN voltages are high and greater than the input threshold, the external enable signal EN_LS will be given a low level. At this time, PMOS transistors MS3 and MS4, and NMOS transistor MS5 are turned on, and NMOS transistors MS1 and MS2 are turned off. Due to the conduction of NMOS transistor MS5, the high-level detection unit is connected to the module total output V O connected. Since MS1 and MS2 are turned off, the sampling resistor R SR is isolated from PMOS transistors MS3 and MS4 and the clamping operational amplifier circuit. The clamping operational amplifier receives the feedback from the high-level detection unit and outputs the feedback current from transistors Q 1 and Q 2 to MS3 and MS4.

[0040] Figure 5 is a schematic diagram of the clamping operational amplifier circuit in a charge and discharge current bidirectional detection circuit of the present invention. As Figure 5 shown, preferably, the output terminal MC1 of the clamping operational amplifier circuit Clamp receives the input current from PMOS transistor MC4 in the current source circuit; the emitter of the first input terminal Q 1 feeds the source-drain current back to the second NMOS transistor MS2 or the fourth PMOS transistor MS4; the emitter of the second input terminal Q 2 feeds the source-drain current back to the first NMOS transistor MS1 or the third PMOS transistor MS3.

[0041] Preferably, the detection circuit further includes a bidirectional detection circuit. The bidirectional detection circuit includes first and second positive switches SP, and first and second negative switches SN; and, one end of the first positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the first negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the source of MR2; one end of the second positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the second negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the drain of NMOS transistor MC6 in the offset cancellation circuit; when the detection circuit receives the switching of the input direction of the battery current, the polarity of the operational amplifier OP_CLAMP is reversed. Figure 6 is a schematic diagram of the current source circuit in a charge and discharge current bidirectional detection circuit of the present invention. As Figure 6 shown, the current source circuit includes switch transistors MC4 and MC7. The source of the switch transistor MC4 is connected to the power supply voltage VDD, the drain is connected to the module total output V O connected, and the source is connected to the clamping operational amplifier unit. In an embodiment of the present invention, some PMOS transistors and NMOS transistors can be set in a double-transistor series connection. For example, MC2, MC3, MC4, MC5, MC6.

[0042] Figure 7 This is a schematic diagram of the overall circuit in a bidirectional detection circuit for charge and discharge current of the present invention. As Figure 7 shown, specifically, when the circuit operates in the low-side current detection state, the positive and negative inputs of the battery current can be detected simultaneously. Assume that the input at this time is the positive input current I SRP . The switch SN is turned off and SP is turned on. The positive feedback current injected into MS1 by MC2 is completely extracted by MC6 at the drain of MS1. Since the voltage drops of MS1 and MS2 are the same, the potentials of SRPs and SRNs are the same. Therefore, according to the equality of voltages, the formula SRP + R P I Q2 = SRN + R N (I Q1 + I MR1 ) is established.

[0043] Among them, the resistances of R N and R P are taken to be equal, denoted as R N.P . The bias currents of Q 1 and Q 2 are taken to be equal. Then there is SRP - SRN = R N.P I MR1 . At the same time, according to the connection relationship of the circuit, it can be known that the two ends of the resistor R SR are respectively connected to SRP and SRN. Then there is R N.P I MR1 = R SR I SRP . And, since MR1 and MC1 are connected in series on a branch, and MC1 and MC4 are mirror-connected, therefore there is I MR1 = I MC1 = I MC4 = I O , where I O is the output terminal current, and it can be obtained that That is Therefore, the sampling result of the output voltage is

[0044] As can be seen from the above formula, this scheme eliminates the error brought by the on-resistances of NMOS transistors MS1 and MS2 to the sampling result. At the same time, by adjusting the mirror ratio K (K < 1) of MC1 and MC3, the additional power consumption brought by the offset cancellation circuit can be reduced to a certain extent.

[0045] When the input is the negative input current I SRN , the switch SP is turned off and SN is turned on. MC6 changes from extracting the current of MS1 to extracting the current of MS2.

[0046] When the input terminals SRP and SRN are at a high level, the high-level detection unit is turned on. Since OP_CLAMP clamps SRPs and SRNs to be equal and R P = R N , the sampling result of the output voltage is also

[0047] When the positive and negative directions of the detected input current change, the switch state changes, and at the same time, the polarity of the operational amplifier OP_CLAMP is reversed.

[0048] The beneficial effects of the present invention are that, compared with the prior art, in the present invention, a bidirectional detection circuit for charging and discharging current can not only detect the charging and discharging current of the charging chip through the current sampling circuit to eliminate offset, but also realize bidirectional current detection to determine the real-time magnitude of the charging and discharging current, thereby improving the detection accuracy.

[0049] The beneficial effects of the present invention at least include:

[0050] 1. Inject current at one end of the switch tube MS1 and draw it out at the other end, so that the voltage drops at both ends of MS1 and MS2

[0051] are equal, thereby eliminating isolation interference;

[0052] 2. By adding a selection switch, bidirectional detection of the charging and discharging current is realized.

[0053] The applicant of the present invention has made a detailed description and illustration of the embodiments of the present invention in combination with the accompanying drawings of the specification. However, those skilled in the art should understand that the above embodiments are only the preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. A bidirectional detection circuit for charge and discharge current, comprising a detection isolation circuit and a clamping operational amplifier circuit, characterized in that: The detection isolation circuit is used to receive the positive and negative inputs of the battery current, and the battery voltage isolates the high-level side and the low-level side; the clamping operational amplifier circuit is used to receive the isolation voltage generated by the detection isolation circuit and output a sampling voltage; The bidirectional detection circuit for charge and discharge current further includes an offset cancellation circuit and a bidirectional detection circuit, wherein, the offset cancellation circuit is used to adjust the source-drain current of the first or second NMOS transistor input to the detection isolation circuit to eliminate the offset effect of the detection isolation circuit; the offset cancellation circuit includes a drain connection unit and a source connection unit; the drain connection unit is connected to the drain of the first or second NMOS transistor in the detection isolation circuit, and is used to extract the current of the first or second NMOS transistor in the detection isolation circuit based on the charge and discharge current; the source connection unit is connected to the source of the first or second NMOS transistor in the detection isolation circuit, and is used to inject current into the first or second NMOS transistor in the detection isolation circuit based on the sampling voltage generated by the clamping operational amplifier circuit; The drain connection unit includes a PMOS transistor MC3, an NMOS transistor MC5 and an NMOS transistor MC6, and the gate of the PMOS transistor MC3 is connected to the gate of MC1 in the clamping operational amplifier circuit, the source is connected to the power supply voltage, the drain is connected to the drain and the gate of the NMOS transistor MC5, the source of the NMOS transistor MC5 is grounded, the gate is connected to the gate of the NMOS transistor MC6, the drain of the NMOS transistor MC6 is connected to the drain of the first or second NMOS transistor in the detection isolation circuit, and the source is grounded; The source connection unit includes a PMOS transistor MC2, the gate of the PMOS transistor MC2 is connected to the gate of MC1 in the clamping operational amplifier circuit, the source is connected to the power supply voltage, and the drain is connected to the source of the first NMOS transistor in the detection isolation circuit; The bidirectional detection circuit is used to control the circuit to detect the charge and discharge current based on the charge and discharge state.

2. A bidirectional detection circuit for charge and discharge current according to claim 1, characterized in that: The detection isolation circuit includes NMOS transistor MS1, NMOS transistor MS2, PMOS transistor MS3, PMOS transistor MS4, detection resistor R P , detection resistor R N , ESD resistor R 3 and ESD resistor R 4 , sampling resistor R SR , and The detection resistor R P One end is connected to the SRP to receive the positive input of the battery current, and the other end is connected to the drain of the NMOS transistor MS1. The source of the NMOS transistor MS1 is connected to the source of the PMOS transistor MS3. The drain of the PMOS transistor MS3 is grounded through the ESD resistor R 3 subsequently; The detection resistor R N One end is connected to SRN to receive the negative input of the battery current, and the other end is connected to the drain of the NMOS transistor MS2. The source of the NMOS transistor MS2 is connected to the source of the PMOS transistor MS4. The drain of the PMOS transistor MS4 is grounded through the ESD resistor R 4 afterwards; The gates of the NMOS transistor MS1, the NMOS transistor MS2, the PMOS transistor MS3, and the PMOS transistor MS4 are respectively connected to the enable signal EN_LS; The sampling resistor R SR has one end connected to the detection resistor R P and SRP, and the other end connected to the detection resistor R N and SRN.

3. A bidirectional detection circuit for charge and discharge current according to claim 2, characterized in that: The detection isolation circuit further includes a high-level detection unit; and, The high-level detection unit includes an operational amplifier OP_CLAMP, an adjustment transistor MR2, and a switching transistor MS5; The positive and negative input terminals of the operational amplifier OP_CLAMP are respectively connected to the other ends of the detection resistors R P , R N in the detection isolation circuit, that is, connected to the points SRPs and SRNs in the circuit, and the output terminal is connected to the gate of the adjustment transistor MR2; The adjustment transistor MR2 is a PMOS transistor, and the switching transistor MS5 is an NMOS transistor; The source of the adjustment transistor MR2 is respectively connected to the detection resistors R through switches SP and SN P , the detection resistor R N at the other end, that is, connected to the points SRPs and SRNs in the circuit, and the drain is connected to the drain of the switching transistor MS5; The gate of the switching transistor MS5 is connected to the enabling signal EN_LS, and the source is connected to the overall output V of the module. O Connection.

4. A bidirectional detection circuit for charge and discharge current according to claim 3, characterized in that: When the detection circuit detects that the voltage at the SRP or SRN point of the circuit is lower than the input threshold, the output of the enable signal EN_LS is at a high level, and the connection between the high-level detection unit and the module total output V O is truncated; When the detection circuit detects that the voltage at the SRP or SRN point of the circuit is higher than the input threshold, the output of the enable signal EN_LS is at a low level, and the high-level detection unit is O connected.

5. A bidirectional detection circuit for charge and discharge current according to claim 3 or 4, characterized in that: The output terminal MC1 of the Clamp operational amplifier circuit receives the input current from the PMOS transistor MC4 in the current source circuit; The emitter of the first input terminal Q1 and the source of MR1 feedback the source-drain current to the NMOS transistor MS2 or the PMOS transistor MS4; The emitter of the second input terminal Q2 feedbacks the source-drain current to the NMOS transistor MS1 or the PMOS transistor MS3.

6. A bidirectional detection circuit for charging and discharging current according to claim 5, characterized in that: The bidirectional detection circuit includes first and second positive switches SP, and first and second negative switches SN; and, One end of the first positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the first negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the source of MR2; One end of the second positive switch SP is connected to the SRPs point in the detection isolation circuit, one end of the second negative switch SN is connected to the SRNs point in the detection isolation circuit, and the other ends are both connected to the drain of the NMOS transistor MC6 in the offset cancellation circuit; When the input direction of the battery current received by the detection circuit is switched, the polarity of the operational amplifier OP_CLAMP is reversed.

7. A bidirectional detection circuit for charging and discharging current according to claim 5, characterized in that: The current source circuit includes a PMOS transistor MC4 and a switching transistor MC7. The source of the PMOS transistor MC4 is connected to the power supply voltage VDD, the drain is connected to the module total output V O connection, and the source is connected to the clamping operational amplifier unit.

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