Control circuit and control method for three-level dc-dc converter

Abstract

Disclosed is a three-level DC-DC converter. The embodiment of the application stabilizes the voltage value of the flying capacitor at a preset value by adjusting the phase difference between the first power tube and the second power tube in the three-level DC-DC converter and the duty cycle of each power tube, wherein the duty cycle variation is proportional to the phase difference variation. The scheme is effective in any load condition, which improves the efficiency and stability of the circuit.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and more specifically, to a control circuit and control method for a three-level DC-DC converter. Background Technology

[0002] The three-level DC-DC converters used in existing technologies, such as Figure 1 The diagram shows a three-level Buck converter, comprising power transistors S1-S4, a flying capacitor Cf, an inductor L, and an output capacitor Co. The drive signals G for power transistors S1 and S4 are... S1 and G S4 Complementary, the drive signals G of power transistors S2 and S3 S2 and G S3 Complementary. Furthermore, the drive signals G for power transistors S1 and S2... S1 and G S2 The duty cycles are equal, and the drive signals G of power transistors S1 and S2 are equal. S1 and G S2 The phase difference α is 180° (π radians).

[0003] Ideally, a three-level Buck converter operates with the flying capacitor voltage (Vcf) equal to 1 / 2 Vin. In this state, the switching transistors of the three-level Buck converter withstand half the voltage of Vin, and the inductor current exhibits a frequency multiplication effect. In reality, due to component tolerances and parasitic circuit parameters, the flying capacitor voltage (Vcf) can become unbalanced, disrupting the optimal operating condition of the three-level Buck converter. Therefore, voltage equalization strategies such as phase-shift control are needed to balance the flying capacitor voltage and ensure it remains at 1 / 2 Vin. However, under adverse conditions such as rapid input voltage changes or sudden load shifts, the instantaneous value of the flying capacitor voltage can deviate significantly from 1 / 2 Vin, rendering conventional voltage equalization strategies ineffective. Therefore, rapid and effective adjustment of the flying capacitor voltage under adverse conditions is required. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a control circuit and control method for a three-level DC-DC converter, which overcomes the shortcomings of conventional voltage equalization strategies in that they cannot balance the voltage of the flying capacitor in a timely manner under extreme operating conditions, and achieves rapid and effective regulation of the voltage of the flying capacitor.

[0005] According to a first aspect of the present invention, a control method for adjusting the capacitor voltage in a three-level DC-DC converter is provided, wherein the three-level DC-DC converter includes first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between a common node of the first and second power transistors and a common node of the third and fourth power transistors, the control method comprising:

[0006] When the voltage value of the flying capacitor is outside the first threshold range, the flying capacitor is controlled to enter the charging stage multiple times to continuously charge, or to enter the discharging stage multiple times to continuously discharge, so that the voltage value of the flying capacitor approaches the preset value.

[0007] Specifically, there is at least one holding phase between two adjacent charging phases and between two adjacent discharging phases, wherein the voltage of the flying capacitor is controlled to remain constant during the holding phase.

[0008] Specifically, the control method further includes:

[0009] When the voltage value of the flying capacitor approaches the preset value from outside the first threshold range, the three-level DC-DC converter is controlled to enter the normal operation mode, so that the charging phase and the discharging phase alternate in each switching cycle.

[0010] Specifically, the control method further includes:

[0011] When the voltage value of the flying capacitor is less than the lower limit of the first threshold range, the three-level DC-DC converter is controlled to enter the undervoltage operating mode so that the flying capacitor enters the charging stage multiple times in a row.

[0012] When the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, the three-level DC-DC converter is controlled to enter the overvoltage working mode so that the flying capacitor enters the discharge stage multiple times in a row.

[0013] Specifically, during continuous charging of the flying capacitor in the undervoltage operating mode, the flying capacitor is controlled to enter at least one discharge phase; during continuous discharging of the flying capacitor in the overvoltage operating mode, the flying capacitor is controlled to enter at least one charging phase.

[0014] Specifically, the control method further includes:

[0015] In the undervoltage operating mode, after every N charging stages, the flying capacitor is controlled to enter the discharge supplement mode to perform at least one discharge; in the overvoltage operating mode, after every N discharge stages, the flying capacitor is controlled to enter the charge supplement mode to perform at least one charge, thereby increasing the voltage of the drive power supply capacitor in the drive circuit of the three-level DC-DC converter, where N is a positive integer greater than 1.

[0016] Specifically, the control method further includes:

[0017] In the discharge replenishment mode, the flying capacitor is controlled to enter a discharge phase and then return to the undervoltage operating mode, or it enters the normal operating mode for a short period and then returns to the undervoltage operating mode; or

[0018] In the charging replenishment mode, the flying capacitor is controlled to enter the first charging stage and then return to the overvoltage working mode, or it enters the normal working mode and then returns to the overvoltage working mode immediately.

[0019] Specifically, the time interval between the start position of the previous charging stage and the start position of the next charging stage in the N charging stages is the charging interval time, and the time interval between the start position of the previous discharging stage and the start position of the next discharging stage in the N discharging stages is the discharging interval time. The length of the charging interval time and the discharging interval time is an integer multiple of 1 / 2 switching cycle.

[0020] Specifically, when D is less than 0.5, the charging interval includes a charging phase with a duration of D×Ts, and the rest are holding phases; the discharging interval includes a discharging phase with a duration of D×Ts, and the rest are holding phases. When D is greater than 0.5, the charging interval includes a charging phase with a duration of Ts×(1-D), and the rest are holding phases; the discharging interval includes a discharging phase with a duration of Ts×(1-D), and the rest are holding phases, where Ts is the switching cycle and D is the duty cycle of the first power transistor.

[0021] Specifically, when the duty cycle is less than 0.5, in each charging interval of the undervoltage operating mode, the first power transistor is controlled to turn on once, and the on-time is the product of the duty cycle and the switching cycle, while the second power transistor is not turned on; in each discharging interval of the overvoltage operating mode, the second power transistor is controlled to turn on once, and the on-time is the product of the duty cycle and the switching cycle, while the first power transistor is not turned on, wherein the drive signals of the first power transistor and the fourth power transistor are complementary, and the drive signals of the second power transistor and the third power transistor are complementary.

[0022] Specifically, when the duty cycle is greater than 0.5, in each charging interval of the undervoltage operating mode, the third power transistor is controlled to turn on once, and the on-time is the product of (1-D) and the switching cycle, while the fourth power transistor is not turned on; in each discharging interval of the overvoltage operating mode, the fourth power transistor is controlled to turn on once, and the on-time is the product of (1-D) and the switching cycle, while the third power transistor is not turned on. The drive signals of the first power transistor and the fourth power transistor are complementary, and the drive signals of the second power transistor and the third power transistor are complementary, where D is the duty cycle of the first power transistor.

[0023] Specifically, the control method further includes:

[0024] When in the normal operating mode, the voltage value of the flying capacitor is controlled to be equal to the preset value.

[0025] According to a second aspect of the invention, a control circuit for a three-level DC-DC converter is provided, wherein the three-level DC-DC converter includes first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between the common node of the first and second power transistors and the common node of the third and fourth power transistors, the control circuit being configured to:

[0026] When the voltage value of the flying capacitor is outside the first threshold range, the flying capacitor is controlled to enter the charging stage multiple times to continuously charge, or to enter the discharging stage multiple times to continuously discharge, so that the voltage value of the flying capacitor approaches the preset value.

[0027] Specifically, the control circuit includes:

[0028] The mode switching module is configured to receive the voltage value of the flying capacitor and output different indication signals according to the degree to which the voltage value of the flying capacitor deviates from the preset value to control the three-level DC-DC converter to switch between different operating modes.

[0029] The feedback compensation circuit is configured to generate a feedback compensation signal based on the error between a feedback signal characterizing the output voltage and a reference signal characterizing the desired value of the output voltage; and

[0030] The drive generation circuit is configured to generate a corresponding drive signal based on the feedback compensation signal and the indication signal, thereby controlling the three-level DC-DC converter to operate in the corresponding operating mode.

[0031] Specifically, the mode switching module is configured as follows:

[0032] When the voltage value of the flying capacitor is less than the lower limit of the first threshold range, an effective undervoltage indication signal is output to indicate that the three-level DC-DC converter enters the undervoltage operating mode, so that the flying capacitor enters the charging stage multiple times in a row.

[0033] When the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, an effective overvoltage indication signal is output to indicate that the three-level DC-DC converter enters the overvoltage operating mode, so that the flying capacitor enters the discharge stage multiple times in a row.

[0034] Specifically, there is at least one holding phase between two adjacent charging phases and between two adjacent discharging phases, wherein the voltage value of the flying capacitor is controlled to remain constant during the holding phase.

[0035] Specifically, when the voltage value of the flying capacitor approaches the preset value from outside the first threshold range, the mode switching module is configured to output a valid normal indication signal to indicate that the three-level DC-DC converter enters the normal operation mode, thereby alternating the charging phase and the discharging phase in each switching cycle.

[0036] Specifically, the drive generation circuit includes:

[0037] A first drive generation circuit is configured to generate a first control signal based on the feedback compensation signal and a first sawtooth wave signal, and to generate a second control signal based on the feedback compensation signal and a second sawtooth wave signal; and

[0038] The second drive generation circuit is configured to generate corresponding drive signals based on the received first and second control signals and various indication signals.

[0039] Specifically, the control circuit is further configured to control the flying capacitor to enter a discharge replenishment mode to perform at least one discharge after every N charging stages; or to control the flying capacitor to enter a charge replenishment mode to perform at least one charge after every N discharge stages, thereby increasing the voltage of the drive power supply capacitor in the drive circuit of the three-level DC-DC converter, where N is a positive integer greater than 1.

[0040] Specifically, the control circuit is further configured to, in the discharge replenishment mode, control the flying capacitor to enter a discharge phase and then return to the undervoltage operating mode, or enter the normal operating mode for a short period and then return to the undervoltage operating mode; or

[0041] In the charging replenishment mode, the flying capacitor is controlled to enter the first charging stage and then return to the overvoltage working mode, or it enters the normal working mode and then returns to the overvoltage working mode immediately.

[0042] Specifically, the time between the start position of the previous charging stage and the start position of the next charging stage in the N charging stages is the charging interval time, and the time between the start position of the previous discharging stage and the start position of the next discharging stage in the N discharging stages is the discharging interval time. The length of the charging interval time and the discharging interval time is an integer multiple of 1 / 2 switching cycle.

[0043] In summary, the technical solution of this invention compensates for the shortcomings of conventional voltage equalization strategies in balancing the flying capacitor voltage in a timely manner under extreme conditions by adjusting the execution timing and number of executions of the charging and discharging phases in the operation of a three-level DC-DC converter, thereby achieving rapid and effective regulation of the flying capacitor voltage. Attached Figure Description

[0044] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0045] Figure 1 This is a circuit diagram of a prior art three-level DC-DC converter;

[0046] Figure 2 This is a waveform diagram of the operation of a three-level DC-DC converter in the prior art;

[0047] Figure 3 This is a schematic diagram of the drive circuit of a three-level DC-DC converter according to an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the control circuit of a three-level DC-DC converter according to an embodiment of the present invention;

[0049] Figure 5 This is the first control waveform diagram of the three-level DC-DC converter in this embodiment of the invention when D < 0.5;

[0050] Figure 6 This is the first control waveform diagram of the three-level DC-DC converter in this embodiment of the invention when D > 0.5;

[0051] Figure 7 This is a second control waveform diagram of the three-level DC-DC converter in an embodiment of the present invention when D < 0.5; and

[0052] Figure 8 This is a second control waveform diagram of the three-level DC-DC converter in an embodiment of the present invention when D > 0.5. Detailed Implementation

[0053] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0054] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0055] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0056] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0057] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] Figure 2 The operating waveforms of a three-level DC-DC converter in the prior art are shown, in which... Figure 2 (a) shows the operating waveforms of the three-level buck converter when the duty cycle D is less than 0.5. Figure 2 (b) shows the waveform diagram of the three-level buck converter when the duty cycle D is greater than 0.5. For example... Figure 2 As shown in (a), when the duty cycle D is less than 0.5, one switching cycle Ts includes four operating stages: ①~④. Stage ① (charging stage): Power transistors S1 and S3 are turned on, the input voltage Vin charges the flying capacitor Cf, and the inductor current I... L Rise. Stage ② (Holding Stage): Power transistors S3 and S4 are turned on, and the inductor current I... L As the freewheeling current decreases through power transistors S3 and S4, the voltage across the flying capacitor Cf remains constant. Stage ③ (Discharge Stage): Power transistors S2 and S4 are turned on, the flying capacitor Cf begins to discharge, and the inductor current I... L Rise. Stage ④ (Holding Stage): Same as Stage ②, power transistors S3 and S4 are turned on, and the inductor current I... L Continuous flow. The time for stage ① plus stage ② is Ts / 2, and the time for stage ③ plus stage ④ is Ts / 2, where Ts is the switching cycle.

[0059] like Figure 2As shown in (b), when the duty cycle D is greater than 0.5, one switching cycle Ts includes four operating stages: ①~④. Stage ① (Holding stage): Power transistors S1 and S2 are turned on, the input voltage Vin stores energy in inductor L, and the inductor current I... L As the voltage rises, the voltage across the flying capacitor Cf remains constant. Stage ② (Charging Stage): Power transistors S1 and S3 are turned on, and the input voltage Vin and inductor L together charge the flying capacitor Cf, with the inductor current I... L The process begins with a decrease in power transistors. Phase ③ (Holding Phase): Power transistors S1 and S2 are turned on, the same as in Phase ①. Phase ④ (Discharge Phase): Power transistors S2 and S4 are turned on, the flying capacitor Cf discharges, and simultaneously the inductor L releases energy to the load, increasing the inductor current I. L The process is a decrease. The time for stage ① plus stage ② is Ts / 2, and the time for stage ③ plus stage ④ is Ts / 2, where Ts is the switching period.

[0060] In summary, within one switching cycle Ts, the operation of a three-level Buck converter includes a charging phase and a discharging phase. Furthermore, to maintain inductance balance, a holding phase follows the end of both the charging and discharging phases. Therefore, within one switching cycle Ts, the charging phase and the holding phase constitute one charging process with a time of Ts / 2, and the discharging phase and the holding phase constitute one discharging process with a time of Ts / 2.

[0061] When the voltage value Vcf of the flying capacitor deviates significantly from a preset value, this embodiment of the invention proposes a control method to quickly pull the voltage value Vcf back to the preset value (here, 1 / 2Vin). This control method adjusts the charging and discharging sequence and number of times of the flying capacitor Cf according to the degree to which the voltage value Vcf deviates from the preset value (1 / 2Vin), thereby making the voltage value Vcf approach the preset value. A first threshold range is set here, having an upper threshold much larger than the preset value and a lower threshold much smaller than the preset value. When the voltage value Vcf of the flying capacitor is outside the first threshold range, indicating that the voltage value Vcf deviates significantly from the preset value, the method controls the flying capacitor Cf to continuously enter the charging stage or continuously enter the discharging stage multiple times, thereby making the voltage value Vcf approach the preset value. Specifically, when the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, the flying capacitor Cf is controlled to enter the overvoltage working mode to continuously enter the discharge stage multiple times; when the voltage value of the flying capacitor is less than the lower limit of the first threshold range, the flying capacitor Cf is controlled to enter the undervoltage working mode to continuously enter the charging stage multiple times.

[0062] It should be understood that the purpose of the fast capacitor balancing strategy of the present invention is to quickly pull the voltage of the flying capacitor back to near the preset value (1 / 2Vin) when the voltage value Vcf of the flying capacitor is outside the first threshold range, that is, when it deviates significantly from the preset value (1 / 2Vin). Therefore, when the voltage of the flying capacitor approaches the preset value, the converter can return to normal operation. In each switching cycle, the charging phase and the discharging phase alternate, such as... Figure 2 As shown. Furthermore, in normal operating mode, the control circuit can execute other capacitor balancing strategies in the prior art, such as phase-shift control, to precisely control the voltage value Vcf of the flying capacitor Cf, thereby making the voltage value Vcf even equal to the preset value (1 / 2Vin).

[0063] Furthermore, the "continuous" mentioned above does not mean that one discharge stage immediately follows the next, but rather, as... Figure 2 As shown, there is at least one holding phase between two adjacent discharge phases, and the interval between the start position of the previous discharge phase and the start position of the next discharge phase is the discharge interval time Td, which is an integer multiple of Ts / 2, i.e., Td = mTs / 2, to satisfy the balance of the inductance, where m is a positive integer. One discharge interval time includes one discharge phase, and the rest are holding phases. When the duty cycle D < 0.5, the duration of the discharge phase is DTs, so the duration of the holding phase in each discharge interval time is mTs / 2 - DTs; if the duty cycle D > 0.5, the duration of the discharge phase is (1-D)Ts, so the duration of the holding phase in each discharge interval time is mTs / 2 - (1-D)Ts. Similarly, for multiple consecutive charging phases, the interval between the start position of the previous charging phase and the start position of the next charging phase is the charging interval time Tc, which is an integer multiple of Ts / 2, i.e., Tc = mTs / 2. One charging interval time includes one charging phase, and the rest are holding phases. When the duty cycle D < 0.5, the duration of the charging phase is DTs, so the duration of the holding phase in each charging interval is mTs / 2 - DTs; if the duty cycle D > 0.5, the duration of the charging phase is (1 - D)Ts, so the duration of the holding phase in each charging interval is mTs / 2 - (1 - D)Ts.

[0064] It should be understood that `m` determines the holding phase time, which is also related to the converter's speed and stability. If `m` is too large, the speed at which the flying capacitor reaches the preset value will decrease. Furthermore, when `D` < 0.5, the inductor freewheeling time will be too long, resulting in a significant decrease in inductor current and the circuit failing to operate normally. When `D` > 0.5, the inductor energy storage time will be too long, leading to a significant increase in inductor current, also affecting the normal operation of the circuit. If `m` is too small, it may cause instability in the converter's control. Therefore, the value of `m` needs to be selected based on the actual operating conditions.

[0065] However, because the drive circuit of a three-level Buck converter uses multiple drive power supply capacitors, and the voltage of these capacitors is related to the different switching states of the three-level Buck converter, after multiple discharges or charges, some drive power supply capacitors may not be able to replenish their energy, thus failing to drive the power transistors properly. The power supply principle of the drive circuit of a three-level Buck converter will be briefly analyzed below.

[0066] Figure 3 This is a schematic diagram of the drive circuit of a three-level DC-DC converter according to an embodiment of the present invention. For ease of description, Figure 3 Only the specific structure of the driving circuitry related to this invention is shown; other parts are omitted here. Figure 3 As shown, V gate This is the power transistor drive supply voltage, used to power the drive amplifier (not shown here) to output the drive signal; C B1 ~C B4 The driving power supply capacitors are used to supply power to the driver chip for generating the driving signal G. S1 -G S4 The corresponding driver module is powered. The power supply for the power transistor S4 is provided by capacitor C. B4 The power supply for driving power transistor S3 is provided by capacitor C. B3 Provided that when power transistor S4 is turned on, D3 is in the on state, V gate For capacitor C B3 Charging is performed so that when the turn-on signal for power transistor S3 arrives, a drive signal can be output to turn on power transistor S3. The drive power supply for power transistor S2 is provided by capacitor C. B2 Provided that when power transistor S3 is turned on, diode D2 is in the conducting state, and capacitor C... B3 Discharge to capacitor C B2 Charging is performed to prepare for the power transistor S2 to turn on. The power transistor S1 is powered by capacitor C. B1 Provided that when power transistor S2 is turned on, diode D1 is in the conducting state, and capacitor C... B2 Discharge to capacitor C B1Charging is performed to prepare for the power transistor S1 to turn on. It should be understood that, under normal circumstances, power transistors S1 through S4 are selected with similar characteristics. To ensure that the voltage values ​​of these capacitors are similar, C is usually chosen. B3 =3C B1 C B2 =2C B1 .

[0067] Specifically, such as Figure 3 As shown, capacitor C B4 The two ends are coupled to the Vgate and PGND ports of the driver chip, respectively. The PGND port is connected to the system ground. The voltage between the Vgate and PGND ports is the capacitance C. B4 Voltage V on CB4 And V CB4 =Vgate, the voltage V between port Vgate and port PGND CB4 To generate the drive signal G S4 The driver module provides the drive power supply voltage;

[0068] Node SW3 is connected to port SW3, therefore the voltage between port Boost3 and port SW3 is equivalent to the capacitance C. B3 Voltage V on CB3 In this embodiment of the invention, the voltage V between port Boost3 and port SW3 is... CB3 To generate the drive signal G S3 The driver module provides the drive power supply voltage;

[0069] Similarly, since node SW2 is connected to port SW2, the voltage between port Boost2 and port SW2 is equivalent to the capacitance C. B2 Voltage V on CB2 In this embodiment of the invention, the voltage V between port Boost2 and port SW2 is... CB2 To generate the drive signal G S2 The driver module provides the drive power supply voltage;

[0070] Node SW1 is connected to port SW1, therefore the voltage between port Boost1 and port SW1 is equivalent to the capacitance C. B1 Voltage V on CB3 In this embodiment of the invention, the voltage V between port Boost1 and port SW1 is... CB3 To generate the drive signal G S3 The drive module provides the drive power supply voltage. When D < 0.5, if the flying capacitor is continuously charged, there is no discharge phase, i.e., no... Figure 2 In stage ③ of (a), the power transistor S2 is always off, so capacitor C B1If the energy is not replenished, its voltage will continue to drop. When the voltage is too low, the power transistor S1 cannot reliably switch, meaning the circuit cannot function properly. Similarly, when D > 0.5, if the flying capacitor is continuously charged, there is no discharge phase, meaning there is no... Figure 2 (b) in stage ④, therefore power transistor S4 is always off, capacitor C B3 Unable to charge, and capacitor C B2 and C B1 The energy comes from capacitor C B3 Therefore, capacitor C B1 -C B3 The energy cannot be replenished; if the capacitor discharges continuously, there is no charging phase, that is, no... Figure 2 In stage ② of (b), the power transistor S3 is always in the off state, so capacitor C B2 The capacitor C cannot be charged, thus causing it to... B1 The energy cannot be replenished. Therefore, it is necessary to limit the number of consecutive charging (discharging) cycles.

[0071] To avoid the above situations, the control method further includes: In undervoltage operating mode, after every N charging stages, the flying capacitor is controlled to enter a discharge replenishment mode to perform at least one discharge. Specifically, in discharge replenishment mode, the flying capacitor is controlled to enter one discharge stage, thereby replenishing the energy of the drive power supply capacitor. Afterward, it returns to undervoltage operating mode for continuous charging. This method only replenishes the capacitor's energy once. Of course, it is possible that one discharge is insufficient to fully replenish the energy of the drive power supply capacitor. Therefore, at least one alternating charge and discharge process (i.e., operating in normal operating mode for a period of time) can be performed before returning to undervoltage operating mode to compensate the capacitor's energy multiple times. In overvoltage operating mode, after every N discharge stages, the flying capacitor is controlled to enter a charge replenishment mode to perform at least one charge. In charge replenishment mode, the flying capacitor is controlled to enter one charging stage, thereby replenishing the energy of the drive power supply capacitor. Afterward, it returns to overvoltage operating mode for continuous discharge. This method only replenishes the capacitor's energy once. Of course, a single charge may not be sufficient to fully replenish the energy of the drive power supply capacitor. Therefore, at least one more alternating discharge-charge process (equivalent to operating in normal mode for a period of time) can be performed before returning to the overvoltage operating mode to compensate the capacitor energy multiple times. The duration of the discharge / charge replenishment mode is kTs / 2, where k is a positive integer. In the case of replenishing only once, the duration of the discharge / charge phase is DTs (when D < 0.5) or (1-D)Ts (when D > 0.5), with the other time being a holding phase. In the case of replenishing the capacitor energy multiple times, one discharge process and one charge process alternate for Ts / 2. For ease of description, k=1 will be used in the following description, that is, the drive power supply capacitor is replenished only once after every N consecutive charge or discharge cycles, where N is a positive integer greater than 1.

[0072] The principle for selecting the number of consecutive charge (discharge) cycles is that after N charge or discharge cycles, the minimum voltage of the drive power supply capacitor should not be less than the minimum allowable value. For ease of explanation, Q is defined as... g C is the amount of charge required to drive the power supply capacitor when the power transistor is turned on for the first time. B For driving the power supply capacitor (in practice, C is used) B1 -C B3 Substitute C respectively B ), where n is the number of consecutive turns-on cycles of the power transistor, and β is the maximum allowable percentage drop in voltage of the drive power supply capacitor, i.e., the minimum allowable value of the capacitor voltage is (1-β)V. gate Then it must satisfy:

[0073] (1)

[0074] Where, the left side of the equation is the energy required for the power transistor to turn on n times, and the right side of the equation is C. B The maximum energy that can be provided when the voltage drops by β. From equation (1), we can obtain:

[0075]

[0076] Therefore, the predetermined number N of consecutive discharges or charges of the flying capacitor must be less than or equal to n and be a positive integer.

[0077] To achieve the above control method, Figure 4 A schematic diagram of the control circuit of a three-level DC-DC converter according to an embodiment of the present invention is provided. Figure 4 As shown, the control circuit is configured to adjust the charging and discharging sequence and number of times of the flying capacitor Cf according to the degree to which the flying capacitor voltage Vcf deviates from a preset value (here, 1 / 2Vin), thereby causing the voltage value of the flying capacitor Cf to quickly approach the preset value. The control circuit includes a mode switching module 1, a feedback compensation circuit 2, and a drive generation circuit 3. The mode switching module 1 is configured to receive the voltage value Vcf of the flying capacitor and control the three-level DC-DC converter to switch between different operating modes according to the degree to which the voltage value Vcf of the flying capacitor deviates from the preset value. The feedback compensation circuit 2 is configured to generate a feedback compensation signal Vc based on the error between the feedback signal Vfb representing the output voltage Vout and the reference signal Vref representing the expected value of the output voltage. The drive generation circuit 3 is configured to generate corresponding drive signals based on the feedback compensation signal Vc and different indication signals output by the mode switching module 1 (i.e., overvoltage indication signal OV, undervoltage indication signal UV, and normal indication signal normal), thereby controlling the converter to operate in the corresponding operating mode.

[0078] Specifically, the mode switching module 1 compares the voltage value Vcf of the flying capacitor with different thresholds and outputs different indication signals, namely, overvoltage indication signal OV, undervoltage indication signal UV, and normal indication signal normal, to indicate the operating mode of the converter. When the voltage value Vcf of the flying capacitor is less than the lower limit threshold Vref_L of the first threshold range, the normal indication signal normal is invalid, and the undervoltage indication signal UV is valid; when the voltage value Vcf of the flying capacitor is greater than the upper limit threshold Vref_H of the first threshold range, the overvoltage indication signal OV is valid, and the normal indication signal normal is invalid; when the voltage value Vcf of the flying capacitor approaches a preset value from outside the first threshold range, the normal indication signal normal is valid.

[0079] It should be understood that a second threshold range can be set, with an upper threshold of Vp, slightly greater than the preset value of 1 / 2Vin, and a lower threshold of Vn, slightly less than the preset value of 1 / 2Vin. Thus, when the voltage value of the flying capacitor enters the second threshold range from outside the first threshold range, it indicates that it is approaching the preset value, and the mode switches back to normal operation. Of course, Vp and Vn can be equal, that is, the same value near 1 / 2Vin.

[0080] The feedback compensation circuit 2 includes an error amplifier 2a for receiving a feedback signal Vfb and a reference signal Vref to generate an error signal; and a compensation network 2b for compensating the error signal to generate a feedback compensation signal Vc.

[0081] The drive generation circuit 3 includes a first drive generation circuit 31 and a second drive generation circuit 32. The first drive generation circuit 31 is configured to generate a control signal G1 based on a feedback compensation signal Vc and a first sawtooth wave signal Vramp1, and to generate a control signal G2 based on the feedback compensation signal Vc and the second sawtooth wave signal Vramp2. The periods of Vramp1 and Vramp2 are equal to the switching period and have the same peak-to-peak value, and the phase difference between them is π. Specifically, the first drive generation circuit 31 includes a comparator cmpr1, whose first input terminal (e.g., non-inverting input terminal) receives the feedback compensation signal Vc, its second input terminal (e.g., inverting input terminal) receives the first sawtooth wave signal Vramp1, and its output terminal outputs the control signal G1; and a comparator cmpr2, whose first input terminal (e.g., non-inverting input terminal) receives the feedback compensation signal Vc, its second input terminal (e.g., inverting input terminal) receives the second sawtooth wave signal Vramp2, and its output terminal outputs the control signal G2. The second drive generation circuit 32 is used to generate a corresponding drive signal G based on the received control signals G1 and G2 and various indicator signals (including overvoltage indicator signal OV, undervoltage indicator signal UV, and normal indicator signal normal). S1 -G S4Specifically, the second drive generation circuit 32 includes a first timing circuit 32a, a second timing circuit 32b, and a logic unit 32c. The first timing circuit 32a starts timing when the normal indication signal (normal) is invalid, i.e., when the undervoltage or overvoltage indication signal is valid. The first timing signal T1 is valid, and timing stops when the timing time equals mTs / 2, at which point the first timing signal T1 becomes invalid, indicating the end of N consecutive charging or discharging cycles. The second timing circuit 32b starts timing when the first timing signal T1 is invalid, and the second timing signal T2 is valid. Timing stops when the timing time is kTs / 2, at which point the second timing signal T2 becomes invalid. This timing time is the duration of the discharge / charge replenishment phase. When the second timing signal T2 becomes invalid, the first timing circuit 32a restarts timing, and this cycle continues until the normal indication signal (normal) becomes valid, at which point both timing circuits stop operating. The logic unit 32c then outputs a corresponding drive signal G based on the received control signals G1 and G2, various indication signals, and the first and second timing signals T1 and T2. S1 -G S4 The drive signals G for power transistors S1 and S4 are... S1 and G S4 Complementary, the drive signals G of power transistors S2 and S3 S2 and G S3 Complementary. It should be understood that using timing to determine the end of N charge / discharge cycles is only one method. In other embodiments, counting can also be used. Therefore, the first timing circuit can be replaced by a counting circuit, which instructs the second timing circuit to operate after detecting the completion of N charge / discharge cycles. Of course, other circuits with the above functions are within the scope of protection of this invention.

[0082] Specifically, when the voltage value Vcf of the flying capacitor is greater than the upper limit threshold Vref_H, the overvoltage indication signal OV output by the mode switching module 1 is valid, and the drive generation circuit 3 outputs a corresponding drive signal to control the converter to enter the overvoltage operating mode. In this mode, the flying capacitor Cf continuously enters multiple discharge stages. When the voltage Vcf of the flying capacitor is less than the lower limit threshold Vref_L, the undervoltage indication signal UV output by the mode switching module 1 is valid, and the drive generation circuit 3 outputs a corresponding drive signal to control the converter to enter the undervoltage operating mode. In this mode, the flying capacitor Cf continuously enters the charging stage multiple times. It should be understood that since each charging stage or discharging stage is followed by a holding stage, the charging / discharging stage + holding stage equals Ts / 2. Therefore, if the flying capacitor is in the charging or discharging stage before entering the overvoltage or undervoltage operating mode, it will first go through a holding stage before starting continuous charging or discharging; if the flying capacitor is in the holding stage at this time, it can directly enter the charging stage to start continuous charging or directly enter the discharging stage to start continuous discharging.

[0083] When the voltage value Vcf of the flying capacitor approaches the preset value from outside the first threshold range, the normal indication signal output by the mode switching module 1 becomes valid, and the drive generation circuit 3 outputs the corresponding drive signal to control the converter to enter the normal working mode, thereby alternating between the charging and discharging phases in each switching cycle.

[0084] In undervoltage operating mode, when D is less than 0.5, at the beginning of each charging interval Tc, the drive signal G1 changes from invalid to valid to control the power transistor S1 to turn on. The on-time is the same as the on-time of the power transistor S1 in normal operating mode, i.e., DTs. S2 It is ineffective during each charging interval, meaning that power transistor S2 is not turned on during this period. Drive signal G S3 With drive signal G S2 Complementary, driving signal G S4 With drive signal G S1 The switching states of power transistors S3 and S2 are complementary, thus the switching states of power transistor S4 and S1 are opposite. Therefore, the duration of the hold phase in each charging interval is mTs / 2-DTs; when D is greater than 0.5, at the beginning of each charging interval Tc, the drive signal G... S3 When the signal changes from inactive to active, power transistor S3 is turned on for a duration equal to the normal operating time of S3, i.e., (1-D)Ts. Power transistor S4 remains inactive during this period. The drive signals for power transistors S1 and S4 are complementary, as are the drive signals for power transistors S2 and S3. Consequently, the switching states of power transistors S1 and S4 are opposite, and the switching states of power transistors S2 and S3 are opposite. Therefore, the duration of the hold phase in each charging interval is mTs / 2-(1-D)Ts.

[0085] The first timing circuit is configured to start timing when the undervoltage indication signal UV is valid, stop timing after the timing time reaches N×mTs / 2, and generate a valid first timing signal to control the second timing circuit to start timing. At this time, the flying capacitor begins a discharge to replenish the energy of the power supply capacitor. It should be understood that there are many ways to determine the completion of N charging cycles. In other embodiments, the number of charging stages can also be counted, and a discharge is initiated when the count value reaches m. This will not be described in detail here.

[0086] Similarly, in overvoltage operating mode, when D is less than 0.5, at the beginning of each discharge interval Td, drive signal G2 changes from inactive to active to control power transistor S2 to conduct, and the conduction time is the conduction time of power transistor S2 in normal operating mode, i.e., DTs. Drive signal G1 is inactive during each discharge interval, meaning power transistor S1 is not active during this period. Drive signal G3 is complementary to drive signal G2, and drive signal G4 is complementary to drive signal G1. Therefore, the switching states of power transistor S3 and power transistor S2 are opposite, and the switching states of power transistor S4 and power transistor S1 are opposite. Thus, the duration of the holding phase of each discharge interval is mTs / 2-DTs. When D is greater than 0.5, at the beginning of each discharge interval Td, drive signal G4 changes from inactive to active to control power transistor S4 to conduct, and the conduction time is the conduction time of power transistor S4 in normal operating mode, i.e., (1-D)Ts. Power transistor S3 is not active during this period. The drive signals for power transistors S1 and S4 are complementary, and the drive signals for power transistors S2 and S3 are complementary. Therefore, the switching states of power transistors S1 and S4 are opposite, and the switching states of power transistors S2 and S3 are opposite. Thus, the duration of the holding phase in each discharge interval is mTs / 2 - (1 - D)Ts.

[0087] The first timing circuit is configured to start timing when the overvoltage indication signal 0V is valid, stop timing after the timing time reaches N×mTs / 2, and generate a valid first timing signal to control the second timing circuit to start timing. At this time, the flying capacitor begins a charge to replenish the energy of the power supply capacitor. It should be understood that there are many ways to determine the completion of N charges. In other embodiments, the number of charging stages can also be counted, and when the count value reaches m, a discharge is initiated. This will not be described in detail here.

[0088] Figure 5 The diagram illustrates a first control waveform of a three-level DC-DC converter according to an embodiment of the present invention when D < 0.5. As shown, the diagram illustrates the operating waveform of the three-level Buck converter when the voltage value Vcf across the flying capacitor is less than the lower threshold Vref_L. In this embodiment, it is assumed that C... B3 =3C B1 C B2 =2C B1 C B1 =0.22Uf、V gate =5V, Q g =30Nc, β=10%, then substituting them into equation (2) yields N≤3, which will be explained here using N=3 as an example. In addition, in this embodiment, Tc=Ts / 2 will be used as an example for explanation.

[0089] Before time t0, the flying capacitor Cf alternately charges and discharges. At time t0, the voltage value Vcf of the flying capacitor suddenly drops below the lower threshold Vref_L, that is, significantly lower than 1 / 2Vin and with a high deviation. Therefore, the undervoltage indication signal UV becomes effective, and the normal indication signal normal becomes ineffective. The converter enters undervoltage operating mode, causing the flying capacitor to continuously enter three charging stages, with an interval of Ts / 2 between the start times of adjacent charging stages. Since the flying capacitor is in the holding stage before time t0, it can directly enter the charging stage at time t0. At time t0, the drive signal G... S1 The power transistor S1 turns on, changing from inactive to active, due to the drive signal G. S3 It is also effective; power transistor S3 is turned on, and the voltage value Vcf across the flying capacitor begins to rise. After the on-time DTs of power transistor S1 in normal operating mode, the drive signal G... S1 The drive signal G changes from valid to invalid. S4 From invalid to valid, the driving signal G S3 It remains valid, and at this point, it enters the holding phase, where the voltage value Vcf of the flying capacitor remains unchanged until time t1. The operation during t0-t1 is then repeated, with a time interval of Ts / 2 between t0 and t1. Simultaneously, the first timing circuit starts timing from time t0. When the timing time equals 1.5Ts, i.e., time t2, the first timing signal becomes valid, and the three charging processes end. During time intervals t0-t2, the drive signal G... S2 The operation remains ineffective, and power transistor S2 does not conduct during this period. In this embodiment, since D < 0.5, the drive power supply capacitor C... B1 voltage V cB1 The voltage is reduced to a minimum. Therefore, when the first timing signal is valid, the second timing circuit starts timing, and the flying capacitor Cf enters a discharge phase, so that the voltage V... cB1 Re-rising to V gate When the timing time of the second timing circuit equals 0.5Ts, i.e., at time t3, the second timing signal becomes valid, the first timing circuit restarts timing, and the flying capacitor undergoes three more charging cycles. At time t4, the voltage value Vcf of the flying capacitor is pulled back to around Vin / 2, the normal indicator signal becomes valid, and the converter switches to normal operating mode. The flying capacitor then begins an alternating charging and discharging process, first undergoing a discharging phase and then a charging phase.

[0090] Figure 6 The first control waveform diagram of the three-level DC-DC converter according to an embodiment of the present invention is given when D > 0.5. As shown in the figure, the operating waveform diagram of the three-level buck converter when the voltage value Vcf of the flying capacitor is less than the lower threshold Vref_L is given. Again, the example with m=1 and N=3 is used for illustration.

[0091] Before time t0, the flying capacitor Cf alternately charges and discharges. At time t0, the voltage value Vcf of the flying capacitor suddenly drops below the lower threshold Vref_L, that is, significantly lower than 1 / 2Vin and with a high deviation. Therefore, the undervoltage indication signal UV becomes effective, and the normal indication signal normal becomes ineffective. The converter enters undervoltage operating mode, causing the flying capacitor to continuously enter three charging stages, with an interval of Ts / 2 between the start times of adjacent charging stages. Since the flying capacitor is in the discharging stage before time t0, at time t0, the drive signal G... S1 and G S2 Effective, the flying capacitor first enters the holding phase, and at time t1, the drive signal G... S3 From invalid to valid, G S2 The change from active to inactive causes power transistor S3 to turn on and S2 to turn off, thus the voltage Vcf across the flying capacitor begins to rise; after the on-time (1-D)Ts of power transistor S3 in normal operating mode, at time t2, the drive signal G... S3 The drive signal G changes from valid to invalid. S2 The signal changes from invalid to valid, and then repeats the actions during the period t0-t2, which is Ts / 2 apart. Simultaneously, the first timing circuit starts timing from time t0. When the timing time equals 1.5Ts, i.e., at time t3, the first timing signal becomes valid, and the three charging processes end. In this embodiment, since D > 0.5, the driving power supply capacitor C... B3 voltage V cB3 The voltage is reduced to a minimum. Therefore, when the first timing signal is valid, the second timing circuit starts timing, and the flying capacitor Cf enters a discharge phase, so that the voltage V... cB3 Re-rising to V gate When the timing time of the second timing circuit equals 0.5Ts, i.e., at time t4, the second timing signal becomes valid, the first timing circuit restarts timing, and the flying capacitor undergoes three more charging cycles. At time t5, the voltage value Vcf of the flying capacitor is pulled back to around Vin / 2, the normal indicator signal becomes valid, and the converter switches to normal operating mode, and the flying capacitor begins its alternating charging and discharging process.

[0092] Figure 7 The second control waveform diagram of the three-level DC-DC converter according to an embodiment of the present invention is given when D < 0.5. As shown in the figure, the operating waveform diagram of the three-level Buck converter when the flying capacitor voltage Vcf is less than the lower threshold Vref_L is given. Unlike the previous embodiment, this embodiment uses m=2 and N=3 as an example for explanation.

[0093] Before time t0, the flying capacitor Cf alternately charges and discharges. At time t0, the voltage value Vcf of the flying capacitor suddenly drops below the lower threshold Vref_L. Therefore, the undervoltage indication signal UV becomes valid, and the normal indication signal normal becomes invalid. The converter enters undervoltage operating mode, causing the flying capacitor to charge three times consecutively. Unlike the previous embodiment, in this embodiment, the interval between the start times of adjacent charging stages is Tc = mTs / 2 = Ts. Since the flying capacitor is in the holding stage before time t0, it can directly enter the charging stage at time t0. At time t0, the drive signal G... S1 The power transistor S1 turns on, changing from inactive to active, due to the drive signal G. S3 It is also effective; power transistor S3 is turned on, and the voltage value Vcf across the flying capacitor begins to rise. After the on-time DTs, the drive signal G... S1 The drive signal G changes from valid to invalid. S4 From invalid to valid, the driving signal G S3 It remains valid, and at this point, it enters the holding phase, where the voltage value Vcf of the flying capacitor remains unchanged until time t1. The operation during t0-t1 is then repeated, with a time interval Ts between t0 and t1. Simultaneously, the first timing circuit starts timing from time t0. At time t2, the first timing circuit has not yet reached 3Ts, but the voltage value Vcf of the flying capacitor has been pulled back to near Vin / 2. Therefore, the normal indication signal is valid at time t2. Afterward, the converter switches to normal operating mode, and the flying capacitor begins an alternating charge and discharge process, discharging before charging. At time t3, the flying capacitor enters the discharge phase, C... B1 The energy is replenished, and the voltage V cB1 Re-rising to V gate After that, it will work normally by alternating between charging and discharging.

[0094] Figure 8 The second control waveform diagram of the three-level DC-DC converter according to an embodiment of the present invention is given when D > 0.5. As shown in the figure, the operating waveform diagram of the three-level Buck converter when the flying capacitor voltage Vcf is less than the lower threshold Vref_L is given. Similarly, in this embodiment, m=2 and N=3 are used as examples for illustration.

[0095] Before time t0, the flying capacitor alternately charges and discharges. At time t0, the voltage value Vcf of the flying capacitor suddenly drops below the lower threshold Vref_L. Therefore, the undervoltage indication signal UV becomes active, and the normal indication signal normal becomes inactive. The converter enters undervoltage operating mode, causing the flying capacitor to charge three times consecutively. Since the flying capacitor is in the discharging phase before time t0, at time t0, the drive signal G... S1 and G S2Effective, the flying capacitor first enters the holding phase, and at time t1, the drive signal G... S3 From invalid to valid, G S2 The switch changes from active to inactive, causing power transistor S3 to turn on and power transistor S2 to turn off. Therefore, the voltage Vcf across the flying capacitor begins to rise. After a conduction time of (1-D)Ts, at time t2, the drive signal G... S3 The drive signal G changes from valid to invalid. S2 From invalid to valid, the flying capacitor Cf enters a holding phase until time t3, after which it repeats the operation from t0 to t3, with a time interval Tc between t0 and t3. In this embodiment, the interval between the start times of adjacent charging phases is Tc = mTs / 2 = Ts. Simultaneously, the first timing circuit starts timing from time t0. By time t4, the first timing circuit has not yet reached 3Ts, but the voltage value Vcf of the flying capacitor is pulled back to near Vin / 2. At this time, the normal indication signal is valid, and the converter switches to normal operating mode. The flying capacitor begins an alternating charging and discharging process, discharging first and then charging. At time t5, the flying capacitor enters the discharging phase, C... B3 The energy is replenished, and the voltage V cB3 Re-rising to V gate After that, it will work normally by alternating between charging and discharging.

[0096] In all the above embodiments, the system switches to normal operating mode when the voltage value of the flying capacitor returns to the second threshold range, regardless of whether the continuous charging process has ended. Those skilled in the art will understand that the voltage value of the flying capacitor can also be determined after the continuous charging process has ended, thereby determining whether to switch back to normal operating mode.

[0097] Furthermore, the above operating waveforms are all based on the undervoltage operating mode. It should be understood that if Vcf suddenly rises, far exceeding 1 / 2Vin, the above control process can be used to pull the voltage of the flying capacitor back to around Vin / 2. The principle of this process is the same as above and will not be elaborated here.

[0098] In summary, the technical solution of this invention compensates for the shortcomings of conventional voltage equalization strategies in balancing the flying capacitor voltage in a timely manner under extreme conditions by adjusting the charging and discharging phases during the operation of a three-level DC-DC converter, thereby achieving rapid and effective regulation of the flying capacitor voltage.

[0099] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control method for adjusting the capacitor voltage in a three-level DC-DC converter, the three-level DC-DC converter comprising first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between the common node of the first and second power transistors and the common node of the third and fourth power transistors, characterized in that, include: When the voltage value of the flying capacitor is less than the lower limit of the first threshold range, the flying capacitor is controlled to enter the charging stage multiple times in a row. When the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, the flying capacitor is controlled to enter the discharge stage multiple times in a row, so that the voltage value of the flying capacitor approaches the preset value.

2. The control method according to claim 1, characterized in that, There is at least one holding phase between two adjacent charging phases and between two adjacent discharging phases, wherein the voltage value of the flying capacitor is controlled to remain constant during the holding phase.

3. The control method according to claim 1, characterized in that, Also includes: When the voltage value of the flying capacitor approaches the preset value from outside the first threshold range, the three-level DC-DC converter is controlled to enter the normal operation mode, so that the charging phase and the discharging phase alternate in each switching cycle.

4. The control method according to claim 1, characterized in that, Also includes: When the voltage value of the flying capacitor is less than the lower limit of the first threshold range, the three-level DC-DC converter is controlled to enter the undervoltage operating mode so that the flying capacitor enters the charging stage multiple times in a row. When the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, the three-level DC-DC converter is controlled to enter the overvoltage working mode so that the flying capacitor enters the discharge stage multiple times in a row.

5. The control method according to claim 4, characterized in that, During continuous charging of the flying capacitor in the undervoltage operating mode, the flying capacitor is controlled to enter at least one discharge phase; during continuous discharging of the flying capacitor in the overvoltage operating mode, the flying capacitor is controlled to enter at least one charging phase.

6. The control method according to claim 5, characterized in that, Also includes: Under the undervoltage working mode, after every N charging stages, the flying capacitor is controlled to enter the discharge compensation mode to perform at least one discharge. In the overvoltage operating mode, after every N discharge stages, the flying capacitor is controlled to enter the charging replenishment mode to perform at least one charge, thereby raising the voltage of the driving power supply capacitor in the driving circuit of the three-level DC-DC converter, where N is a positive integer greater than 1.

7. The control method according to claim 6, characterized in that, Also includes: In the discharge replenishment mode, the flying capacitor is controlled to enter a discharge stage and then return to the undervoltage working mode, or it enters the normal working mode for a short time and then returns to the undervoltage working mode. or In the charging replenishment mode, the flying capacitor is controlled to enter the first charging stage and then return to the overvoltage working mode, or it enters the normal working mode and then returns to the overvoltage working mode immediately.

8. The control method according to claim 6, characterized in that, The time interval between the start position of the previous charging stage and the start position of the next charging stage in the N charging stages is the charging interval time. The time interval between the start position of the previous discharging stage and the start position of the next discharging stage in the N discharging stages is the discharging interval time. The length of the charging interval time and the discharging interval time is an integer multiple of 1 / 2 switching cycle.

9. The control method according to claim 8, characterized in that, When D is less than 0.5, the charging interval includes a charging phase with a duration of D×Ts, and the rest are holding phases; the discharging interval includes a discharging phase with a duration of D×Ts, and the rest are holding phases. When D is greater than 0.5, the charging interval includes a charging phase with a duration of Ts×(1-D), and the rest are holding phases; the discharging interval includes a discharging phase with a duration of Ts×(1-D), and the rest are holding phases, where Ts is the switching cycle and D is the duty cycle of the first power transistor.

10. The control method according to claim 8, characterized in that, When the duty cycle is less than 0.5, in each charging interval of the undervoltage operating mode, the first power transistor is controlled to turn on once, and the on-time is the product of the duty cycle and the switching cycle, while the second power transistor is not turned on; in each discharging interval of the overvoltage operating mode, the second power transistor is controlled to turn on once, and the on-time is the product of the duty cycle and the switching cycle, while the first power transistor is not turned on. The drive signals of the first power transistor and the fourth power transistor are complementary, and the drive signals of the second power transistor and the third power transistor are complementary.

11. The control method according to claim 8, characterized in that, When the duty cycle is greater than 0.5, in each charging interval of the undervoltage operating mode, the third power transistor is controlled to conduct once, and the conduction time is the product of (1-D) and the switching cycle, while the fourth power transistor is not conducted; in each discharging interval of the overvoltage operating mode, the fourth power transistor is controlled to conduct once, and the conduction time is the product of (1-D) and the switching cycle, while the third power transistor is not conducted. The drive signals of the first power transistor and the fourth power transistor are complementary, and the drive signals of the second power transistor and the third power transistor are complementary, where D is the duty cycle of the first power transistor.

12. The control method according to claim 3, further comprising: When in the normal operating mode, the voltage value of the flying capacitor is controlled to be equal to the preset value.

13. A control circuit for a three-level DC-DC converter, the three-level DC-DC converter comprising first to fourth power transistors connected in series between an input voltage and a reference ground, and a flying capacitor connected between the common node of the first and second power transistors and the common node of the third and fourth power transistors, characterized in that, The control circuit is configured as follows: When the voltage value of the flying capacitor is less than the lower threshold of the first threshold range, the flying capacitor is controlled to enter the charging stage multiple times in succession; when the voltage value of the flying capacitor is greater than the upper threshold of the first threshold range, the flying capacitor is controlled to enter the discharging stage multiple times in succession, so that the voltage value of the flying capacitor approaches the preset value.

14. The control circuit according to claim 13, characterized in that, The control circuit includes: The mode switching module is configured to receive the voltage value of the flying capacitor and output different indication signals according to the degree to which the voltage value of the flying capacitor deviates from the preset value to control the three-level DC-DC converter to switch between different operating modes. The feedback compensation circuit is configured to generate a feedback compensation signal based on the error between a feedback signal characterizing the output voltage and a reference signal characterizing the desired value of the output voltage; and The drive generation circuit is configured to generate a corresponding drive signal based on the feedback compensation signal and the indication signal, thereby controlling the three-level DC-DC converter to operate in the corresponding operating mode.

15. The control circuit according to claim 14, characterized in that, The mode switching module is configured as follows: When the voltage value of the flying capacitor is less than the lower limit of the first threshold range, an effective undervoltage indication signal is output to indicate that the three-level DC-DC converter enters the undervoltage operating mode, so that the flying capacitor enters the charging stage multiple times in a row. When the voltage value of the flying capacitor is greater than the upper limit of the first threshold range, an effective overvoltage indication signal is output to indicate that the three-level DC-DC converter enters the overvoltage operating mode, so that the flying capacitor enters the discharge stage multiple times in a row.

16. The control circuit according to claim 15, characterized in that, There is at least one holding phase between two adjacent charging phases and between two adjacent discharging phases, wherein the voltage value of the flying capacitor is controlled to remain constant during the holding phase.

17. The control circuit according to claim 15, characterized in that, When the voltage value of the flying capacitor approaches the preset value from outside the first threshold range, the mode switching module is configured to output a valid normal indication signal to indicate that the three-level DC-DC converter enters the normal operation mode, thereby alternating the charging phase and the discharging phase in each switching cycle.

18. The control circuit according to claim 14, characterized in that, The drive generation circuit includes: A first drive generation circuit is configured to generate a first control signal based on the feedback compensation signal and a first sawtooth wave signal, and to generate a second control signal based on the feedback compensation signal and a second sawtooth wave signal; and The second drive generation circuit is configured to generate corresponding drive signals based on the received first and second control signals and various indication signals.

19. The control circuit according to claim 15, characterized in that, The control circuit is also configured to control the flying capacitor to enter a discharge replenishment mode to perform at least one discharge after every N charging stages; or to control the flying capacitor to enter a charge replenishment mode to perform at least one charge after every N discharge stages, thereby increasing the voltage of the drive power supply capacitor in the drive circuit of the three-level DC-DC converter, where N is a positive integer greater than 1.

20. The control circuit according to claim 19, characterized in that, The control circuit is also configured to, in the discharge replenishment mode, control the flying capacitor to enter a discharge phase and then return to the undervoltage operating mode, or to enter the normal operating mode and then return to the undervoltage operating mode immediately. or In the charging replenishment mode, the flying capacitor is controlled to enter the first charging stage and then return to the overvoltage working mode, or it enters the normal working mode and then returns to the overvoltage working mode immediately.

21. The control circuit according to claim 19, characterized in that, The time between the start position of the previous charging stage and the start position of the next charging stage in the N charging stages is the charging interval time, and the time between the start position of the previous discharging stage and the start position of the next discharging stage in the N discharging stages is the discharging interval time. The length of the charging interval time and the discharging interval time is an integer multiple of 1 / 2 switching cycle.

Images