A multi-environment packaged chip testing method and a packaged chip

Abstract

The present disclosure relates to a multi-environment packaged chip testing method. The method includes step 1, performing a test on the packaged chip based on a first test environment, and obtaining a first trimming value based on the test result; step 2, burning the first trimming value into the first trimming bit integrated inside the packaged chip to achieve a first trimming of the packaged chip; step 3, reading the first trimming value recorded in the first trimming bit of the packaged chip and performing a second test on the packaged chip based on a second test environment, and obtaining a second trimming value based on the second test result and the first trimming value; step 4, burning the second trimming value into the second trimming bit integrated inside the packaged chip to achieve a second trimming of the packaged chip. By performing multi-environment packaged chip testing through the above method, the testing cost is reduced and the testing efficiency and accuracy are improved.

Description

Technical Field

[0001] The present invention relates to a chip testing method, and more particularly to a multi-environment packaged chip testing method and a packaged chip. Background Art

[0002] Currently, in the integrated circuit chip development process, to ensure high-precision chip manufacturing yields, the chips must be tested multiple times in different environments before they are shipped. The test results from these different environments are then calculated to produce a final test result, verifying whether the chip's performance meets high-precision requirements. For example, during the production of temperature sensor chips, it is necessary to test the chip's output voltage or current, corresponding to the ambient temperature, at different ambient temperatures.

[0003] In the chip testing and verification phase, the chip parameters are tested in two or more different temperature environments, and the test results in different temperature environments can be calculated, so that the chip can be adjusted and screened based on the two or more test results. When testing a single chip, the chip can be placed in two environments for testing respectively, and the data is recorded. The two data are processed to obtain the final parameter test value. However, the test of a single chip consumes a lot of test time, places high demands on the test equipment, and has unavoidable test errors, so it is not feasible for large-scale industrial production. In addition, when mass-producing large quantities of chips, if the batch chips are first placed in the first environment for testing and then placed in the second environment for testing, the order of testing the chips in the second environment will be disrupted, and the test equipment cannot mark and trace the batch chips, so it is impossible to associate the first test data with the second test data of the same chip.

[0004] In the prior art, it is usually chosen to perform CP (Circuit Probing or Chip Probing, wafer) testing on the chip to be packaged before the chip is packaged. The chips are distinguished by recording the coordinate position of each chip on the wafer. However, the problem with this testing method is that certain parameters of the high-precision chip during the packaging process may change slightly due to the chip packaging operation. Although the chip to be packaged has passed the test and meets the accuracy requirements, after being packaged into a finished product, the random changes in the chip parameters caused by the packaging cannot be measured or predicted. Therefore, in the manufacturing process of high-precision chips, wafer-level chip testing still cannot meet the testing requirements.

[0005] To address the above issues, there is an urgent need for a multi-environment packaged chip testing method with high efficiency, low cost and high accuracy. Summary of the Invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a multi-environment packaged chip testing method and a packaged chip, which can provide high-precision testing in multiple environments based on the packaged chip.

[0007] The present invention adopts the following technical solutions.

[0008] According to a first aspect of the present invention, a multi-environment packaged chip testing method is provided, comprising the following steps: Step 1, performing a test on the packaged chip based on a first test environment, and obtaining a first trimming value based on the result of the first test; Step 2, burning the first trimming value into a first trimming bit integrated inside the packaged chip to achieve a first trimming of the packaged chip; Step 3, reading the first trimming value recorded in the first trimming bit of the packaged chip and performing a second test on the packaged chip based on a second test environment, and obtaining a second trimming value based on the result of the second test and the first trimming value; Step 4, burning the second trimming value into a second trimming bit integrated inside the packaged chip to achieve a second trimming of the packaged chip.

[0009] Preferably, step 1 also includes: step 11, presetting multiple gears for the packaged chip, and each gear corresponds to two fixed gear values ​​that match the test results to identify the gear range; step 12, comparing a test result with the fixed gear value, if the test result falls within the gear range, then obtaining the gear range of the test result; step 13, determining the gear according to the gear range of the test result and generating a first adjustment value.

[0010] Preferably, 2 is preset for the packaged chip N-1 +1 to 2 N gears, each of which corresponds to one of the N-bit binary adjustment values.

[0011] Preferably, step 12 also includes: step 1201, if a test result falls outside the gear range, then calculating and generating a third adjustment value, and burning the third adjustment value into a third adjustment bit integrated inside the packaged chip to achieve pre-adjustment of the packaged chip; step 1202, based on the pre-adjustment, so that a test result obtained by the chip in the first test environment is adjusted to fall within the gear range; step 1203, re-testing the packaged chip based on the first test environment, and obtaining a test result.

[0012] Preferably, step 3 further includes: presetting a property value for the packaged chip, and calculating a second trimming value according to the preset property value, the first trimming value and the secondary test result.

[0013] Preferably, the first test environment and the second test environment are respectively a first constant temperature and a second constant temperature, and the first test result and the second test result are respectively a first test voltage and a second test voltage.

[0014] Preferably, there is a linear relationship between the constant temperature and the test voltage, and the calculation formula is V=kT+b; wherein V is the test voltage, k is the preset property value of the packaged chip, T is the constant temperature, b is the relationship coefficient between the constant temperature and the test voltage, and k and b are fixed values ​​used to identify the performance of the packaged chip.

[0015] Preferably, in step 31, a first trimming value is obtained, and the gear voltage V′1 of the first test voltage V1 is restored according to the first trimming value; in step 32, a second trimming voltage V2′ is calculated according to the preset attribute value k and the first trimming value, and the calculation formula of the second trimming voltage is V2′=k(T2-T1)+V′1, wherein V2′ is the second trimming voltage, T2 is the second constant temperature, T1 is the first constant temperature, and V′1 is the gear voltage of the first test voltage; in step 33, the second trimming voltage is compared with the second test voltage, and a second trimming value is generated.

[0016] According to a second aspect of the present invention, a packaged chip is provided, comprising an input module, a trimming module and an output module. The input module is used to input the trimming value obtained by testing the packaged chip into the trimming module; the trimming module is used to burn the trimming value into the trimming bit integrated inside the chip to achieve trimming of the packaged chip; and the output module is used to recognize that the packaged chip is located in a second test environment, read the first trimming bit and output the first trimming value.

[0017] Preferably, the packaged chip in the second aspect of the present invention is also used to implement a multi-environment packaged chip testing method as in the first aspect of the present invention.

[0018] Preferably, the packaged chip in the second aspect of the present invention is a temperature sensor chip.

[0019] The beneficial effect of the present invention is that, compared with the prior art, a multi-environment packaged chip testing method in the present invention calculates and saves multiple test results of the chip in different test environments into the trimming bits inside the chip, and performs multiple trimmings on the chip according to the trimming values ​​in the trimming bits, thereby changing the factory parameters of the chip through multiple tests to make the chip have higher precision.

[0020] The present invention can embed the test results obtained from the first test into the packaged chip, and during the second test, the second adjustment value is modified based on the first test results. This eliminates the need to mark the packaged chips externally, allowing batch testing of chips. Consequently, the present invention reduces testing costs, shortens testing time, improves testing efficiency, eliminates inevitable testing errors caused by complex testing methods, and enhances test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flowchart of a multi-environment packaged chip testing method according to the present invention;

[0022] Figure 2 This is a flowchart of step 1 in a multi-environment packaged chip testing method of the present invention;

[0023] Figure 3 This is a method flow chart of step 3 in a multi-environment packaged chip testing method of the present invention;

[0024] Figure 4 This is a schematic diagram of a module structure of a packaged chip in one embodiment of the present invention;

[0025] Figure 5 FIG. 1 is a schematic diagram of a module structure of a packaged chip in another embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present application will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.

[0027] A first aspect of the present invention provides a multi-environment packaged chip testing method.

[0028] Figure 1 This is a flow chart of a multi-environment packaged chip testing method in the present invention. Figure 1 As shown, a multi-environment packaged chip testing method includes steps 1 to 4.

[0029] Step 1: Perform a test on the packaged chip based on a first test environment, and obtain a first trimming value according to the test result.

[0030] Specifically, the first test environment can be determined based on the characteristics of the chip and the specific purpose of the test. For example, the first test environment can be determined to be one or more of a certain temperature value, a certain humidity value, a certain atmospheric pressure value, or data such as external pressure, voltage, or current changes received by the chip.

[0031] Typically, when testing a single chip or batches of chips, the chip is placed in specialized chip testing equipment and connected to the chip pins via electrical equipment. This equipment is designed to maintain a constant chip environment. After the chip is placed in the chip testing equipment for a period of time, its properties are adjusted according to the equipment's settings, and the environment is monitored to generate test results. For example, after a temperature sensor chip is placed in a constant temperature test environment for a period of time, it will generate an output voltage based on the ambient temperature. This output voltage is the test result of a single test.

[0032] It's worth noting that a single test refers to a test performed on a chip in a first test environment. A single test may include multiple tests on a batch of chips or a single chip. The single test result is the actual chip output data obtained during the last test in a single test, such as a specific voltage value. In order to embed the information obtained from a single test result into the chip, the test result must be processed to obtain a storable adjustment value.

[0033] Preferably, obtaining the adjustment value according to a test result further includes steps 11 to 13. Figure 2 This is a flowchart of step 1 in a multi-environment packaged chip testing method of the present invention. Figure 2 As shown, in step 11, multiple gears are preset for the packaged chip, and each gear corresponds to two fixed gear values ​​that match the test results to identify the gear range. In step 12, the test result is compared with the fixed gear values. If the test result falls within the gear range, the gear range of the test result is obtained. In step 13, the gear is determined based on the gear range of the test result and a first adjustment value is generated.

[0034] Preferably, 2 is preset for the packaged chip N-1 +1 to 2 N gears, each of which corresponds to one of the N-bit binary adjustment values.

[0035] For example, 8 gears are preset for the packaged chip, and each gear corresponds to one of the three-bit binary adjustment values. The adjustment values ​​are 000, 001, 010, 011, 100, 101, 110 and 111. Generally speaking, the number of preset gears for the packaged chip can be determined according to the actual requirements of the chip precision test, and the length of the binary adjustment value can be selected according to the number of preset gears. For example, when the test precision requirement is that the test result falls within the range (a, b), 2 is preset for the packaged chip. N-1 +1 to 2 N The sum of the gear ranges of the gears should be consistent with the range (a, b). In addition, when the preset gears are 9 to 16, you can choose to generate a four-bit length adjustment value.

[0036] In one embodiment of the present invention, a temperature sensor chip can be tested. By placing the chip in a test environment with a constant temperature, the voltage value corresponding to the current constant temperature output by the chip is detected. In one embodiment of the present invention, there is a linear relationship between the constant temperature of the temperature sensor chip and the test voltage, and its calculation formula is V=kT+b. Among them, V is the test voltage, the slope k is the preset property value of the packaged chip, T is the constant temperature, and the intercept b is the relationship coefficient between the constant temperature and the test voltage. k and b are fixed values ​​used to identify the performance of the packaged chip. For example, V=0.01T+1, where k=0.01volt / ℃ and b=1volt.

[0037] It is worth noting that the accuracy of the temperature sensor chip is usually preset before testing to determine whether the manufactured chip meets the requirements. In this embodiment, the accuracy can be set to ±0.4%.

[0038] In this example, we select 0°C as the first test environment. Since the intercept b is fixed at 1 volt and the chip test accuracy is set to ±0.4%, it can be seen that the primary test results of qualified chips should fall within the target range of 0.96 volt to 1.04 volt. To improve chip yield and ensure that more chips pass the test, the chips can be pre-trimmed during the first test based on the test results and expected chip performance. This pre-trimming ensures that more chips fall within the target range of qualified chips.

[0039] Preferably, step 12 also includes, step 1201, if a test result falls outside the gear range, then calculating and generating a third adjustment value, saving the third adjustment value to a third adjustment bit integrated inside the packaged chip, and burning the packaged chip according to the third adjustment bit to achieve pre-adjustment of the packaged chip; step 1202, based on the pre-adjustment, so that a test result obtained by the chip in the first test environment is adjusted to fall within the gear range; step 1203, re-testing the packaged chip based on the first test environment, and obtaining a test result.

[0040] Specifically, a chip can be tested more than once in the first test environment. Usually, a chip that passes the first test will not be tested again, that is, one test is completed. However, for a chip that fails the first test, the chip can be pre-trimmed by burning the third trimming bit. After the pre-trimming, a second test is performed based on the first test environment. When the second test determines that the chip is a qualified chip, the test is terminated, the test results are recorded, and the first trimming value is obtained. Theoretically, during the process of testing a chip once, the chip can be tested multiple times in unlimited numbers until the chip is trimmed to a qualified chip.

[0041] In one embodiment, different voltage values ​​can be used as fixed gear values, and gears can be preset for the packaged chip based on the gear values. For example, fixed gear values ​​can be preset as 0.96 volt, 0.97 volt, 0.98 volt, 1.03 volt, and 1.04 volt, and the first gear range can be set to [0.96 volt, 0.97 volt], the second gear range can be set to (0.97 volt, 0.98 volt], the eighth gear range can be set to (1.03 volt, 1.04 volt], and so on. After obtaining a test result, the test result is compared with the multiple fixed gear values. When the test result falls within the first gear range, the corresponding gear adjustment value is determined based on the test result.

[0042] Step 2: Burn the first trimming value into the first trimming bit integrated inside the packaged chip to achieve a one-time trimming of the packaged chip.

[0043] Specifically, before the chip is packaged, blank chip trim bits are reserved within the chip during the integrated circuit design process. For example, eight bits of chip reserved bits are reserved for subsequent recording of chip test results. Bits 1-2 of the eight bits are used to program the third trim value, bits 3-5 are used to program the first trim value, and bits 6-8 are used to program the second trim value. These chip reserved bits can be written to based on the circuitry connected to the chip pins.

[0044] In one embodiment, after obtaining the first trimming value, this first trimming value can be burned into the trimming bits integrated within the chip. Depending on the specific configuration of the packaged chip, laser trimming of the resistor film, fuse burnout trimming, diode short-circuit trimming, trimming of an embedded non-volatile storage unit, or other possible trimming methods known in the art can be selected to perform a single trimming of the packaged chip. The single trimming in this embodiment of the present invention is simply used to record the first trimming value obtained from a single test and does not alter the performance of the chip.

[0045] Unlike the primary trimming, the pre-trimming method in step 1 is the same as the primary trimming method, but the process can burn the third trimming bit according to the third trimming value, and change the performance of the chip according to the change of the state of the third trimming bit, so that the performance of the packaged chip meets the expected accuracy requirements, such as the output voltage is within ±0.4% of the target value.

[0046] Step 3: read the first trimming value recorded in the first trimming bit of the packaged chip and perform a secondary test on the packaged chip based on a second test environment, and obtain a second trimming value according to the secondary test result and the first trimming value.

[0047] After completing the initial trimming of the packaged chip, the present method can perform a secondary test on the packaged chip by changing the environmental parameters of the chip testing equipment. In one embodiment, the chip testing equipment changes its temperature parameters and, after a certain period of time, uses its own temperature sensor to determine that the temperature environment meets the test conditions, thereby initiating a secondary test on the packaged chip placed therein.

[0048] Optionally, the batch of chips previously tested can be binned based on the position of the first trimming value obtained after the first test. This binning test ensures that chips in the same position have the same first trimming value, thereby obtaining a unified specific trimming method for the second trimming based on the first trimming value.

[0049] Therefore, during the secondary test, the first trimming value recorded in the chip trimming bit can also be read simultaneously, and the second trimming value can be calculated based on the first trimming value according to the secondary test result.

[0050] Preferably, a property value is preset for the packaged chip, and a second trimming value is calculated based on the preset property value, the first trimming value, and the secondary test result. Typically, the preset property value of a chip represents the property data provided by the chip manufacturer regarding the desired properties of the chip. The preset property value can be a fixed value or a function value that varies based on certain environmental factors.

[0051] Based on the preset attribute values, the parameters representing the first test environment, the first test results, the first adjustment value, the parameters representing the second test environment and the second test results, the specific value or value range of the second adjustment value should be reasonably determined.

[0052] In one embodiment, the packaged chip can be a temperature sensor chip that can accurately measure the ambient temperature, and the first test environment and the second test environment are respectively a first constant temperature T1 and a second constant temperature T2. The first constant temperature T1 and the second constant temperature T2 can be set according to the requirements of the chip test. There is a certain difference between the two temperatures, which can well reflect the accuracy of the chip's temperature perception in different temperature environments. At the same time, the result of the first test is a first test voltage V1, and the result of the second test is a second test voltage V2. The first test voltage V1 is the output voltage value of the chip tested in the environment of the first constant temperature T1, and the second test voltage V2 is the output voltage value of the chip tested in the environment of the second constant temperature T1.

[0053] Preferably, Figure 3 This is a flowchart of step 3 in a multi-environment packaged chip testing method of the present invention. Figure 3As shown, in step 31, a first trimmed value is obtained and, based on the first trimmed value, the level V′1 at which the first test voltage V1 is located is restored. In step 32, a second trimmed voltage is calculated based on the preset attribute value k and the first trimmed value. The calculation formula for the second trimmed voltage is V2′=k(T2-T1)+V′1, where V2′ is the second trimmed voltage, T2 is the second constant temperature, T1 is the first constant temperature, and V′1 is the level at which the first test voltage is located. In step 33, the second trimmed voltage V2′ is compared with the second test voltage V2 to generate a second trimmed value.

[0054] In one embodiment of the present invention, the constant temperature of the second test environment is assumed to be 100°C. At the second test temperature, the preset attribute value of the chip, i.e., the slope k, can be corrected. Assuming that a second test is performed on all chips in the first gear, the expected value of k is 0.01mvolt / °C. The first trimmed value read for all chips is the average of the target range represented by the first gear, i.e., the average of (0.96volt, 0.97volt) is 0.965volt. Therefore, the second trimmed voltage V2' can be obtained as (0.01mvolt / °C)*(100°C-0°C)+0.965volt=1.965volt.

[0055] Specifically, the second trimming voltage is calculated based on the first trimming value and the preset attributes, and can represent the output voltage value that the chip manufacturer expects to obtain in the second test environment. By comparing the expected output voltage value with the second test voltage obtained by actual measurement, the difference between the actual and expected values ​​can be obtained. Usually, during the comparison process, the difference between the second trimming voltage V2' and the second test voltage V1 can be calculated, and the second trimming value can be generated based on the difference. The specific generation method of the second trimming value is consistent with the generation method of the first trimming value. A specific gear can also be set according to the size of the above-mentioned difference, and a three-bit binary data can be determined according to the specific gear range in which the difference falls. Then, the binary data is sent to the chip through the chip pin and burned into the chip trimming bit.

[0056] Step 4: Burn the second trimming value into the second trimming bit integrated inside the packaged chip to achieve secondary trimming of the packaged chip.

[0057] The programming method for the secondary trim is exactly the same as the primary trim, so I will not go into detail here. Based on the internal design of the chip, the secondary trim bit can actually change the chip's properties to meet the expected property values ​​of the chip.

[0058] According to a second aspect of the present invention, a packaged chip 100 is provided. Figure 4 The figure is a schematic diagram of a module structure of a packaged chip in one embodiment of the present invention. Figure 5FIG. 1 is a schematic diagram of a module structure of a packaged chip in another embodiment of the present invention. Figure 4-5 As shown, the packaged chip 100 includes an input module 101 , a trimming module 102 and an output module 103 .

[0059] The input module 101 is configured to input the trimming values ​​obtained by testing the packaged chip into the trimming module.

[0060] Specifically, the input module 101 may include a first input unit 1011 and a second input unit 1012, wherein the first input unit 1011 is used to input a first adjustment value obtained by performing a primary test on the packaged chip into the adjustment module; the second input unit 1012 is used to input a second adjustment value obtained by performing a secondary test on the packaged chip into the adjustment module.

[0061] Specifically, the input module 101 may further include a third input unit 1013 for inputting a third trimming value obtained by performing a test on the packaged chip into the trimming module.

[0062] Specifically, the input module 101 may further include a first calculation unit 1014 and a second calculation unit 1015, respectively configured to calculate a first adjustment value and a second adjustment value based on the obtained primary test result and the secondary test result. The input module 101 may further include a third calculation unit 1016, configured to calculate a third adjustment value based on the obtained primary test result. For the specific calculation method, reference may be made to the content described in the first part of the present invention.

[0063] The trimming module 102 is configured to burn the trimming value into the trimming bit integrated inside the chip to achieve trimming of the packaged chip.

[0064] Specifically, the trimming module 102 may include a first trimming module 1021 and a second trimming module 1022. These two modules may respectively adjust a first trimming bit and a second trimming bit based on a first trimming value and a second trimming value inputted from the input module 101. The trimming module 102 may also include a third trimming module 1023 for adjusting a third trimming bit based on a third trimming value inputted from the input module 101. Typically, the trimming module also includes one or more components such as a resistive film, a fuse, and a diode for trimming.

[0065] The output module 103 is used to identify that the packaged chip is in the second test environment, read the first trimming position and output the first trimming value, so as to calculate the gear position of the chip and the secondary trimming mode of the chip according to the first trimming value.

[0066] It is worth noting that there are various methods for identifying that a packaged chip is in the second test environment. In one embodiment, the status of the packaged chip can be identified by a secondary test signal transmitted by chip testing equipment in circuit connection with the packaged chip, and a first trimming value can be output. In another embodiment, based on an input signal obtained from first input unit 1011 of input module 101 in the packaged chip, it can be determined that the packaged chip has completed one test and is about to begin a second test, thereby outputting a second trimming value after a predetermined period of time.

[0067] Preferably, the packaged chip can be used to implement the multi-environment packaged chip testing method as described in the first aspect of the present invention.

[0068] Preferably, the packaged chip is a temperature sensor chip. The output voltage of the packaged chip exhibits a linear relationship with the ambient temperature. The packaged chip integrates a trim bit and a circuit module for programming the trim bit, enabling it to modify its properties based on the results of two chip tests to meet the chip's high-precision requirements.

[0069] The beneficial effect of the present invention is that, compared with the prior art, a multi-environment packaged chip testing method in the present invention calculates and saves multiple test results of the chip in different test environments into the trimming bits inside the chip, and performs multiple trimmings on the chip according to the trimming values ​​in the trimming bits, thereby changing the factory parameters of the chip through multiple tests to make the chip have higher precision.

[0070] The present invention can embed the test results obtained from the first test into the packaged chip, and during the second test, the second adjustment value is modified based on the first test results. This eliminates the need to mark the packaged chips externally, allowing batch testing of chips. Consequently, the present invention reduces testing costs, shortens testing time, improves testing efficiency, eliminates inevitable testing errors caused by complex testing methods, and enhances test accuracy.

[0071] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation plans of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, and is not a limitation on the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A multi-environment packaged chip testing method, characterized in that: The following steps are involved: Step 1: performing a test on the packaged chip based on a first test environment, and obtaining a first trimming value according to the test result; Step 2: Burning the first trimming value into the first trimming bit integrated in the packaged chip to achieve a one-time trimming of the packaged chip; Step 3, reading the first trimming value recorded in the first trimming bit of the packaged chip and performing a secondary test on the packaged chip based on a second test environment, and obtaining a second trimming value based on the secondary test result and the first trimming value; Step 4, burning the second trimming value into the second trimming bit integrated in the packaged chip to achieve secondary trimming of the packaged chip; Wherein, the step 1 further includes: Step 11: Preset 2 for the packaged chip N-1 +1 to 2 N gears, and each gear corresponds to two fixed gear values ​​that match the test results to identify the gear range, and each of the gears corresponds to one of the N-bit binary adjustment values; Step 12: Compare the primary test result with the fixed gear value. If the primary test result falls within the gear range, obtain the gear range of the primary test result. Step 13: Determine the gear according to the gear range of the first test result and generate the first adjustment value.

2. The multi-environment packaged chip testing method according to claim 1, characterized in that: The step 12 further comprises: Step 1201: If the primary test result falls outside the gear range, a third trimming value is calculated and generated, and the third trimming value is burned into a third trimming bit integrated in the packaged chip to implement pre-trim of the packaged chip. Step 1202: Based on the pre-adjustment, a test result of the chip obtained in the first test environment is adjusted to fall within the gear range; Step 1203: retest the packaged chip based on the first test environment and obtain a test result.

3. The multi-environment packaged chip testing method according to claim 1, characterized in that: The step 3 further comprises: A property value is preset for the packaged chip, and a second trimming value is calculated according to the preset property value, the first trimming value and a secondary test result.

4. A multi-environment packaged chip testing method according to any one of claims 1 to 3, characterized in that: The first test environment and the second test environment are respectively a first constant temperature and a second constant temperature, and the first test result and the second test result are respectively a first test voltage and a second test voltage.

5. The multi-environment packaged chip testing method according to claim 4, characterized in that: There is a linear relationship between the constant temperature and the test voltage, and the calculation formula is V=kT+b; Among them, V is the test voltage, k is the preset property value of the packaged chip, T is the constant temperature, b is the relationship coefficient between the constant temperature and the test voltage, and k and b are fixed values ​​used to identify the performance of the packaged chip.

6. The multi-environment packaged chip testing method according to claim 5, characterized in that: Step 31 , obtaining a first trimming value, and restoring the gear voltage V′1 of the first test voltage V1 according to the first trimming value; Step 32, calculating a second trimmed voltage V2' based on the preset attribute value k and the first trimmed value, wherein the calculation formula for the second trimmed voltage is V2'=k(T2-T1)+V'1, where V2' is the second trimmed voltage, T2 is the second constant temperature, T1 is the first constant temperature, and V'1 is the voltage level of the first test voltage; Step 33: compare the second trimming voltage with a second test voltage and generate a second trimming value.

7. A packaged chip comprising an input module, a trimming module, and an output module, characterized in that: The input module is used to input the trimming value obtained by testing the packaged chip into the trimming module, wherein the trimming value includes a first trimming value, and the first trimming value is generated by the following method: Step 11, preset 2 for the packaged chip N-1 +1 to 2 N gears, and each gear corresponds to two fixed gear values ​​that match the test results to identify the gear range, and each of the gears corresponds to one of the N-bit binary adjustment values; step 12, comparing a test result obtained by performing a test on the packaged chip based on the first test environment with the fixed gear value, and if the test result falls within the gear range, obtaining the gear range of the test result; step 13, determining the gear according to the gear range of the test result and generating the first adjustment value; The trimming module is used to burn the trimming value into the trimming bit integrated inside the chip to achieve trimming of the packaged chip, wherein the first trimming value is burned into the first trimming bit integrated inside the packaged chip; The output module is configured to recognize that the packaged chip is located in a second test environment, read the first trimming bit, and output the first trimming value.

8. The packaged chip according to claim 7, characterized in that: The packaged chip is also used to implement a multi-environment packaged chip testing method according to any one of claims 1 to 6.

9. A packaged chip according to claim 7 or 8, characterized in that: The packaged chip is a temperature sensor chip.

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