Memory Subsystem Memory Bank Search Component

Abstract

This application relates to a memory bank search component of a memory subsystem. A logical array having a plurality of memory banks is constructed, where each of the plurality of memory banks is divided into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The position of a data component stored in a memory component is determined by locating an element stored in a specific slot of the plurality of slots; and performing a corrective search on the located element in the specific slot to locate a specific element. The data component is accessed based on the position of the specific element.

Description

[0001] Priority Information

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 132,178, filed on December 30, 2020, the content of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to memory bank search components of a memory subsystem. Background Art

[0004] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0005] Aspects of the present disclosure provide a system that includes: a memory component; and a processing device operatively coupled to the memory component to: construct a logical array having a plurality of memory banks, wherein each of the plurality of memory banks is divided into a plurality of slots; store a plurality of elements corresponding to a plurality of data components stored in the memory component in the plurality of slots of each of the plurality of memory banks of the logical array; determine a location of a data component stored in the memory component by: locating an element stored in a particular slot of the plurality of slots; and performing a corrective search on the located element in the plurality of slots of each of the plurality of memory banks to locate a particular element; and access the data component stored in the memory component based on a location of the particular element.

[0006] Another aspect of the present disclosure provides a method that includes: constructing a logical array having a plurality of memory banks, wherein each of the plurality of memory banks is divided into a plurality of slots; dividing each slot of the plurality of slots of each of the plurality of memory banks of the logical array into rows; storing elements corresponding to data components in a memory component of a memory subsystem in each row of the plurality of slots of each of the plurality of memory banks of the logical array; determining two or more elements associated with a data component stored in the memory component by: searching for the two or more elements in each of the plurality of slots; and performing a corrective search by searching in parallel for a particular one of the two or more elements in rows of the plurality of memory banks; and accessing the data component stored in the memory component.

[0007] Another aspect of the present disclosure provides a non - transitory computer - readable storage medium that includes instructions which, when executed by a processing device, cause the processing device to: construct a logical array having a plurality of memory banks, where each of the plurality of memory banks is divided into a plurality of slots and is associated with a single data port; store different elements in each slot of the plurality of memory banks of the logical array, where each different element corresponds to a different data component stored in a memory component of a memory subsystem; determine a particular element associated with a particular data component stored in the memory component by: locating two or more elements in the plurality of memory banks; and searching each slot of the plurality of memory banks containing the two or more elements in parallel to locate the particular element associated with the particular data component stored in the memory component; and access the data component stored in the memory component. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be regarded as limiting the present disclosure to specific embodiments, but are for explanation and understanding only.

[0009] Figure 1 Illustrate an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

[0010] Figure 2 is a flowchart of an example method of operating a memory bank search component in accordance with some embodiments of the present disclosure.

[0011] Figure 3 Illustrate an example of a logical array having a plurality of memory banks in accordance with some embodiments of the present disclosure.

[0012] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to a memory bank search component of a memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below. Generally, a host system can utilize a memory subsystem that includes one or more components (e.g., a memory device that stores data). The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem. Figure 1 Describe examples of storage devices and memory modules.

[0014] Conventional memory subsystems may utilize traditional binary search methods to search for (e.g., find) data stored in the memory subsystem. Traditional binary search may search for data in a sorted list. For example, traditional methods of searching for data may include repeatedly dividing the list in half until the possible location of the data is narrowed down. However, traditional binary search methods may increase the time taken to search for and locate data stored in the memory subsystem, which may degrade the performance of the memory subsystem.

[0015] To improve the performance of the memory subsystem (e.g., reduce search time), conventional methods may use multiple data ports to stripe data across different data ports. However, doing so may increase the cost and / or complexity of the memory subsystem, and / or reduce the amount of storage space available in the memory subsystem.

[0016] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that utilizes a logical array comprising multiple individual data ports to improve search speed in the memory subsystem. In many cases, by dividing an individual data port into slots and storing elements of the logical array in the slots of the individual data port, an individual data port of the memory subsystem may include multiple storage spaces within a particular individual data port. Components of the memory subsystem may perform parallel searches of the slots to quickly locate data in the memory subsystem. Thus, the memory subsystem may quickly access data components stored in the memory subsystem without causing data replication, which may reduce the cost and / or complexity of the memory subsystem, and / or increase the amount of storage space available in the memory subsystem.

[0017] Figure 1 An example computing environment 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] Memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a single memory subsystem 110 is illustrated. For example, the host system 120 uses the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0020] The host system 120 can be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation means), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device. The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0021] The memory device can include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) can be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0022] Examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory. Each of the memory devices 130 may include one or more memory cell arrays. Memory cells may include single-level cells (SLCs) that can store one bit per cell, multi-level cells (MLCs) that can store two bits per cell, three-level cells (TLCs) that can store three bits per cell, four-level cells (QLCs) that can store four bits per cell, and / or five-level cells (PLCs) that can store five bits per cell, etc. As used herein, the term "multi-level cell" is used to refer to cells configured to store more than one bit per cell (e.g., MLCs, TLCs, QLCs, PLCs, etc.). In some embodiments, a particular memory component may include an SLC portion and an MLC portion, TLC portion, QLC portion, and / or PLC portion of memory cells. Each of the memory cells may store one or more data bits used by the host system 120. Additionally, the memory cells of the memory device 130 may be grouped into memory pages or memory blocks, which may refer to the units of the memory component for storing data.

[0023] Although non-volatile memory components such as NAND type flash memory are described, the memory device 130 may be based on any other type of non-volatile memory, e.g., read-only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), nor flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory may perform in-place write operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells.

[0024] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0025] The memory subsystem controller 115 can be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120).

[0026] In some embodiments, the local memory 119 can include memory registers for storing memory pointers, fetched data, etc. The local memory 119 can also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in Figure 1 has been illustrated as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 can not include the memory subsystem controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0027] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical block address and the physical block address associated with the memory device 130. The memory subsystem controller 115 can further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system 120 into command instructions for accessing the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0028] The memory subsystem 110 can also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0029] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0030] Memory subsystem 110 includes a memory bank search component 113 that may store elements (e.g., indices) corresponding to data in the memory banks of a logical array. In some embodiments, memory subsystem controller 115 includes at least a portion of memory bank search component 113. For example, memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, memory bank search component 113 is part of host system 110, an application, or an operating system. In some embodiments, memory bank search component 113 may be included in local media controller 135 of memory device 130.

[0031] Memory bank search component 113 may construct a logical array of memory banks. Memory bank search component 113 may divide each memory bank into slots to store an array of elements. In some embodiments, each element may include a key and a corresponding value. Each element may correspond to a data component stored in memory device 130. Memory bank search component 113 may determine the location of a data component stored in memory device 130. For example, memory bank search component 113 may locate the approximate location of an element stored in a slot of a memory bank. The element may correspond to a data component stored in memory device 130, which may provide the location of the data component. After the approximate location of the element has been determined, memory bank search component 113 may perform a corrective search on the data component within the slot on a particular memory bank. Performing a corrective search on the approximate location of the element may provide memory bank search component 113 with the information needed to determine the location of the data component and access the data component stored at memory device 130. Other details regarding the operation of memory bank search component 113 are described below.

[0032] For example, memory bank search component 113 may construct a logical array having multiple memory banks, where each of the memory banks may be divided into slots. In some embodiments, each of the memory banks may be associated with a single data port. The single data port associated with each of the memory banks may include a small random access memory (RAM). In some embodiments, the single data port associated with each of the memory banks may be one of three or more data ports of memory subsystem 110. Memory bank search component 113 may also store multiple elements corresponding to multiple data components in memory device 130 in the slots of each of the memory banks of the logical array. For example, each different element may correspond to a different data component of memory device 130.

[0033] To determine the location of data components stored in the memory device 130, the memory bank search component 113 may locate elements stored in a particular slot and perform a corrective search on the located elements in the slots of each memory bank to locate a particular element. In some embodiments, the memory bank search component 113 may locate a particular element in one of the memory banks by processing each memory bank simultaneously. Once the particular element is determined, the memory bank search component 113 may access the data components stored at the memory device 130.

[0034] In some embodiments, the memory banks of a logical array may be divided into three or more slots (e.g., the slots may include three or more slots). Additionally, each slot may be divided into two or more rows, and each corresponding element may be stored in a different row. For example, elements may be stored in ascending or descending order based on the key of the element. However, the present disclosure is not limited thereto. For example, in some embodiments, elements may be stored in ascending order based on the key of the element. In some embodiments, the memory bank search component 113 may search each slot in parallel to locate a particular element. For example, the memory bank search component 113 may perform a corrective search by searching the rows of a particular slot in parallel to locate a particular element.

[0035] In some embodiments, the memory bank search component 113 may identify a particular element by locating the lowest numbered key in the memory bank. That is, two or more elements may be identified by locating the lowest numbered key in the memory bank. For example, the memory bank search component 113 may identify the element associated with the data component by identifying the lowest numbered key within a slot (e.g., the approximate location of a row). If there is a duplicate of the lowest numbered key, the memory bank search component 113 may return the key with the lowest index number. That is, the location of the element may be approximated by identifying the row of the memory bank. As described herein, the memory bank search component 113 may perform a corrective search to determine a particular element based on the identified row and access the data components stored at the memory device 130 based on the determined row. In some embodiments, performing the corrective search may include performing two or more sensing operations (e.g., reads) on the slot in which the element is located. For example, the corrective search may include performing two or more reads on the rows of the memory bank to determine the particular element associated with the data component.

[0036] Figure 2is a flowchart of an example method 250 of operating a memory bank search component according to some embodiments of the present disclosure. Method 250 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 250 is performed by the Figure 1 memory bank search component 113. Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, all processes are not required in every embodiment. Other process flows are possible.

[0037] At operation 251, the processing device may construct a logical array of memory banks having memory banks divided into slots. The memory banks of the logical array may be used to store elements corresponding to data components stored in a memory device (e.g., Figure 1 memory device 130) as previously described herein. Each memory bank may be split to form a plurality of slots. In some embodiments, each memory bank may be divided into three or more slots. The memory banks may be divided into the same number of slots or different numbers of slots. For example, in a non-limiting example, the first and second memory banks may be divided into three slots. In another non-limiting example, the first memory bank may be divided into three slots and the second memory bank may be divided into four slots. The slots within each memory bank may be used to store information. For example, each memory bank may store a plurality of information groups that may be accessed individually.

[0038] At operation 252, the processing device may divide each slot of each memory bank of the logical array into rows. In some embodiments, the logical array may be fully striped across the memory banks. For example, the logical array may include three memory banks and may be fully striped across the three memory banks. The rows of the logical array may spread across the memory banks of the logical array. In some embodiments, an element may be accessed from any position within a row. In some embodiments, each slot may be divided into two or more rows. Each slot of the memory bank may be divided (e.g., partitioned) into rows to increase the storage space of each memory bank. For example, the memory bank may store multiple information groups in a slot of the memory bank by storing each corresponding information group in a different row, thereby increasing the amount of information stored in each slot of the memory bank compared to a memory bank divided into slots and / or rows. Additionally, increasing the amount of information in the memory bank may reduce the number of memory banks that need to be searched to access a data component stored in the memory device, which may reduce the search time for the data component compared to a memory bank with reduced storage capacity.

[0039] At operation 253, the processing device may store elements corresponding to data components stored in the memory device in each row of each slot. As discussed herein, each row may be used to separately store information within a slot of the memory bank. For example, the processing device may store elements in each row. For example, each slot may include multiple rows, where each row may include an element. In some embodiments, the processing device may perform a faster search for a data component when the element corresponding to the data component is stored in a row within the memory bank compared to a memory bank that does not store elements in the rows of the memory bank. In some embodiments, the elements may be stored in ascending order of the corresponding memory bank. In some embodiments, the elements may be stored in ascending or descending order of the corresponding memory bank.

[0040] At operation 254, the processing device may search for two or more elements in a slot of the memory bank. For example, the processing device may search multiple slots in the memory bank to find the approximate location of a particular element. That is, the processing device may locate two or more elements to locate a particular element corresponding to a data component. In some embodiments, the processing device may locate the approximate location of a particular element by searching the memory banks in parallel (e.g., simultaneously) compared to searching the memory banks one at a time. In some embodiments, searching for two or more elements within a row of the memory bank may reduce the number of elements searched when accessing a data component. For example, the processing device may limit and narrow the search for a particular element within the logical array to reduce the number of elements searched.

[0041] At operation 255, the processing device may perform a calibration search by searching in parallel for a particular element among two or more elements in a row of a memory bank. For example, the processing device may search in parallel rows of slots to precisely locate the actual position of a particular element corresponding to a particular data component. That is, based on the approximate positions of two or more elements, the calibration search may determine the actual position of the particular element and thus determine the corresponding data component. For example, the approximate position of the particular element may determine the memory bank and / or slot in which the particular element is located, but may not determine the particular row in which the particular element is located. The processing device may perform two or more reads on the slot to perform the calibration search. For example, the row of the slot may be read two or more times to determine the particular element and thus determine the corresponding data component.

[0042] In some embodiments, an element may include a key and a corresponding value. The memory bank search component may search for the lowest numbered key in each element to determine the approximate positions of two or more elements. For example, when a series of keys (e.g., [10, 8]) are provided to the processing device, a search through the rows may locate all keys within the range (e.g., keys that include ten (10), eight (8), and all numbers in between). The processing device may select the lowest key within the range to locate two or more elements and / or the particular element. If there is a duplicate of the lowest key, the processing device may select the lowest key with the lowest array index to locate the element. The corresponding value of the lowest key of the particular element may provide the location of the data component in the memory device. That is, the processing device may use the element to determine the location of the data component in the memory device.

[0043] At operation 256, the processing device may access the data component stored in the memory device. That is, once the location of the data component is determined, the processing device may access the data component from the stored location.

[0044] Figure 3 An example of a logic array 340 having multiple memory banks 341 in accordance with some embodiments of the present disclosure is illustrated. The logic array 340 may be constructed by, for example Figure 1 a memory bank search component 113. In Figure 3In the example described, the logical array 340 has been striped into three memory banks 341-1, 341-2, and 341-3 (e.g., the memory banks 341-1, 341-2, and 341-3 may be collectively referred to as the memory bank 341). However, the present disclosure is not limited thereto. For example, the logical array may be striped into more or fewer memory banks. In some embodiments, each memory bank 341 has the ability to store twelve (12) elements. For example, the elements are striped across the logical array, with twelve (12) elements stored in each of the memory banks 341-1, 341-2, and 341-3.

[0045] In some embodiments, each memory bank 341 in the logical array may be divided into three or more slots 342. For example, the memory bank 341-1 may be divided into slots 342-1A, 342-2A, and 342-3A; the memory bank 341-2 may be divided into slots 342-1B, 32-2B, and 342-3B; and the memory bank 341-3 may be divided into slots 342-1C, 342-2C, and 342-3C (e.g., the slots 342 may be collectively referred to as the slots 342-1A, 342-2A, 342-3A, 342-1B, 342-2B, 342-3B, 342-1C, 342-2C, and 342-3C). Each slot 342 may store an element corresponding to a data component stored in a memory device (e.g., Figure 1 the memory device 130). The memory bank search component 113 may search for elements in the slots 342 of the memory bank 341.

[0046] In some embodiments, each memory bank 341 may be connected to a data port. For example, the number of memory banks 341 may be equal to the number of data ports. The data port may be coupled to any slot of the memory bank 341 to which it is connected. Additionally, each memory bank 341 may include an address port. In some embodiments, each address port may be connected to the memory bank to receive elements and / or send elements to the row 344 or each memory bank 341.

[0047] The slots 342 of the memory bank 341 can be divided into rows 344. For example, the slots 342-1A, 342-2A, and 342-3A of the memory bank 341-1 can each be divided into rows 344-1D, 344-2D, 344-3D, and 344-4D; the slots 342-1B, 342-2B, and 342-3B of the memory bank 341-2 can be divided into rows 344-1E, 344-2E, 344-3E, and 344-4E; and the slots 342-1C, 342-2C, and 342-3C can be divided into rows 344-1F, 344-2F, 344-3F, and 344-4F (e.g., the rows 344 can be collectively referred to as rows 344-1D, 344-2D, 344-3D, 344-4D, 344-1E, 344-2E, 344-3E, 342-4E, 344-1F, 344-2F, 344-3F, and 344-4F). In some embodiments, the processor can store elements in each row 344 of each slot 342 of the memory bank 341.

[0048] In some embodiments, the memory bank search component can search for elements in each memory bank (341-1, 341-2, and 341-3) simultaneously. For example, the memory bank search component can search for two or more elements in each slot 342 of each memory bank simultaneously. For example, the memory bank search component can search the slots 342-1A, 342-2A, and 342-3A of the memory bank 341-1, the slots 342-1B, 342-2B, and 342-3B of the memory bank 341-2, and the slots 342-1C, 342-2C, and 342-3C of the memory bank 341-3 to determine the approximate location of a particular element. The memory bank search component can determine the approximate location of a particular element by locating two or more elements during the search of the memory bank 341, and these approximate locations of the elements can be stored in a queue. As used herein, the term "queue" refers to a location for storing information.

[0049] For example, in some embodiments, the search of the slots 342 of the memory bank 341 can return the approximate location (e.g., row) of a particular element. For example, if the approximate search returns the approximate location as S (where S represents a particular row within the memory bank 341), the location of the element can be at S or S-1. That is, the approximate search can provide results that are too high and / or too low (e.g., rows). In some embodiments, an auxiliary correction search can search for the element in all possible rows (e.g., row S, row S+1, and row S-1). For example, if the approximate search returns the approximate location of S, then:

[0050]

[0051] Where α is a memory bank, h is the element of each row, T is the element being searched, and A is the logical array being searched.

[0052] The above equation allows approximating the position of a specific element. In another embodiment, the approximate position determined by the search may be the midpoint position of the element. For example, the search of slot 342 may find the row closest to the position of the specific element. In some embodiments, the memory bank search component may find multiple midpoint positions in a single search. For example, the memory bank search component may perform a search to locate a first midpoint and then perform a second search to locate a second midpoint. The memory bank search component may utilize the midpoint positions to determine the actual position of the specific element in the refinement search.

[0053] In some embodiments, once the approximate position of the element (e.g., row and / or slot) is determined, the memory bank search component may perform a refinement search on the memory bank (e.g., 341-1, 341-2, and / or 341-3) to determine the position of the specific element within the memory bank (e.g., 341-1, 341-2, and / or 341-3). The refinement search may search for potential position matches (e.g., rows of the memory bank) stored in a queue. For example, the memory bank search component may perform the refinement search by searching in parallel the rows (e.g., 344-1D, 344-2D, 344-3D, and / or 344-4D) of the memory bank (e.g., 341-1) identified during the search for the approximate position of the element. For example, if the approximate search identifies slot 1 342-1A, row 344-1D of memory bank 341-1 and slot 1 342-1A, row 344-2D of memory bank 341-1, the memory bank search component may search in parallel slot 1 342-1A, row 344-1D of memory bank 341-1 and slot 1 342-1A, row 344-2D of memory bank 341-1 to perform the refinement search based on the information received during the approximate search.

[0054] In some embodiments, the memory bank search component may use an algorithm to perform a refinement search on the memory bank and search in parallel the rows 344 of the memory bank (e.g., 341-1, 341-2, or 341-3). For example, the memory bank search component may use the following algorithm to perform the refinement search:

[0055]

[0056] It can simplify

[0057]

[0058] It can simplify

[0059]

[0060] where k is the memory read latency, d is the additional pipeline stage, α is the number of memory banks, and n is defined as the minimum value that satisfies 2 (n+1) -2 ≥ α ≥ 2 n -1, where it should be noted that n > 1.

[0061] The memory bank search component can determine the element with the lowest key stored in the queue during the correction search and identify the corresponding data component. The memory bank search component can use the identified specific element to access the data component stored in the memory device. That is, the element with the lowest key can be used to determine the position of the data component in the memory subsystem.

[0062] In some embodiments, dividing the slots 342 of the memory bank 341 into rows 344 can increase the storage capacity of each memory bank and the logical array compared to memory banks that are not divided into slots and / or rows. For example, since the slots are divided into rows, each memory bank can store multiple elements in the slots, thereby increasing the storage capacity of the memory bank. Increasing the storage capacity of each memory bank can reduce the searched elements to a single logical array (e.g., array 340). In addition, increasing the storage capacity of the memory bank can also reduce the number of memory banks to be searched, which can reduce the search time of the elements compared to memory banks with reduced storage capacity. In addition, searching the rows 344 of the memory banks 341-1, 341-2, or 341-3 in parallel can increase the search speed for locating a specific element and / or two or more elements compared to searching the rows 344 individually (e.g., not in parallel).

[0063] Figure 4 is a block diagram of an example computer system 400 in which embodiments of the present disclosure may operate. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 the memory subsystem 110), or may be used to perform the operations of the controller (e.g., execute an operating system to perform the operations corresponding to Figure 1 the memory bank search component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0064] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch, or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Additionally, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute one (or more) set of instructions to perform any one or more of the methods discussed herein.

[0065] Example computer system 400 includes a processing device 402, a main memory 404 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418 that communicate with each other via a bus 430.

[0066] Processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 402 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 can further include a network interface device 408 to communicate over a network 420.

[0067] Data storage system 418 can include a machine-readable storage medium 424 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 426 or software embodying any one or more of the methods or functions described herein. The instructions 426 can also reside, completely or at least partially, within main memory 404 and / or within processing device 402 during execution by computer system 400, which main memory 404 and processing device 402 also constitute machine-readable storage media. Machine-readable storage medium 424, data storage system 418, and / or main memory 404 can correspond to Figure 1 memory subsystem 110.

[0068] In one embodiment, the instructions 426 include those for implementing corresponding to memory bank search component 413 (e.g., Figure 1instructions for the functionality of the memory bank search component 113). Although the machine-readable storage medium 424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0069] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm, as used herein and generally, is conceived of as a self-consistent sequence of operations that produce a desired result. Operations are those operations that require physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0070] However, it should be borne in mind that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that controls and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0071] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus for performing the method. The structure of various of these systems will be presented as will be shown in the description below. In addition, no specific programming language has been described for the present disclosure. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0073] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0074] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A computer system (100, 400), comprising: A memory component (130); And A processing device (115, 402) operably coupled to the memory component (130) to: Construct a logical array (340) having a plurality of memory banks (341) separate from the memory component (130), wherein each of the plurality of memory banks (341) is divided into a plurality of slots (342), and each of the plurality of slots (342) in each of the plurality of memory banks (341) is divided into rows (344); Store a plurality of elements corresponding to a plurality of data components stored in the memory component (130) in the plurality of slots (342) of each of the plurality of memory banks (341) of the logical array (340); Determine the location of a data component stored in the memory component (130) by: Searching for an element stored in a particular slot (342) of the plurality of slots (342) to determine which of the plurality of slots (342) contain the element; Performing a corrective search on the rows of the slots of the plurality of slots (342) that contain the element to locate a particular element by locating the lowest numbered key within the element, wherein the particular element is associated with the lowest numbered key, and wherein the lowest numbered key has a corresponding value, and the corresponding value is stored in the element having the lowest numbered key; and Determining the location of the data component by using the corresponding value stored in the element having the lowest numbered key; Accessing the data component stored in the memory component (130) based on the location.

2. The computer system according to claim 1, wherein each of the plurality of memory banks is divided into three or more slots.

3. The computer system according to claim 1, wherein the processing device is further configured to: Store each corresponding element of the plurality of elements in a different row (344).

4. The computer system according to claim 1, wherein the processing device is further configured to perform the corrective search by searching in parallel the rows of the slots of the plurality of slots that contain the element to locate the particular element.

5. The computer system according to claim 1, wherein each of the plurality of memory banks is associated with a single data port.

6. The computer system according to claim 5, wherein the single data port associated with each of the plurality of memory banks includes a random access memory RAM (140).

7. The computer system according to claim 5, wherein the single data port associated with each of the plurality of memory banks is one of three or more data ports of the computer system.

8. A method (250) for memory operation, comprising: Construct a logic array (340) having a plurality of memory banks (341), wherein each of the plurality of memory banks (341) is divided into a plurality of slots (342); Divide each slot (342) among the plurality of slots (342) of each of the plurality of memory banks (341) of the logic array (340) into rows (344); Store elements corresponding to data components in a memory component (130) of a memory subsystem (110) in each row (344) of each of the plurality of slots (342) of each of the plurality of memory banks (341) of the logic array (340), wherein the memory component (130) is separate from the plurality of memory banks (341) of the logic array (340); Determine two or more elements associated with a data component stored in the memory component (130) by: Searching for the two or more elements in each of the plurality of slots (342) to determine which of the plurality of slots (342) contain the two or more elements; and Performing a corrective search on the rows (344) of the slots among the plurality of slots (342) that contain the two or more elements by locating the lowest numbered key among the two or more elements to parallel search for a particular one of the two or more elements in the rows (344) of the slots that contain the two or more elements, the particular element being associated with the lowest numbered key, wherein the lowest numbered key has a corresponding value, and the corresponding value is stored in the element having the lowest numbered key; Determine the location of the data component by using the corresponding value stored in the element having the lowest numbered key; And Access the data component stored in the memory component (130).

9. The method of claim 8, further comprising including a key and a corresponding value in each element stored in each row.

10. The method of claim 9, further comprising sorting each element stored in each row in ascending or descending order based on the key.

11. The method of claim 8, wherein performing the corrective search includes performing two or more sensing operations on the memory bank.

12. The method of claim 8, further comprising determining a plurality of rows to approximate the particular element.

13. A non-transitory computer-readable storage medium (424) comprising instructions (426) that, when executed by a processing device (115, 402), cause the processing device (115, 402) to: Construct a logic array (340) having a plurality of memory banks (341), wherein each of the plurality of memory banks (341) is divided into a plurality of slots (342) and associated with a single data port, and wherein each of the plurality of slots (342) of each of the plurality of memory banks (341) is divided into rows (344); Store different elements in each slot (342) of the plurality of memory banks (341) of the logic array (340), wherein each different element corresponds to a different data component stored in a memory component (130) of a memory subsystem (110), and wherein the memory component (130) is separate from the plurality of memory banks (341) of the logic array (340); Determine a specific element associated with a specific data component stored in the memory component (130) by: Searching for two or more elements in a specific slot among the plurality of slots (342) to determine which of the plurality of slots (342) contain the two or more elements; and Performing a corrective search on the rows of the slots among the plurality of slots (342) that contain the two or more elements by locating the lowest numbered key among the two or more elements to parallel search each of the plurality of slots (342) that contain the two or more elements to locate the specific element associated with the specific data component stored in the memory component (130), wherein the specific element is associated with the lowest numbered key, and wherein the lowest numbered key has a corresponding value, and the corresponding value is stored in the element having the lowest numbered key; Determine the location of the specific data by using the corresponding value stored in the element having the lowest numbered key; And Access the data component stored in the memory component (130).

14. The non-transitory computer-readable storage medium of claim 13, wherein the processing device is further configured to perform the corrective search by performing two or more sensing operations on the slots that contain the two or more elements to locate the specific data component.

15. The non-transitory computer-readable storage medium of claim 13, wherein the processing device is further configured to locate the specific element in one of the plurality of memory banks by simultaneously processing each of the plurality of memory banks.

16. The non-transitory computer-readable storage medium of claim 13, wherein each different element includes a key and a corresponding value.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing device is further configured to: Store the elements in the rows (344) in ascending order of the keys.

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