Electronic device and method for solving transient pulse output of communication interface

Abstract

The present invention provides an electronic device and method for resolving transient pulse output issues with a communication interface. The electronic device includes a reset controller, a communication interface controller, and a communication interface circuit. The reset controller outputs a reset signal and a reset event link signal in response to a reset instruction. The communication interface controller outputs a reset control signal in response to the reset signal. The communication interface circuit receives the reset event link signal, causing the communication interface circuit to store the voltage state of the currently transmitted communication signal in preparation for entering an input mode. The communication interface circuit also receives the reset control signal, causing the communication interface circuit to reset. The communication interface circuit enters the input mode earlier than the time when the communication interface circuit is reset.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device and a method for solving transient pulse output problems of a communication interface. Background Art

[0002] In a general-purpose input / output (GPIO) communication interface, when the GPIO circuit receives a reset command from the GPIO controller, it switches from output mode to input mode. During this mode transition, when the GPIO circuit performs a logical reset, the speeds at which electrical signals travel between the GPIO controller and the GPIO circuit differ. This can cause transient pulses in the GPIO interface, potentially causing system malfunctions. If the GPIO circuit enters input mode later than the time it performs the reset, a transient pulse may also occur. Summary of the Invention

[0003] An electronic device for resolving transient pulse output issues on a communication interface according to an embodiment of the present invention includes a reset controller, a communication interface controller, and a communication interface circuit. The reset controller outputs a reset signal and a reset event link signal in response to a reset instruction. The communication interface controller outputs a reset control signal in response to the reset signal. The communication interface circuit receives the reset event link signal, causing the communication interface circuit to store the voltage state of the currently transmitted communication signal in preparation for entering an input mode. The communication interface circuit also receives the reset control signal, causing the communication interface circuit to reset. The communication interface circuit enters input mode earlier than the time at which the communication interface circuit is reset.

[0004] In the electronic device described above, the communication interface circuit includes an output terminal, an output enable terminal, an input terminal, and an input / output terminal. When the voltage at the output enable terminal changes from a high level to a low level, the communication interface circuit enters an input mode. When the reset control signal changes from a high level to a low level, the communication interface circuit is reset.

[0005] In the electronic device described above, the communication interface circuit further comprises an AND gate, wherein the output terminal and the output enable terminal of the communication interface circuit serve as inputs of the AND gate, the input and output terminals of the communication interface circuit serve as outputs of the AND gate, and the input terminal of the communication interface circuit is coupled to the input and output terminals.

[0006] In the electronic device as described above, the time point at which the voltage of the output enable terminal of the communication interface circuit changes from a high level to a low level is earlier than the time point at which the reset control signal changes from a high level to a low level.

[0007] In the electronic device as described above, the communication interface circuit includes an output terminal, an output enable terminal, an input terminal, an input-output terminal, a latch enable terminal, a first flip-flop, a second flip-flop, a first multiplexer, a second multiplexer, an AND gate, and a delay device.

[0008] In the electronic device described above, the latch enable terminal is coupled to the clock input terminals of the first and second flip-flops, and the input of the delay device. The output of the delay device is coupled to the control terminals of the first and second multiplexers. The data input terminal of the first flip-flop is coupled to the output terminal of the communication interface circuit, and the output result terminal of the first flip-flop is coupled to a first input of the first multiplexer. The data input terminal of the second flip-flop is coupled to the output enable terminal of the communication interface circuit. The output result terminal of the second flip-flop is coupled to a third input of the second multiplexer. The output terminal of the communication interface circuit is coupled to a second input of the first multiplexer. The output enable terminal of the communication interface circuit is coupled to a fourth input of the second multiplexer. The outputs of the first and second multiplexers serve as inputs of an AND gate. The input and output terminals of the communication interface circuit serve as the outputs of the AND gate, and the input terminal of the communication interface circuit is coupled to the input and output terminal.

[0009] In the electronic device described above, the latch enable terminal of the communication interface circuit receives a reset event link signal. When the communication interface controller changes the reset event link signal from a low level to a high level, the first flip-flop and the second flip-flop store the voltage states of the current output terminal and the output enable terminal, causing the first multiplexer to output the current output terminal voltage state stored by the first flip-flop to the AND gate, and the second multiplexer to output the current output enable terminal voltage state stored by the second flip-flop to the AND gate.

[0010] In the electronic device as described above, the time point when the reset control signal changes from a high level to a low level falls during the period when the reset event link signal maintains a high level, so that the voltage states of the output end and the output enable end of the communication interface circuit remain consistent before and after the communication interface circuit is reset.

[0011] A method for resolving transient pulse output issues in a communication interface according to an embodiment of the present invention is applicable to an electronic device for transmitting communication signals. The electronic device includes a reset controller, a communication interface controller, and a communication interface circuit. The method includes: the reset controller outputting a reset signal and a reset event link signal in response to a reset instruction; the communication interface controller outputting a reset control signal in response to the reset signal; the communication interface circuit receiving the reset event link signal, causing the communication interface circuit to store the voltage state of the currently transmitted communication signal in preparation for entering an input mode; and the communication interface circuit receiving the reset control signal, causing the communication interface circuit to reset. The communication interface circuit enters the input mode earlier than the time when the communication interface circuit is reset.

[0012] The method as described above also includes: when the reset controller changes the reset event link signal from a low level to a high level, the communication interface circuit stores the voltage state of the transmitted communication signal; and during the period when the reset controller maintains the reset event link signal at a high level, the communication interface controller changes the reset control signal from a high level to a low level, so that the voltage state of the communication signal of the communication interface circuit can be maintained consistent before and after the time point when the communication interface circuit is reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention.

[0014] Figure 2 FIG. 1 is a signal timing diagram of the electronic device 100 according to an embodiment of the present invention.

[0015] Figure 3 FIG. 3 is a schematic diagram of an electronic device 300 according to an embodiment of the present invention.

[0016] Figure 4 FIG. 4 is a schematic diagram of an electronic device 400 according to an embodiment of the present invention.

[0017] Figure 5 For the embodiment of the present invention Figure 1 Flowchart of a method for the electronic device 100 to resolve transient pulse output of a communication interface.

[0018] Figure Number:

[0019] 100: Electronic devices

[0020] 102: Reset controller

[0021] 104: Communication interface controller

[0022] 106: Communication interface circuit

[0023] 110: AND gate

[0024] 112: Output

[0025] 114: Output enable terminal

[0026] 116: Input terminal

[0027] 118: Input and output terminals

[0028] 120: Reset command

[0029] 122: Reset signal

[0030] 124: Reset control signal

[0031] 130: Reset event link signal

[0032] 200: Transient pulse

[0033] t1, t2, t3: time points

[0034] 300: Electronic devices

[0035] 302: Flip-flop

[0036] 304: Flip-flop

[0037] 306: Multiplexer

[0038] 308: Multiplexer

[0039] 310: Delay

[0040] 320: latch enable terminal

[0041] 330: Communication interface circuit

[0042] 400: Electronic devices

[0043] 402: Communication interface controller

[0044] 408: Multiplexer

[0045] 410:GPIO controller

[0046] 412:I2C controller

[0047] 414:SPI controller

[0048] 420: Control signal

[0049] S500, S502, S504: Steps

[0050] S506, S508, S510: Steps DETAILED DESCRIPTION

[0051] The present invention is described with reference to the accompanying drawings, in which like reference numerals throughout the drawings indicate similar or identical elements. The drawings are not drawn to scale and are provided solely to illustrate the invention. Some embodiments of the invention are described below as references to illustrative applications. This means that many specific details, relationships, and methods are set forth to provide a complete understanding of the invention. However, those skilled in the art will recognize that the invention can still be practiced without one or more of the specific details or with alternative methods.

[0052] In other examples, well-known structures or operations are not described in detail to avoid obscuring the present invention. The present invention is not limited by the order of the acts or events described; some acts may occur in a different order or concurrently with other acts or events. Furthermore, not all acts or events described need to be performed in the same manner as in the prior invention.

[0053] Figure 1 FIG is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 100 includes a reset controller 102, a communication interface controller 104, and a communication interface circuit 106. The reset controller 102 receives a reset command 120 from a central processing unit (CPU) (not shown) in the system in which it is located. The reset controller 102 first determines whether the content of the reset command 120 is a reset event. If the reset controller 102 determines that the content of the reset command 120 is indeed a reset event, the reset controller 102 outputs a reset signal 122 to the communication interface controller 104 according to the reset command 120, and simultaneously outputs a reset event link signal 130 to the communication interface circuit 106.

[0054] The communication interface controller 104 receives the reset signal 122 from the reset controller 102 and outputs a reset control signal 124 to the communication interface circuit 106 according to the reset signal 122. In some embodiments, the communication interface circuit 106 receives the reset event link signal 130 from the reset controller 102 and the reset control signal 124 from the communication interface controller 104. In some embodiments, Figure 1 As shown, communication interface circuit 106 includes an output terminal 112, an output enable terminal 114, an input terminal 116, an input / output terminal 118, and an AND gate 110. When communication interface circuit 106 is in an output mode, the voltage at output enable terminal 114 remains high, and the voltage state of output terminal 112 is the same as the voltage state of input / output terminal 118. Therefore, communication signals to be transmitted to other chips can pass through output terminal 112, pass through AND gate 110, and finally be transmitted to other chips through input / output terminal 118. In some embodiments, input / output terminal 118 may be external pins of the communication interface circuit 106 after packaging, but the present invention is not limited thereto.

[0055] In some embodiments, when the communication interface circuit 106 is in an input mode, the voltage at the output enable terminal 114 remains low, and the output terminal 112 of the AND gate 110 outputs a low level. Therefore, communication signals from other chips can pass through the input / output terminal 118, through the input terminal 116, and finally be received by the communication interface circuit 106, thereby obtaining the data transmitted by the other chips. In some embodiments, when the communication interface circuit 106 receives the reset event link signal 130 from the reset controller 102, the communication interface circuit 106 can be driven to quickly enter the input mode. In other words, when the communication interface circuit 106 receives the reset event link signal 130 from the reset controller 102, the communication interface circuit 106 can be driven to change the voltage at the output enable terminal 114 from a high level to a low level.

[0056] In some embodiments, when the communication interface circuit 106 receives the reset event link signal 130 from the reset controller 102, the communication interface circuit 106 is caused to store the voltage state of the currently transmitted communication signal (e.g., the voltage at the output terminal 112 and the output enable terminal 114). In some embodiments, when the communication interface circuit 106 receives the reset control signal 124 from the communication interface controller 104, the communication interface circuit 106 is caused to perform a reset operation. In some embodiments, the time point at which the communication interface circuit 106 enters the input mode is earlier than the time point at which the communication interface circuit 106 is reset. In other words, the time point at which the voltage at the output enable terminal 114 of the communication interface circuit 106 changes from a high level to a low level is earlier than the time point at which the reset control signal 124 received by the communication interface circuit 106 changes from a high level to a low level.

[0057] In some embodiments, the communication interface controller 104 may be a general-purpose input / output (GPIO) controller, and the communication interface circuit 106 may be a GPIO circuit, but the present invention is not limited thereto. In some embodiments, the reset controller 102, the communication interface controller 104, and the communication interface circuit 106 may be implemented in the same chip. In some embodiments, the communication interface controller 104 and the communication interface circuit 106 are implemented in the same chip, while the reset controller 102 is implemented in another chip, but the present invention is not limited thereto.

[0058] Figure 2 FIG. 1 is a signal timing diagram of the electronic device 100 according to an embodiment of the present invention. Figure 2 Public Figure 1 The reset instruction 120, reset signal 122, reset control signal 124 of the electronic device 100, and the output terminal 112, output enable terminal 114, input and output terminal 118, and input terminal 116 of the communication interface circuit 106 are shown in the signal timing diagram. Figure 2As shown, the reset command 120 changes from a high level to a low level at time t1. In other words, the reset controller 102 receives the reset command 120 from the system at time t1. The reset signal 122 changes from a high level to a low level at time t2. In other words, the communication interface controller 104 receives the reset signal 122 from the reset controller 102 at time t2. The reset control signal 124 changes from a high level to a low level at time t3. In other words, the communication interface circuit 106 receives the reset control signal 124 from the communication interface controller 104 at time t3 and performs a reset operation at time t3.

[0059] Between time points t2 and t3, for example, if the communication interface circuit 106 also receives the reset event link signal 130 from the reset controller 102 at time point t2 (i.e., the reset event link signal 130 transitions from a low level to a high level at time point t2), the voltage at the output enable terminal 114 of the communication interface circuit 106 transitions from a high level to a low level. In other words, the communication interface circuit 106 enters input mode between time points t2 and t3. Since the communication interface circuit 106 enters input mode before receiving the reset control signal 124 at time point t3, even though the output terminal 112 of the communication interface circuit 106 experiences a transient pulse 200 at time point t3 due to the communication interface circuit 106 performing a reset operation, the voltage at the output enable terminal 114 has already transitioned to a low level at time point t3. Therefore, the AND gate 110 can filter out the transient pulse 200 through an AND logic operation, thereby maintaining the voltages at the input / output terminal 118 and the input terminal 116 stable at time point t3.

[0060] In other words, since the communication interface circuit 106 enters the input mode before executing the reset operation due to receiving the reset event link signal 130, the transient pulse 200 can be avoided from being generated at the input / output terminal 118 and the input terminal 116. In some embodiments, the time point at which the reset control signal 124 changes from a high level to a low level (e.g., time point t3) falls within the period during which the reset event link signal 130 maintains a high level (e.g., time point t4). Figure 2 As shown in FIG. 1 , the voltage states of the output terminal 112 and the output enable terminal 114 of the communication interface circuit 106 remain consistent before and after the communication interface circuit 106 is reset at time point t3.

[0061] Figure 3 FIG. 3 is a schematic diagram of an electronic device 300 according to an embodiment of the present invention. Figure 3 The electronic device 300 and Figure 1 The electronic device 100 is different in that Figure 3 The electronic device 300 includes a communication interface circuit 330 , wherein the communication interface circuit 330 is different from the communication interface circuit 106 of the electronic device 100 . Figure 3 The electronic device 300 includes a reset controller 102 and a communication interface controller 104 and Figure 1 The same, so no further description. Figure 3 As shown, the communication interface circuit 330 includes an output terminal 112, an output enable terminal 114, an input terminal 116, an input-output terminal 118, a latch enable terminal 320, a flip-flop 302, a flip-flop 304, a multiplexer 306, a multiplexer 308, an AND gate 110, and a delay 310.

[0062] The latch enable terminal 320 of the communication interface circuit 330 is coupled to the clock input terminals of the flip-flop 302 and the flip-flop 304, as well as the input of the delay circuit 310. In some embodiments, the flip-flop 302 and the flip-flop 304 are both D-type flip-flops. Therefore, when the voltage at the latch enable terminal 320 changes from a low level to a high level, the flip-flop 302 stores the current voltage state of the output terminal 112, and the flip-flop 304 stores the current voltage state of the output enable terminal 114. In some embodiments, the latch enable terminal 320 of the communication interface circuit 330 receives the reset event link signal 130. The output of the delay circuit 310 is coupled to the control terminals of the multiplexer 306 and the multiplexer 308.

[0063] like Figure 3 As shown, the data input terminal of flip-flop 302 is coupled to output terminal 112 of communication interface circuit 330, and the output terminal of flip-flop 302 is coupled to a first input of multiplexer 306. The data input terminal of flip-flop 304 is coupled to output enable terminal 114 of communication interface circuit 330, and the output terminal of flip-flop 304 is coupled to a third input of multiplexer 308. Output terminal 112 of communication interface circuit 330 is coupled to a second input of multiplexer 306, and output enable terminal 114 of communication interface circuit 330 is coupled to a fourth input of multiplexer 308. The outputs of multiplexers 306 and 308 serve as inputs of AND gate 110. Input / output terminal 118 of communication interface circuit 330 serves as the output of AND gate 110, and input terminal 116 of communication interface circuit 330 is coupled to input / output terminal 118.

[0064] In some embodiments, while referring to Figure 2 and Figure 3 , when the latch enable terminal 320 of the communication interface circuit 330 receives the reset event link signal 130 from the reset controller 102, that is, Figure 2At time t2, the reset event link signal 130 changes from a low level to a high level. The flip-flop 302 stores the current voltage state of the output terminal 112, and the flip-flop 304 stores the current voltage state of the output enable terminal 114. The reset event link signal 130 is delayed by the delay 310, causing the multiplexer 306 to conduct its first input and output later than the time when the flip-flop 302 stores the current voltage state of the output terminal 112, and causing the multiplexer 308 to conduct its third input and output later than the time when the flip-flop 304 stores the current voltage state of the output enable terminal 114.

[0065] In other words, when the reset event link signal 130 transitions from a low level to a high level (i.e., the voltage at the latch enable terminal 320 transitions from a low level to a high level), the delay device 310 ensures that the multiplexer 306 outputs the current voltage state of the output terminal 112 stored by the flip-flop 302 to the AND gate 110, and ensures that the multiplexer 308 outputs the current voltage state of the output enable terminal 114 stored by the flip-flop 304 to the AND gate 110. In some embodiments, when the reset event link signal 130 transitions from a low level (i.e., the voltage at the latch enable terminal 320 transitions to a low level), the flip-flop 302 does not store the current voltage state of the output terminal 112, and the multiplexer 306 conducts its second input and its output to output the current voltage state of the output terminal 112 to the AND gate 110. Similarly, when the reset event link signal 130 becomes a low level (i.e., the voltage of the latch enable terminal 320 becomes a low level), the flip-flop 304 does not store the current voltage state of the output enable terminal 114, and the multiplexer 308 turns on its fourth input and its output to output the current voltage state of the output enable terminal 114 to the AND gate 110.

[0066] In some embodiments, during the period when the reset controller 102 maintains the reset event link signal 130 at a high level (e.g. Figure 2 The communication interface controller 104 changes the reset control signal 124 from a high level to a low level (e.g., from the time point t2 to the time point t3). Figure 2 At the time point t2), the voltage state of the output terminal 112 and the output enable terminal 114 of the communication interface circuit 330 can be reset at the time point (eg, Figure 2 When the reset event link signal 130 returns to a low level, the voltage states of the output terminal 112 and the output enable terminal 114 of the communication interface circuit 330 return to the latest (immediate) state.

[0067] For example, if Figure 2 and Figure 3As shown, when the reset event link signal 130 changes from a low level to a high level at time point t2, the flip-flop 302 stores the voltage state of the output terminal 112 at time point t2 (for example, a low level), and the flip-flop 304 stores the voltage state of the output enable terminal 114 at time point t2 (for example, a high level). During the period when the reset event link signal 130 maintains a high level, the multiplexer 306 transmits the voltage state of the output terminal 112 at the time point t2 stored by the flip-flop 302 (e.g., a low level) to the input of the AND gate 110, and the multiplexer 308 transmits the voltage state of the output enable terminal 114 at the time point t2 stored by the flip-flop 304 (e.g., a high level) to the input of the AND gate 110. Therefore, the voltage states of the output of the AND gate 110 (i.e., the input-output terminal 118 and the input terminal 116) are both low (i.e., "0" AND "1" = "0"), thereby filtering out the transient pulse 200 generated by the reset of the communication interface circuit 330 at the output terminal 112.

[0068] Figure 4 FIG. 4 is a schematic diagram of an electronic device 400 according to an embodiment of the present invention. Figure 4 The electronic device 400 and Figure 1 The electronic device 100 is different in that Figure 4 The electronic device 400 includes a communication interface controller 402, wherein the communication interface controller 402 is different from the communication interface controller 104 of the electronic device 100. Figure 4 As shown, the communication interface controller 402 includes a GPIO controller 410, an integrated circuit bus (I2C) controller 412, a serial peripheral interface (SPI) controller 414, and a multiplexer 408. In some embodiments, the communication interface controller 402 further includes a universal asynchronous receiver / transmitter (UART) controller (not shown), but the present invention is not limited thereto.

[0069] In some embodiments, the GPIO controller 410, the I2C controller 412, and the SPI controller 414 each receive a reset signal 122 from the reset controller 102. The communication interface controller 402 selects the interface to be reset via a control signal 420. For example, if the communication interface circuit 106 supports the GPIO communication interface, the communication interface controller 402 sets the content of the control signal 420 to "00" to couple the multiplexer 408 to the GPIO controller 410. The GPIO controller 410 then outputs a reset control signal 124 to the communication interface circuit 106 based on the reset signal 122.

[0070] In another example, when the communication interface circuit 106 supports the SPI communication interface, the communication interface controller 402 sets the content of the control signal 420 to "10", so that the multiplexer 408 is coupled to the SPI controller 414. The SPI controller 414 therefore outputs a reset control signal 124 to the communication interface circuit 106 according to the reset signal 122. Thereafter, the communication interface circuit 106 receives the reset event link signal 130 from the reset controller 102, so that the time point at which the communication interface circuit 106 enters the input mode is earlier than the time point at which the communication interface circuit 106 performs the reset operation according to the reset control signal 124, so as to avoid generating transient pulses (e.g., Figure 2 transient pulse 200).

[0071] Figure 5 For the embodiment of the present invention Figure 1 Flowchart of the method for solving the transient pulse output of the communication interface of the electronic device 100. Figure 5 As shown, Figure 1 The reset controller 102 executes step S500 , ie, outputs a reset signal 122 and a reset event link signal 130 according to a reset instruction 120 . Figure 1 The communication interface controller then executes step S502, that is, outputs a reset control signal 124 according to the reset signal 122. Figure 1 The communication interface circuit 106 executes step S506, that is, receives the reset event link signal 130, so that the communication interface circuit 106 stores the voltage state of the currently transmitted communication signal (such as the output terminal 112 and the output enable terminal 114) in preparation for entering an input mode (such as Figure 2 The voltage of the output enable terminal 114 changes from a high level to a low level).

[0072] Next, the communication interface circuit 106 executes step S506, i.e., receives the reset control signal 124, causing the communication interface circuit 106 to reset. The time point at which the communication interface circuit 106 enters the input mode in step S504 is earlier than the time point at which the communication interface circuit 106 resets in step S506. Thereafter, the communication interface circuit 106 executes step S508, i.e., when the reset event link signal 130 changes from a low level to a high level, the communication interface circuit 106 stores the voltage state of the transmitted communication signal (e.g., the output terminal 112 and the output enable terminal 114).

[0073] Finally, the reset controller 102, the communication interface controller 104, and the communication interface circuit 106 complete step S510 together. In step S510, while the reset controller 102 maintains the reset event link signal 130 at a high level, the communication interface controller 104 changes the reset control signal 124 from a high level to a low level, so that the voltage state of the communication signal (e.g., the output terminal 112 and the output enable terminal 114) of the communication interface circuit 106 can be maintained consistent before and after the communication interface circuit 106 is reset. The electronic device and the method for solving the transient pulse output of the communication interface of the present invention are as follows: Figure 1 The reset event link signal 130 is used to pre-process the communication interface (such as GPIO) state change problem to ensure that the chip does not generate unexpected transient pulses during the reset process.

[0074] Although embodiments of the present invention have been described above, it should be understood that these are presented by way of example only and not limitation. Many variations of the exemplary embodiments described above may be implemented without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. Rather, the scope of the present invention is defined by the following claims and their equivalents.

[0075] Although the invention has been illustrated and described above with reference to one or more embodiments, equivalent changes and modifications will occur to others skilled in the art based on the above specification and drawings. In addition, although a particular feature of an embodiment of the invention has been demonstrated with reference to one of the multiple embodiments, that feature may be combined with one or more other features as may be desirable and useful for any known or particular application.

[0076] Unless otherwise defined, all terms used herein (including technical or scientific terms) are generally understood by persons skilled in the art to which the present invention pertains. It should be understood that these terms, as defined in commonly used dictionaries, should be interpreted in the context of the relevant art. Unless otherwise specifically defined herein, these terms are not to be interpreted in an idealized or overly formal sense.

Claims

1. An electronic device for solving transient pulse output of a communication interface, characterized in that: include: a reset controller, outputting a reset signal and a reset event link signal according to a reset instruction; a communication interface controller, outputting a reset control signal according to the reset signal; a communication interface circuit that receives the reset event link signal so that the communication interface circuit stores the voltage state of the currently transmitted communication signal in preparation for entering an input mode; and receives the reset control signal so that the communication interface circuit is reset; The time point at which the communication interface circuit enters the input mode is earlier than the time point at which the communication interface circuit is reset.

2. The electronic device according to claim 1, wherein: The communication interface circuit includes an output terminal, an output enable terminal, an input terminal, and an input-output terminal; when the voltage of the output enable terminal changes from a high level to a low level, the communication interface circuit enters the input mode; and when the reset control signal changes from a high level to a low level, the communication interface circuit is reset.

3. The electronic device according to claim 2, wherein: The communication interface circuit also includes an AND gate; wherein the output end and the output enable end of the communication interface circuit serve as inputs of the AND gate, the input and output ends of the communication interface circuit serve as outputs of the AND gate, and the input end of the communication interface circuit is coupled to the input and output ends.

4. The electronic device according to claim 2, wherein: A time point at which the voltage of the output enable terminal of the communication interface circuit changes from a high level to a low level is earlier than a time point at which the reset control signal changes from a high level to a low level.

5. The electronic device according to claim 1, wherein: The communication interface circuit includes an output terminal, an output enable terminal, an input terminal, an input-output terminal, a latch enable terminal, a first flip-flop, a second flip-flop, a first multiplexer, a second multiplexer, an AND gate, and a delay device.

6. The electronic device according to claim 5, wherein: The latch enable terminal is coupled to the clock input terminals of the first flip-flop and the second flip-flop, and the input of the delay device; the output of the delay device is coupled to the control terminals of the first multiplexer and the second multiplexer; The data input terminal of the first flip-flop is coupled to the output terminal of the communication interface circuit, and the output result terminal of the first flip-flop is coupled to a first input of the first multiplexer; The data input terminal of the second flip-flop is coupled to the output enable terminal of the communication interface circuit, and the output result terminal of the second flip-flop is coupled to a third input of the second multiplexer; The output terminal of the communication interface circuit is coupled to a second input of the first multiplexer; The output enable terminal of the communication interface circuit is coupled to a fourth input of the second multiplexer; the outputs of the first multiplexer and the second multiplexer serve as inputs of the AND gate; the input and output terminals of the communication interface circuit serve as outputs of the AND gate, and the input terminal of the communication interface circuit is coupled to the input and output terminals.

7. The electronic device according to claim 6, wherein: The latch enable terminal of the communication interface circuit receives the reset event link signal; when the communication interface controller changes the reset event link signal from a low level to a high level, the first flip-flop and the second flip-flop store the current voltage states of the output terminal and the output enable terminal, so that the first multiplexer outputs the current voltage state of the output terminal stored by the first flip-flop to the AND gate, and the second multiplexer outputs the current voltage state of the output enable terminal stored by the second flip-flop to the AND gate.

8. The electronic device according to claim 7, wherein: The time point when the reset control signal changes from a high level to a low level falls during the period when the reset event link signal maintains a high level, so that the voltage states of the output end and the output enable end of the communication interface circuit remain consistent before and after the communication interface circuit is reset.

9. A method for solving transient pulse output of a communication interface, characterized in that: Applicable to an electronic device for transmitting communication signals, the electronic device includes a reset controller, a communication interface controller, and a communication interface circuit, the method comprising: The reset controller outputs a reset signal and a reset event link signal according to a reset instruction; The communication interface controller outputs a reset control signal according to the reset signal; The communication interface circuit receives the reset event link signal, so that the communication interface circuit stores the voltage state of the currently transmitted communication signal in preparation for entering an input mode; The communication interface circuit receives the reset control signal, causing the communication interface circuit to reset; The time point at which the communication interface circuit enters the input mode is earlier than the time point at which the communication interface circuit is reset.

10. The method for solving the problem of transient pulse output of a communication interface according to claim 9, characterized in that: Also includes: When the reset controller changes the reset event link signal from a low level to a high level, the communication interface circuit stores the voltage state of the transmitted communication signal; During the period when the reset controller maintains the reset event link signal at a high level, the communication interface controller changes the reset control signal from a high level to a low level, so that the voltage state of the communication signal of the communication interface circuit can be maintained consistent before and after the time point when the communication interface circuit is reset.

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