Processor, control method, device and medium

Abstract

The disclosed embodiment discloses a processor, a control method, a device and a medium, wherein the processor includes at least one processor core and at least one upper limit register; the upper limit register is used to store an upper limit rate, when the first rate of the target processor core corresponding to the target upper limit register generating a split lock is greater than or equal to the target upper limit rate in the target upper limit register, the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core. This solution can ensure that the performance of the processor core will not be reduced too much due to the generation of a split lock without affecting the normal execution of the user application as much as possible, thereby improving the user experience.

Description

Technical Field

[0001] The present disclosure relates to the field of network technology, and in particular to a processor, a control method, a device, and a medium. Background Art

[0002] When using a processor to perform operations, non-aligned memory access may occur. For example, a processor that supports symmetric multi-processing (SMP) may include multiple processor cores, and one of the multiple processor cores may read data across two cache lines. When this happens, in order to ensure the atomicity of data reading, the entire bus of the processor needs to be locked. This situation can be understood as the processor core generating a split lock. Although the above solution can ensure the atomicity of data reading, since the processor bus is locked, other processor cores may not be able to access the memory concurrently when the bus is locked, resulting in a decrease in processor performance.

[0003] In the related art, the application program running on the processor and the compiler of the application program can be made to avoid allocating variable addresses across cachelines as much as possible, so as to reduce the number of times splitlock is generated and achieve the purpose of reducing the probability of bus locking.

[0004] Although the above solution can reduce the probability of bus locking, in scenarios where applications cannot be controlled, such as cloud computing scenarios, cloud computing service providers cannot control applications running on the processor. Therefore, when running applications that may generate splitlock on the processor, how to protect other applications running on the processor so that other applications can run normally, while the performance of the processor will not be overly affected by the generation of splitlock, is an urgent problem to be solved in related technologies. Summary of the invention

[0005] In order to solve the problems in the related art, the embodiments of the present disclosure provide a processor, a control method, a device and a medium.

[0006] In a first aspect, an embodiment of the present disclosure provides a processor, wherein the processor includes at least one processor core and at least one upper limit register;

[0007] An upper limit register is used to store an upper limit rate. When the first rate at which the target processor core corresponding to the target upper limit register generates a split lock is greater than or equal to the target upper limit rate in the target upper limit register, the maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. The target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core.

[0008] In combination with the first aspect, in a first implementation of the first aspect of the present disclosure,

[0009] The processor further comprises a frequency control logic circuit, and at least one processor core and at least one upper limit register are both connected to the frequency control logic circuit;

[0010] The frequency control logic circuit is used to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and in response to the first rate being greater than or equal to the target upper limit rate, reduce the maximum frequency of the target processor core.

[0011] In combination with the first implementation of the first aspect, in the second implementation of the first aspect of the present disclosure,

[0012] Reduce the maximum frequency of the target processor core, including:

[0013] Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

[0014] The highest frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the highest frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

[0015] In combination with any one of the first implementation manner to the second implementation manner of the first aspect, in a third implementation manner of the first aspect of the present disclosure, the frequency control logic circuit is further used to:

[0016] Get the third rate at which the current target processor core generates splitlock;

[0017] In response to the third rate being less than the target upper limit rate, the maximum frequency of the target processor core is increased.

[0018] In combination with the third implementation of the first aspect, in a fourth implementation of the first aspect of the present disclosure, the frequency control logic circuit is further used to:

[0019] Obtaining a current frequency adjustment count value and a frequency before the current target processor core is increased, wherein the frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold value according to a count decreasing speed starting from the moment when the frequency of the target processor core is controlled to decrease;

[0020] Increase the maximum frequency of the target processor core, including:

[0021] The maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase.

[0022] In combination with the fourth implementation of the first aspect, in a fifth implementation of the first aspect of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate, and the frequency adjustment count value includes:

[0023] The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

[0024] In combination with the fourth implementation of the first aspect, in a sixth implementation of the first aspect of the present disclosure, wherein:

[0025] The processor further includes a frequency adjustment count threshold register for storing a frequency adjustment count threshold and a frequency adjustment count value register for storing a frequency adjustment count value, wherein the frequency adjustment count threshold register and the frequency adjustment count value register are both connected to the frequency control logic circuit;

[0026] The frequency control logic circuit is used to store the frequency adjustment count threshold read from the frequency adjustment count threshold register in the frequency adjustment count value register when the frequency of the target processor core is controlled to decrease, and continuously decrease the frequency adjustment count threshold in the frequency adjustment count value register according to the count decrease speed;

[0027] Get the current frequency adjustment count value, including:

[0028] Read the current frequency adjustment count value from the frequency adjustment count value register.

[0029] In combination with the fourth implementation manner of the first aspect, in a seventh implementation manner of the first aspect of the present disclosure, the frequency control logic circuit is further used to:

[0030] In response to the frequency adjustment count value being 0, the maximum frequency of the target processor core is set as the processor core maximum frequency.

[0031] In a second aspect, an embodiment of the present disclosure provides a processor control method, wherein the method includes:

[0032] Obtaining a rate at which at least one processor core of a processor generates a split lock and an upper limit rate corresponding to at least one processor core;

[0033] In response to a first rate at which a target processor core in at least one processor core generates splitlock being greater than or equal to an upper limit rate corresponding to the target processor core, a maximum frequency of the target processor core is reduced, and / or an alignment check exception is triggered on the target processor core.

[0034] In combination with the second aspect, in a first implementation of the second aspect of the present disclosure, reducing the maximum frequency of the target processor core includes:

[0035] Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

[0036] The highest frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the highest frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

[0037] In combination with the second aspect or the first implementation of the second aspect, in a second implementation of the second aspect of the present disclosure, the method further includes:

[0038] Get the third rate at which the current target processor core generates splitlock;

[0039] In response to the third rate being less than the target upper limit rate, the maximum frequency of the target processor core is increased.

[0040] In combination with the second implementation of the second aspect, in a third implementation of the second aspect of the present disclosure, the method further includes:

[0041] Obtaining a current frequency adjustment count value and a frequency before the current target processor core is increased, wherein the frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold value according to a count decreasing speed starting from the moment when the frequency of the target processor core is controlled to decrease;

[0042] Increase the maximum frequency of the target processor core, including:

[0043] The maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase.

[0044] In combination with the third implementation of the second aspect, in a fourth implementation of the second aspect of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate, and the frequency adjustment count value includes:

[0045] The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

[0046] In combination with the third implementation of the second aspect, in a fourth implementation of the second aspect of the present disclosure, the method further includes:

[0047] In response to the frequency adjustment count value being 0, the maximum frequency of the target processor core is set as the processor core maximum frequency.

[0048] In a third aspect, an internal processor control device is provided in an embodiment of the present disclosure, and the processor control device includes:

[0049] A rate acquisition module is configured to acquire a rate at which at least one processor core of a processor generates a split lock and an upper limit rate corresponding to at least one processor core;

[0050] The frequency control module is configured to reduce the maximum frequency of the target processor core and / or cause the target processor core to trigger an alignment check exception in response to a first rate at which a target processor core in at least one processor core generates a splitlock being greater than or equal to an upper limit rate corresponding to the target processor core.

[0051] In a fourth aspect, an electronic device is provided in an embodiment of the present disclosure, comprising a memory and at least one processor; the memory is used to store one or more computer instructions, and the one or more computer instructions are executed by at least one processor to implement the method steps of any one of the second aspect and the first implementation method of the second aspect to the fourth implementation method.

[0052] In a fifth aspect, a computer-readable storage medium is provided in an embodiment of the present disclosure, on which computer instructions are stored. When the computer instructions are executed by a processor, the method steps of any one of the second aspect and the first to fourth implementations of the second aspect are implemented.

[0053] In a sixth aspect, a computer program product is provided in an embodiment of the present disclosure, comprising computer instructions, which, when executed by a processor, implement the method steps of any one of the second aspect and the first to fourth implementations of the second aspect.

[0054] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0055] According to the technical solution provided by the embodiment of the present disclosure, the processor includes at least one processor core and at least one upper limit register; wherein the upper limit register is used to store the upper limit rate, when the first rate at which the target processor core corresponding to the target upper limit register generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register, the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core. During use, when the target processor core in the processor generates splitlock, considering that the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much, so the upper limit rate stored in the upper limit register located in the processor can be read at a faster speed, and the rate at which the corresponding processor core generates splitlock is determined based on the upper limit rate. Whether it is high, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception.Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced). When the rate at which splitlock is generated is high and may reduce the performance of the target processor core too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, ensuring that the performance of the processor core is not reduced too much due to the generation of splitlock, so that related applications running on the target processor core (such as applications that may cause the generation of splitlock) can be executed normally. , and the related applications running on other processor cores will not be affected too much; in addition, the target processor core triggers the alignment check exception only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger the alignment check exception, so that the related applications running on the target processor core (such as applications that may cause splitlock to be generated) can be executed normally, and the related applications running on other processor cores will not be affected too much, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core triggers the alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, the above scheme ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0056] According to the technical solution provided by the embodiment of the present disclosure, the processor also includes a frequency control logic circuit, wherein at least one processor core and at least one upper limit register are connected to the frequency control logic circuit, and the frequency control logic circuit is used to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and in response to the first rate being greater than or equal to the target upper limit rate, reduce the maximum frequency of the target processor core. Since the frequency control logic circuit is arranged in the processor, the time taken for the frequency control logic circuit to obtain the rate at which at least one processor core generates splitlock and to read the upper limit rate from at least one upper limit register is relatively short, so that the frequency control logic circuit responds to the first rate being greater than or equal to the target upper limit rate and reduces the maximum frequency of the target processor core. This process has a faster reaction speed, reduces processing delay, and improves processing efficiency.

[0057] According to the technical solution provided by the embodiment of the present disclosure, the frequency control logic circuit obtains the highest frequency of the target processor core after reduction and adjusts the highest frequency of the target processor core to the highest frequency after reduction until the second rate at which the target processor core generates splitlock is less than the target upper limit rate. This ensures that the highest frequency of the target processor core after reduction, i.e., the highest frequency after reduction, is continuously obtained in real time according to the target upper limit rate corresponding to the target processor core, the real-time rate at which the target processor core generates splitlock, i.e., the first rate, and the real-time frequency of the target processor core. The highest frequency of the target processor core is adjusted to the highest frequency after reduction until the rate at which the target processor core generates splitlock, i.e., the second rate, is less than the target upper limit rate. This ensures that the highest frequency of the target processor core can be stably reduced in stages to a range that meets the requirements, thereby avoiding large fluctuations in the performance of the target processor core due to a sharp decline.

[0058] According to the technical solution provided by the embodiment of the present disclosure, the frequency control logic circuit obtains the third rate at which the current target processor core generates splitlock, and in response to the third rate being less than the target upper limit rate, increases the maximum frequency of the target processor core. This can ensure that after the maximum frequency of the target processor core is increased, the rate at which the target processor core generates splitlock can approach the target upper limit rate, ensuring that the maximum frequency of the target processor core is increased as much as possible to improve the performance of the target processor core, under the premise that the performance of the processor core will not be reduced too much due to generating splitlock too quickly.

[0059] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the current frequency adjustment count value and the frequency before the increase of the current target processor core, the maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the obtained maximum frequency after the increase is relatively high, it may cause the frequency of the target processor core to be too high after the maximum frequency of the target processor core is set to the maximum frequency after the increase, thereby causing the target processor core to generate splitlock at a relatively high rate, and even the target processor core to generate splitlock at a rate greater than or equal to the target upper limit rate. Therefore, by making the third rate negatively correlated with the maximum frequency after the increase, it is possible to avoid the maximum frequency after the increase being high when the third rate is already in a relatively high state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment. The longer the time length, the smaller the frequency adjustment count value. Considering that the longer the time length, the greater the impact on the target processor core executing normal applications, therefore, by making the maximum frequency after the increase negatively correlated with the frequency adjustment count value, it is possible to avoid the frequency of the target processor core being in a state of being too low for a long time, so that the normal applications executed by the target processor core will not be affected too much.

[0060] The technical solution provided by the embodiment of the present disclosure can obtain the highest frequency after boosting by Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), which can more conveniently obtain the highest frequency after boosting and improve the efficiency of obtaining the highest frequency after boosting.

[0061] According to the technical solution provided by the embodiment of the present disclosure, the processor also includes a frequency adjustment count threshold register for storing a frequency adjustment count threshold and a frequency adjustment count value register for storing a frequency adjustment count value. The frequency adjustment count threshold register and the frequency adjustment count value register are both connected to the frequency control logic circuit. Since the frequency adjustment count threshold register and the frequency adjustment count value register are both located in the processor, the frequency control logic circuit in the processor has a short delay when reading the frequency adjustment count threshold from the frequency adjustment count threshold register and continuously decreasing the frequency adjustment count threshold in the frequency adjustment count value register according to the counting decrease speed, thereby improving the processing efficiency of the frequency control logic circuit.

[0062] According to the technical solution provided by the embodiment of the present disclosure, when the frequency adjustment count value is 0, it indicates that the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment has reached the maximum time length allowed for limiting the maximum frequency of the target processor core. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application execution of the target processor core. Therefore, the frequency control logic circuit sets the maximum frequency of the target processor core to the maximum frequency of the processor core in response to the frequency adjustment count value being 0, that is, no restrictions are imposed on the maximum frequency of the target processor core, thereby ensuring that the normal application execution of the target processor core will not be affected in any way.

[0063] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the rate at which at least one processor core of the processor generates splitlock and the upper limit rate corresponding to at least one processor core, considering that when the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much, it is possible to determine whether the rate at which the corresponding processor core generates splitlock is high based on the upper limit rate, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced). When the rate at which splitlock is generated is high and may reduce the performance of the target processor core too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, ensuring that the performance of the processor core is not reduced too much due to the generation of splitlock, so that related applications running on the target processor core (such as applications that may cause the generation of splitlock) can be executed normally. , and the related applications running on other processor cores will not be affected too much; in addition, the target processor core triggers the alignment check exception only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger the alignment check exception, so that the related applications running on the target processor core (such as applications that may cause splitlock to be generated) can be executed normally, and the related applications running on other processor cores will not be affected too much, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core triggers the alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, the above scheme ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0064] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the reduced maximum frequency of the target processor core and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate, it can be ensured that the reduced maximum frequency of the target processor core, i.e. the reduced maximum frequency, is continuously obtained in real time according to the target upper limit rate corresponding to the target processor core, the real-time rate at which the target processor core generates splitlock, i.e. the first rate, and the real-time frequency of the target processor core, and the maximum frequency of the target processor core is adjusted to the reduced maximum frequency until the rate at which the target processor core generates splitlock, i.e. the second rate, is less than the target upper limit rate, thereby ensuring that the maximum frequency of the target processor core can be stably reduced in stages to a range that meets the requirements, thereby avoiding large fluctuations in the performance of the target processor core due to a sharp decline.

[0065] According to the technical solution provided by the embodiments of the present disclosure, by obtaining the third rate at which the current target processor core generates splitlock, and in response to the third rate being less than the target upper limit rate, increasing the maximum frequency of the target processor core, it is possible to ensure that after the maximum frequency of the target processor core is increased, the rate at which the target processor core generates splitlock can approach the target upper limit rate, thereby ensuring that, under the premise that the performance of the processor core will not be reduced too much due to the generation of splitlock, the maximum frequency of the target processor core is increased as much as possible, thereby improving the performance of the target processor core.

[0066] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the current frequency adjustment count value and the frequency before the increase of the current target processor core, the maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the obtained maximum frequency after the increase is relatively high, it may cause the frequency of the target processor core to be too high after the maximum frequency of the target processor core is set to the maximum frequency after the increase, thereby causing the target processor core to generate splitlock at a relatively high rate, and even the target processor core to generate splitlock at a rate greater than or equal to the target upper limit rate. Therefore, by making the third rate negatively correlated with the maximum frequency after the increase, it is possible to avoid the maximum frequency after the increase being high when the first rate is already in a relatively high state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment, and the longer the time length, the smaller the frequency adjustment count value, and considering that the longer the time length, the greater the impact on the target processor core executing normal applications, therefore, by making the maximum frequency after the increase negatively correlated with the frequency adjustment count value, it is possible to avoid the frequency of the target processor core being in a state of being too low for a long time, so that the normal applications executed by the target processor core will not be affected too much.

[0067] The technical solution provided by the embodiment of the present disclosure can obtain the highest frequency after boosting by Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), which can more conveniently obtain the highest frequency after boosting and improve the efficiency of obtaining the highest frequency after boosting.

[0068] According to the technical solution provided by the embodiment of the present disclosure, when the frequency adjustment count value is 0, it indicates that the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment has reached the maximum time length allowed for limiting the maximum frequency of the target processor core. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application execution of the target processor core. Therefore, by setting the maximum frequency of the target processor core to the maximum frequency of the processor core in response to the frequency adjustment count value being 0, that is, no restriction is imposed on the maximum frequency of the target processor core, it can be ensured that the normal application execution of the target processor core will not be affected in any way.

[0069] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0071] Figure 1 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown.

[0072] Figure 2 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown.

[0073] Figure 3 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown.

[0074] Figure 4 A flowchart of a processor control method according to an embodiment of the present disclosure is shown.

[0075] Figure 5 A structural block diagram of a processor control device according to an embodiment of the present disclosure is shown.

[0076] Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0077] Figure 7 It is a schematic diagram of the structure of a computer system suitable for implementing a method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0079] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of labels, numbers, steps, behaviors, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other labels, numbers, steps, behaviors, components, parts, or combinations thereof exist or are added.

[0080] It should also be noted that, in the absence of conflict, the embodiments and labels in the embodiments of the present disclosure can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0081] In order to protect other applications running on the processor and enable them to run normally when an application that may generate a splitlock is running on the processor, without affecting the performance of the processor too much due to the generation of the splitlock, the inventors of the present disclosure have considered the following solution.

[0082] In the related art, the application program running on the processor and the compiler of the application program can be made to avoid allocating variable addresses across cachelines as much as possible, so as to reduce the number of times splitlock is generated and achieve the purpose of reducing the probability of bus locking.

[0083] Disadvantages of this solution: Although the above solution can reduce the probability of bus locking, in scenarios where applications cannot be controlled, such as cloud computing scenarios, cloud computing service providers cannot control applications running on the processor. Therefore, when running applications that may generate splitlock on the processor, how to protect other applications running on the processor so that other applications can run normally without affecting the performance of the processor too much due to the generation of splitlock is an urgent problem to be solved in related technologies.

[0084] Considering the shortcomings of the above scheme, the inventor of the present disclosure proposes a new scheme: the processor in the scheme includes at least one processor core and at least one upper limit register; wherein the upper limit register is used to store the upper limit rate, when the first rate at which the target processor core corresponding to the target upper limit register generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register, the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core. During use, when the target processor core in the processor generates splitlock, considering that the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much, so the upper limit rate stored in the upper limit register located in the processor can be read at a faster speed, and based on the upper limit rate, it is determined whether the rate at which the corresponding processor core generates splitlock is high, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced); and when the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, which ensures that the performance of the processor core is not affected by the generation of splitlock. ck and reduce it too much; in addition, only when the first rate at which the target processor core generates splitlock is high, the target processor core is caused to trigger an alignment check exception, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger an alignment check exception, so that the user's related applications (such as applications that may cause splitlock to be generated) can be executed normally, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core will trigger an alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock.Therefore, the above solution ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0085] In order to solve the above problems, the present disclosure proposes a processor, a control method, a device and a medium.

[0086] Figure 1 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the processor 100 includes at least one processor core 101 and at least one upper limit register 102 .

[0087] Among them, the upper limit register 102 is used to store the upper limit rate. When the first rate at which the target processor core corresponding to the target upper limit register generates a split lock is greater than or equal to the target upper limit rate in the target upper limit register, the maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. The target upper limit register belongs to at least one upper limit register 102, and the target processor core belongs to at least one processor core 101.

[0088] In one embodiment of the present disclosure, the processor may include one or more processor cores, each of which may be configured with a cache. The cache is a memory located between the processor execution unit and the main memory (Dynamic Random Access Memory, DRAM), usually composed of a static RAM (Static RAM, SRAM), which is small in size but has a fast access speed. The cache can be used to save a copy of part of the data in the memory. When the processor reads and writes data, it first accesses the cache. When the required data does not exist in the cache, the memory is accessed. The cache is usually divided into multiple groups, each of which is divided into multiple cache lines. When a unit is fetched from the memory to the cache, a memory area of ​​the size of a cache line is fetched into the cache at a time, and then stored in the corresponding cache line.

[0089] In one embodiment of the present disclosure, the processor core generating a splitlock can be understood as the processor core generating a data read across two cache lines. In order to ensure the atomicity of the data read, the entire bus of the processor needs to be locked. This situation can be understood as the processor core generating a splitlock. Among them, the atomicity of the data read can be understood as the data read cannot be interrupted. The order cannot be disrupted, and part of the data read cannot be cut off or only part of the data read can be executed.

[0090] In one embodiment of the present disclosure, the upper limit rate can be understood as an upper limit for indicating the number of times the corresponding processor core is allowed to generate splitlocks within a unit time. For example, the unit of the upper limit rate can be times / second. If the number of times the corresponding processor core generates splitlocks within a unit time is greater than or equal to the upper limit rate, the performance of the corresponding processor core may be greatly reduced.

[0091] In one embodiment of the present disclosure, the upper limit rate may be stored in an upper limit register in advance, or may be calculated by the processor itself based on the processor's historical log according to a corresponding algorithm or model and written into the upper limit register, or may be written into the upper limit register by other devices or systems.

[0092] In one embodiment of the present disclosure, the first rate may be to detect the target processor core in real time to determine whether the target processor core generates a splitlock, and obtain the first rate according to the detection result, wherein the real-time detection of the target processor core may be to periodically detect the target processor core in real time at intervals of a preset detection time threshold, and the preset detection time threshold may be 1ms. Exemplarily, the indication information indicating whether the corresponding processor core generates a splitlock may be periodically obtained through the power management unit (Power Management Unit) in the processor at intervals of 1ms, and whether the corresponding processor core generates a splitlock is determined according to the indication information, and the rate at which the corresponding processor core generates a splitlock is further obtained.

[0093] In one embodiment of the present disclosure, the maximum frequency of the target processor core is reduced, which can be understood as setting the maximum frequency of the target processor core to a preset frequency; or, it can be to pre-set the rate levels for different rates of generating splitlock, and set the correspondence between the rate levels and the maximum frequencies, determine the target rate level corresponding to the first rate before reducing the maximum frequency of the target processor core, obtain the maximum frequency corresponding to the target rate level, and set the maximum frequency of the target processor core to the maximum frequency corresponding to the target rate level.

[0094] According to the technical solution provided by the embodiment of the present disclosure, the processor includes at least one processor core and at least one upper limit register; wherein the upper limit register is used to store the upper limit rate, when the first rate at which the target processor core corresponding to the target upper limit register generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register, the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception, the target upper limit register belongs to at least one upper limit register, and the target processor core belongs to at least one processor core. During use, when the target processor core in the processor generates splitlock, considering that the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much, so the upper limit rate stored in the upper limit register located in the processor can be read at a faster speed, and the rate at which the corresponding processor core generates splitlock is determined based on the upper limit rate. Whether it is high, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate in the target upper limit register corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the highest frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception.Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced). When the rate at which splitlock is generated is high and may reduce the performance of the target processor core too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, ensuring that the performance of the processor core is not reduced too much due to the generation of splitlock, so that related applications running on the target processor core (such as applications that may cause the generation of splitlock) can be executed normally. , and the related applications running on other processor cores will not be affected too much; in addition, the target processor core triggers the alignment check exception only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger the alignment check exception, so that the related applications running on the target processor core (such as applications that may cause splitlock to be generated) can be executed normally, and the related applications running on other processor cores will not be affected too much, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core triggers the alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, the above scheme ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0095] In one embodiment of the present disclosure, Figure 2 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the processor 100 further includes a frequency control logic circuit 103 , and at least one processor core 101 and at least one upper limit register 102 are both connected to the frequency control logic circuit 103 .

[0096] The frequency control logic circuit 103 is used to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and reduce the maximum frequency of the target processor core in response to the first rate being greater than or equal to the target upper limit rate.

[0097] In one embodiment of the present disclosure, the frequency control logic circuit can be understood as a circuit located in a processor and having a logic operation function. By connecting to at least one processor core, the frequency control logic circuit can exchange information with the corresponding processor core, such as obtaining the rate at which the corresponding processor core generates splitlock, and sending maximum frequency control information to the target processor core, so that the target processor core reduces its maximum frequency in response to the maximum frequency control information. By connecting to at least one upper limit register, the frequency control logic circuit can read the upper limit rate stored in the upper limit register from the corresponding upper limit register.

[0098] According to the technical solution provided by the embodiment of the present disclosure, the processor also includes a frequency control logic circuit, wherein at least one processor core and at least one upper limit register are connected to the frequency control logic circuit, and the frequency control logic circuit is used to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and in response to the first rate being greater than or equal to the target upper limit rate, reduce the maximum frequency of the target processor core. Since the frequency control logic circuit is arranged in the processor, the time taken for the frequency control logic circuit to obtain the rate at which at least one processor core generates splitlock and to read the upper limit rate from at least one upper limit register is relatively short, so that the frequency control logic circuit responds to the first rate being greater than or equal to the target upper limit rate and reduces the maximum frequency of the target processor core. This process has a faster reaction speed, reduces processing delay, and improves processing efficiency.

[0099] In one embodiment of the present disclosure, reducing the maximum frequency of a target processor core includes:

[0100] Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

[0101] The highest frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the highest frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

[0102] In one embodiment of the present disclosure, the frequency of the target processor core before reduction can be understood as the frequency of the target processor core at a moment before the highest frequency of the target processor core is reduced. The frequency of the target processor core before reduction can be obtained from the target processor core by the frequency control logic circuit, or can be obtained from other devices or systems by the frequency control logic circuit.

[0103] In one embodiment of the present disclosure, the maximum frequency of the target processor core after the reduction is obtained, and the maximum frequency of the target processor core is adjusted to the maximum frequency after the reduction, until the second rate at which the target processor core generates splitlock is less than the target upper limit rate. It can be understood that the first rate of the target processor core and the frequency of the target processor core, that is, the frequency before the reduction, are periodically obtained in real time at intervals of a preset frequency reduction time threshold, and the target upper limit rate read from the target upper limit register, the first rate obtained in real time, and the frequency before the reduction obtained in real time are calculated to obtain the maximum frequency of the target processor core after the reduction, and adjust the maximum frequency of the target processor core to the maximum frequency after the reduction. Wherein, after the maximum frequency of the target processor core is adjusted to the maximum frequency after the reduction, if the rate at which the target processor core generates splitlock is less than the target upper limit rate, the acquisition of the maximum frequency of the target processor core after the reduction is stopped.

[0104] According to the technical solution provided by the embodiment of the present disclosure, the frequency control logic circuit obtains the highest frequency of the target processor core after reduction and adjusts the highest frequency of the target processor core to the highest frequency after reduction until the second rate at which the target processor core generates splitlock is less than the target upper limit rate. This ensures that the highest frequency of the target processor core after reduction, i.e., the highest frequency after reduction, is continuously obtained in real time according to the target upper limit rate corresponding to the target processor core, the real-time rate at which the target processor core generates splitlock, i.e., the first rate, and the real-time frequency of the target processor core. The highest frequency of the target processor core is adjusted to the highest frequency after reduction until the rate at which the target processor core generates splitlock, i.e., the second rate, is less than the target upper limit rate. This ensures that the highest frequency of the target processor core can be stably reduced in stages to a range that meets the requirements, thereby avoiding large fluctuations in the performance of the target processor core due to a sharp decline.

[0105] In one embodiment of the present disclosure, the frequency control logic circuit is further used for:

[0106] Get the third rate at which the current target processor core generates splitlock;

[0107] In response to the third rate being less than the target upper limit rate, the maximum frequency of the target processor core is increased.

[0108] In one embodiment of the present disclosure, the third rate may be understood as the rate at which the target processor core generates a splitlock after the frequency control logic circuit reduces the maximum frequency of the target processor core.

[0109] In one embodiment of the present disclosure, the third rate may be obtained by performing real-time detection on the target processor core to determine whether the target processor core generates a split lock, and obtaining the third rate according to the detection result.

[0110] In one embodiment of the present disclosure, increasing the maximum frequency of the target processor core can be understood as periodically increasing the maximum frequency of the target processor core according to a preset frequency increase threshold and at intervals of a preset increase time threshold; or, it can also be calculated according to a preset frequency increase speed threshold and the current maximum frequency of the target processor core to obtain the maximum frequency of the target processor core after the increase at different times, and adjust the maximum frequency of the target processor core at the corresponding time.

[0111] According to the technical solution provided by the embodiment of the present disclosure, the frequency control logic circuit obtains the third rate at which the current target processor core generates splitlock, and in response to the third rate being less than the target upper limit rate, increases the maximum frequency of the target processor core. This can ensure that after the maximum frequency of the target processor core is increased, the rate at which the target processor core generates splitlock can approach the target upper limit rate, ensuring that the maximum frequency of the target processor core is increased as much as possible to improve the performance of the target processor core, under the premise that the performance of the processor core will not be reduced too much due to generating splitlock too quickly.

[0112] In one embodiment of the present disclosure, the frequency control logic circuit is further used for:

[0113] Obtaining a current frequency adjustment count value and a frequency before the current target processor core is increased, wherein the frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold value according to a count decreasing speed starting from the moment when the frequency of the target processor core is controlled to decrease;

[0114] Increase the maximum frequency of the target processor core, including:

[0115] The maximum frequency after the increase is obtained according to the frequency before the increase, the third rate after the adjustment and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase.

[0116] In one embodiment of the present disclosure, the frequency control logic circuit may continuously decrease the frequency adjustment count threshold according to the count decrease speed starting from the moment when the frequency of the control target processor core is reduced, so as to obtain the frequency adjustment count value at any moment after the moment when the frequency of the control target processor core is reduced. The frequency adjustment count threshold and the count decrease speed may be preset or obtained from other devices or systems.

[0117] In one embodiment of the present disclosure, the maximum frequency after increasing is obtained according to the frequency before increasing, the third rate and the frequency adjustment count value. The frequency before increasing, the third rate and the frequency adjustment count value are brought into a preset algorithm and the maximum frequency after increasing is calculated according to the algorithm; or the frequency before increasing, the third rate and the frequency adjustment count value are taken as inputs to a pre-trained model to obtain the maximum frequency after increasing output by the model.

[0118] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the current frequency adjustment count value and the frequency before the increase of the current target processor core, the maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the obtained maximum frequency after the increase is relatively high, it may cause the frequency of the target processor core to be too high after the maximum frequency of the target processor core is set to the maximum frequency after the increase, thereby causing the target processor core to generate splitlock at a relatively high rate, and even the target processor core to generate splitlock at a rate greater than or equal to the target upper limit rate. Therefore, by making the third rate negatively correlated with the maximum frequency after the increase, it is possible to avoid the maximum frequency after the increase being high when the third rate is already in a relatively high state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment. The longer the time length, the smaller the frequency adjustment count value. Considering that the longer the time length, the greater the impact on the target processor core executing normal applications, therefore, by making the maximum frequency after the increase negatively correlated with the frequency adjustment count value, it is possible to avoid the frequency of the target processor core being in a state of being too low for a long time, so that the normal applications executed by the target processor core will not be affected too much.

[0119] In one embodiment of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate, and the frequency adjustment count value includes:

[0120] The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

[0121] The technical solution provided by the embodiment of the present disclosure can obtain the highest frequency after boosting by Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), which can more conveniently obtain the highest frequency after boosting and improve the efficiency of obtaining the highest frequency after boosting.

[0122] In one embodiment of the present disclosure, Figure 3 A schematic structural block diagram of a processor according to an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the processor 100 further includes a frequency adjustment count threshold register 104 for storing a frequency adjustment count threshold and a frequency adjustment count value register 105 for storing a frequency adjustment count value, and the frequency adjustment count threshold register 104 and the frequency adjustment count value register 105 are both connected to the frequency control logic circuit 103;

[0123] The frequency control logic circuit 103 is used to store the frequency adjustment count threshold read from the frequency adjustment count threshold register 104 in the frequency adjustment count value register 105 when the frequency of the target processor core is controlled to decrease, and continuously decrease the frequency adjustment count threshold in the frequency adjustment count value register 105 according to the count decrease speed;

[0124] Get the current frequency adjustment count value, including:

[0125] The current frequency adjustment count value is read from the frequency adjustment count value register 105 .

[0126] In one embodiment of the present disclosure, the frequency adjustment count threshold stored in the frequency adjustment count threshold register may be written into the frequency adjustment count threshold register in advance, or may be written into the frequency adjustment count threshold register by the processor itself or other devices or systems.

[0127] According to the technical solution provided by the embodiment of the present disclosure, the processor also includes a frequency adjustment count threshold register for storing a frequency adjustment count threshold and a frequency adjustment count value register for storing a frequency adjustment count value. The frequency adjustment count threshold register and the frequency adjustment count value register are both connected to the frequency control logic circuit. Since the frequency adjustment count threshold register and the frequency adjustment count value register are both located in the processor, the frequency control logic circuit in the processor has a short delay when reading the frequency adjustment count threshold from the frequency adjustment count threshold register and continuously decreasing the frequency adjustment count threshold in the frequency adjustment count value register according to the counting decrease speed, thereby improving the processing efficiency of the frequency control logic circuit.

[0128] In one embodiment of the present disclosure, the frequency control logic circuit is further used for:

[0129] In response to the frequency adjustment count value being 0, the maximum frequency of the target processor core is set as the processor core maximum frequency.

[0130] In one embodiment of the present disclosure, the maximum frequency of the processor core can be understood as the maximum frequency that the target processor core itself can reach. Setting the maximum frequency of the target processor core as the maximum frequency of the processor core can be understood as no longer placing any restrictions on the maximum frequency of the target processor core.

[0131] According to the technical solution provided by the embodiment of the present disclosure, when the frequency adjustment count value is 0, it indicates that the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment has reached the maximum time length allowed for limiting the maximum frequency of the target processor core. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application execution of the target processor core. Therefore, the frequency control logic circuit sets the maximum frequency of the target processor core to the maximum frequency of the processor core in response to the frequency adjustment count value being 0, that is, no restrictions are imposed on the maximum frequency of the target processor core, thereby ensuring that the normal application execution of the target processor core will not be affected in any way.

[0132] Figure 4 A flowchart of a processor control method according to an embodiment of the present disclosure is shown. Figure 4 As shown, the processor control method includes steps S101 and S102.

[0133] In step S101, a rate at which at least one processor core of a processor generates a split lock and an upper limit rate corresponding to the at least one processor core are obtained.

[0134] In step S102, in response to a first rate at which a target processor core in at least one processor core generates splitlock being greater than or equal to an upper limit rate corresponding to the target processor core, a maximum frequency of the target processor core is reduced, and / or an alignment check exception is triggered on the target processor core.

[0135] In one embodiment of the present disclosure, the processor may include one or more processor cores (Core), and each CPU Core may be configured with a cache (Cach). The cache is a memory located between the processor execution unit and the main memory (Dynamic Random Access Memory, DRAM), usually composed of static RAM (Static RAM, SRAM), which is small in size but has a fast access speed. The cache can be used to save a copy of part of the data in the memory. When the processor reads and writes data, it first accesses the cache. When the required data does not exist in the cache, the memory is accessed. The cache is usually divided into multiple groups, each of which is divided into multiple cache data lines (cachelines). When fetching a unit from the memory to the cache, a memory area of ​​the size of a cache data line is fetched into the cache at a time, and then stored in the corresponding cache data line.

[0136] In one embodiment of the present disclosure, the processor core generating a splitlock can be understood as the processor core generating a data read across two cache lines. In order to ensure the atomicity of the data read, the entire bus of the processor needs to be locked. This situation can be understood as the processor core generating a splitlock. Among them, the atomicity of the data read can be understood as the data read cannot be interrupted. The order cannot be disrupted, and part of the data read cannot be cut off or only part of the data read can be executed.

[0137] In one embodiment of the present disclosure, the upper limit rate can be understood as an upper limit for indicating the number of times the corresponding processor core is allowed to generate splitlocks within a unit time. For example, the unit of the upper limit rate can be times / second. If the number of times the corresponding processor core generates splitlocks within a unit time is greater than or equal to the upper limit rate, the performance of the corresponding processor core may be greatly reduced.

[0138] In one embodiment of the present disclosure, the upper limit rate may be stored in an upper limit register in advance, or may be calculated by the processor itself based on the processor's historical log according to a corresponding algorithm or model and written into the upper limit register, or may be written into the upper limit register by other devices or systems.

[0139] In one embodiment of the present disclosure, the first rate may be to detect the target processor core in real time to determine whether the target processor core generates a splitlock, and obtain the first rate according to the detection result, wherein the real-time detection of the target processor core may be to periodically detect the target processor core in real time at intervals of a preset detection time threshold, and the preset detection time threshold may be 1ms. Exemplarily, the indication information indicating whether the corresponding processor core generates a splitlock may be periodically obtained through the power management unit (Power Management Unit) in the processor at intervals of 1ms, and whether the corresponding processor core generates a splitlock is determined according to the indication information, and the rate at which the corresponding processor core generates a splitlock is further obtained.

[0140] In one embodiment of the present disclosure, the maximum frequency of the target processor core is reduced, which can be understood as setting the maximum frequency of the target processor core to a preset frequency; or, it can be pre-set for different rates of generating splitlock, and set the correspondence between the rate level and the maximum frequency, determine the target rate level corresponding to the first rate before reducing the maximum frequency of the target processor core, obtain the maximum frequency corresponding to the target rate level, and set the maximum frequency of the target processor core to the maximum frequency corresponding to the target rate level.

[0141] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the rate at which at least one processor core of the processor generates splitlock and the upper limit rate corresponding to at least one processor core, it is considered that when the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much. Therefore, it is possible to determine whether the rate at which the corresponding processor core generates splitlock is high based on the upper limit rate, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced). When the rate at which splitlock is generated is high and may reduce the performance of the target processor core too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, ensuring that the performance of the processor core is not reduced too much due to the generation of splitlock, so that related applications running on the target processor core (such as applications that may cause the generation of splitlock) can be executed normally. , and the related applications running on other processor cores will not be affected too much; in addition, the target processor core triggers the alignment check exception only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger the alignment check exception, so that the related applications running on the target processor core (such as applications that may cause splitlock to be generated) can be executed normally, and the related applications running on other processor cores will not be affected too much, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core triggers the alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, the above scheme ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0142] In one embodiment of the present disclosure, in step S102, lowering the maximum frequency of the target processor core may be achieved by the following steps:

[0143] Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

[0144] The highest frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the highest frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

[0145] In one embodiment of the present disclosure, the frequency of the target processor core before reduction can be understood as the frequency of the target processor core at a moment before the highest frequency of the target processor core is reduced. The frequency of the target processor core before reduction can be obtained from the target processor core or from other devices or systems.

[0146] In one embodiment of the present disclosure, the maximum frequency of the target processor core after reduction is obtained, and the maximum frequency of the target processor core is adjusted to the maximum frequency after reduction, until the second rate at which the target processor core generates splitlock is less than the target upper limit rate. It can be understood that the first rate of the target processor core and the frequency of the target processor core, i.e., the frequency before reduction, are periodically obtained in real time at intervals of a preset frequency reduction time threshold, and the target upper limit rate read from the target upper limit register, the first rate obtained in real time, and the frequency before reduction obtained in real time are calculated to obtain the maximum frequency of the target processor core after reduction, and adjust the maximum frequency of the target processor core to the maximum frequency after reduction. Wherein, after the maximum frequency of the target processor core is adjusted to the maximum frequency after reduction, if the rate at which the target processor core generates splitlock, i.e., the first rate, is less than the target upper limit rate, then the acquisition of the maximum frequency of the target processor core after reduction is stopped.

[0147] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the reduced maximum frequency of the target processor core and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate, it can be ensured that the reduced maximum frequency of the target processor core, i.e. the reduced maximum frequency, is continuously obtained in real time according to the target upper limit rate corresponding to the target processor core, the real-time rate at which the target processor core generates splitlock, i.e. the first rate, and the real-time frequency of the target processor core, and the maximum frequency of the target processor core is adjusted to the reduced maximum frequency until the rate at which the target processor core generates splitlock, i.e. the second rate, is less than the target upper limit rate, thereby ensuring that the maximum frequency of the target processor core can be stably reduced in stages to a range that meets the requirements, thereby avoiding large fluctuations in the performance of the target processor core due to a sharp decline.

[0148] In one embodiment of the present disclosure, the method further comprises the following steps:

[0149] Get the third rate at which the current target processor core generates splitlock;

[0150] In response to the third rate being less than the target upper limit rate, the maximum frequency of the target processor core is increased.

[0151] In one embodiment of the present disclosure, the third rate may be understood as the rate at which the target processor core generates a splitlock after the highest frequency of the target processor core is reduced.

[0152] In one embodiment of the present disclosure, the third rate may be obtained by performing real-time detection on the target processor core to determine whether the target processor core generates a split lock, and obtaining the third rate according to the detection result.

[0153] In one embodiment of the present disclosure, increasing the maximum frequency of the target processor core can be understood as periodically increasing the maximum frequency of the target processor core according to a preset frequency increase threshold and at intervals of a preset increase time threshold; or, it can also be calculated according to a preset frequency increase speed threshold and the current maximum frequency of the target processor core to obtain the maximum frequency of the target processor core after the increase at different times, and adjust the maximum frequency of the target processor core at the corresponding time.

[0154] According to the technical solution provided by the embodiments of the present disclosure, by obtaining the third rate at which the current target processor core generates splitlock, and in response to the third rate being less than the target upper limit rate, increasing the maximum frequency of the target processor core, it is possible to ensure that after the maximum frequency of the target processor core is increased, the rate at which the target processor core generates splitlock can approach the target upper limit rate, thereby ensuring that, under the premise that the performance of the processor core will not be reduced too much due to the generation of splitlock, the maximum frequency of the target processor core is increased as much as possible, thereby improving the performance of the target processor core.

[0155] In one embodiment of the present disclosure, the method further comprises the following steps:

[0156] Obtaining a current frequency adjustment count value and a frequency before the current target processor core is increased, wherein the frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold value according to a count decreasing speed starting from the moment when the frequency of the target processor core is controlled to decrease;

[0157] Increase the maximum frequency of the target processor core, including:

[0158] The maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are negatively correlated with the maximum frequency after the increase.

[0159] In one embodiment of the present disclosure, starting from the moment when the frequency of the target processor core is reduced, the frequency adjustment count threshold may be continuously reduced according to the count reduction speed, so as to obtain the frequency adjustment count value at any moment after the moment when the frequency of the target processor core is reduced. The frequency adjustment count threshold and the count reduction speed may be preset or obtained from other devices or systems.

[0160] In one embodiment of the present disclosure, the maximum frequency after increasing is obtained according to the frequency before increasing, the third rate and the frequency adjustment count value. The frequency before increasing, the third rate and the frequency adjustment count value are brought into a preset algorithm and the maximum frequency after increasing is calculated according to the algorithm; or the frequency before increasing, the third rate and the frequency adjustment count value are taken as inputs to a pre-trained model to obtain the maximum frequency after increasing output by the model.

[0161] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the current frequency adjustment count value and the frequency before the increase of the current target processor core, the maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase. Among them, considering that when the third rate is already in a relatively high state, if the obtained maximum frequency after the increase is relatively high, it may cause the frequency of the target processor core to be too high after the maximum frequency of the target processor core is set to the maximum frequency after the increase, thereby causing the target processor core to generate splitlock at a relatively high rate, and even the target processor core to generate splitlock at a rate greater than or equal to the target upper limit rate. Therefore, by making the third rate negatively correlated with the maximum frequency after the increase, it is possible to avoid the maximum frequency after the increase being high when the first rate is already in a relatively high state; and the frequency adjustment count value is inversely proportional to the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment, and the longer the time length, the smaller the frequency adjustment count value, and considering that the longer the time length, the greater the impact on the target processor core executing normal applications, therefore, by making the maximum frequency after the increase negatively correlated with the frequency adjustment count value, it is possible to avoid the frequency of the target processor core being in a state of being too low for a long time, so that the normal applications executed by the target processor core will not be affected too much.

[0162] In one embodiment of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate, and the frequency adjustment count value can be achieved by the following steps:

[0163] The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate after adjustment, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

[0164] The technical solution provided by the embodiment of the present disclosure can obtain the highest frequency after boosting by Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), which can more conveniently obtain the highest frequency after boosting and improve the efficiency of obtaining the highest frequency after boosting.

[0165] In one embodiment of the present disclosure, the method further comprises the following steps:

[0166] In response to the frequency adjustment count value being 0, the maximum frequency of the target processor core is set as the processor core maximum frequency.

[0167] In one embodiment of the present disclosure, the maximum frequency of the processor core can be understood as the maximum frequency that the target processor core itself can reach. Setting the maximum frequency of the target processor core as the maximum frequency of the processor core can be understood as no longer placing any restrictions on the maximum frequency of the target processor core.

[0168] According to the technical solution provided by the embodiment of the present disclosure, when the frequency adjustment count value is 0, it indicates that the time length from the moment when the frequency of the target processor core is controlled to be reduced to the current moment has reached the maximum time length allowed for limiting the maximum frequency of the target processor core. If the maximum frequency of the target processor core continues to be limited, it may affect the normal application execution of the target processor core. Therefore, by setting the maximum frequency of the target processor core to the maximum frequency of the processor core in response to the frequency adjustment count value being 0, that is, no restriction is imposed on the maximum frequency of the target processor core, it can be ensured that the normal application execution of the target processor core will not be affected in any way.

[0169] The following reference Figure 5 Describe a processor control device according to an embodiment of the present disclosure, Figure 5 FIG. 1 is a structural block diagram of a processor control device 200 according to an embodiment of the present disclosure.

[0170] like Figure 5 As shown, the processor control device 200 includes:

[0171] The rate acquisition module 201 is configured to acquire a rate at which at least one processor core of a processor generates a split lock and an upper limit rate corresponding to at least one processor core;

[0172] The frequency control module 202 is configured to reduce the maximum frequency of the target processor core and / or cause the target processor core to trigger an alignment check exception in response to a first rate at which the target processor core in at least one processor core generates a splitlock being greater than or equal to an upper limit rate corresponding to the target processor core.

[0173] According to the technical solution provided by the embodiment of the present disclosure, by obtaining the rate at which at least one processor core of the processor generates splitlock and the upper limit rate corresponding to at least one processor core, considering that when the rate at which the processor core generates splitlock is low, the performance of the processor core will not be reduced too much, it is possible to determine whether the rate at which the corresponding processor core generates splitlock is high based on the upper limit rate, so that when the first rate at which the target processor core generates splitlock is greater than or equal to the target upper limit rate corresponding to the target processor core (that is, the rate at which the target processor core generates splitlock is high), the maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. Among them, since the frequency of the processor core is positively correlated with the rate at which the processor core generates splitlock, the maximum frequency of the target processor core is reduced only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the normal operation of the target processor core is not affected (that is, the maximum frequency of the target processor core is not reduced). When the rate at which splitlock is generated is high and may reduce the performance of the target processor core too much, the maximum frequency of the target processor core is reduced, and the rate at which splitlock is generated is also reduced, ensuring that the performance of the processor core is not reduced too much due to the generation of splitlock, so that related applications running on the target processor core (such as applications that may cause the generation of splitlock) can be executed normally. , and the related applications running on other processor cores will not be affected too much; in addition, the target processor core triggers the alignment check exception only when the first rate at which the target processor core generates splitlock is high, which can ensure that when the rate at which splitlock is generated is low and the performance of the target processor core is not reduced too much, the target processor core will not trigger the alignment check exception, so that the related applications running on the target processor core (such as applications that may cause splitlock to be generated) can be executed normally, and the related applications running on other processor cores will not be affected too much, and the user experience will not be damaged in any way. When the rate at which splitlock is generated is high and the performance of the target processor core may be reduced too much, the target processor core triggers the alignment check exception, ensuring that the performance of the processor core will not be reduced too much due to the generation of splitlock. Therefore, the above scheme ensures that the performance of the processor core will not be reduced too much due to the generation of splitlock, while minimizing the impact on the normal execution of user applications running on the processor, thereby improving the user experience.

[0174] Those skilled in the art will understand that referring to Figure 5The described technical solution can be combined with any of the embodiments described above, so as to have the technical effect achieved by any of the embodiments described above. The specific contents can refer to the description of the above embodiments, and the specific contents will not be repeated here.

[0175] The present disclosure also provides an electronic device, Figure 6 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Figure 6 As shown, the electronic device 303 includes at least one processor 301; and a memory 302 that is communicatively connected to the at least one processor 301; wherein the memory 302 stores instructions that can be executed by the at least one processor 301, and the instructions are executed by the at least one processor 301 to implement the following steps:

[0176] In an embodiment of the present disclosure, a processor control method is provided, wherein the method comprises:

[0177] Obtaining a rate at which at least one processor core of a processor generates a splitlock and an upper limit rate corresponding to at least one processor core;

[0178] In response to a first rate at which a target processor core in at least one processor core generates splitlock being greater than or equal to an upper limit rate corresponding to the target processor core, a maximum frequency of the target processor core is reduced, and / or an alignment check exception is triggered on the target processor core.

[0179] In combination with the second aspect, in a first implementation of the second aspect of the present disclosure, reducing the maximum frequency of the target processor core includes:

[0180] Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate;

[0181] The highest frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the highest frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

[0182] In combination with the second aspect or the first implementation of the second aspect, in a second implementation of the second aspect of the present disclosure, the method further includes:

[0183] Get the third rate at which the current target processor core generates splitlock;

[0184] In response to the third rate being less than the target upper limit rate, the maximum frequency of the target processor core is increased.

[0185] In combination with the second implementation of the second aspect, in a third implementation of the second aspect of the present disclosure, the method further includes:

[0186] Obtaining a current frequency adjustment count value and a frequency before the current target processor core is increased, wherein the frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold value according to a count decreasing speed starting from the moment when the frequency of the target processor core is controlled to decrease;

[0187] Increase the maximum frequency of the target processor core, including:

[0188] The maximum frequency after the increase is obtained according to the frequency before the increase, the third rate and the frequency adjustment count value, and the maximum frequency of the target processor core is set to the maximum frequency after the increase, and the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase.

[0189] In combination with the third implementation of the second aspect, in a fourth implementation of the second aspect of the present disclosure, obtaining the highest frequency after the increase according to the frequency before the increase, the third rate, and the frequency adjustment count value includes:

[0190] The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

[0191] In combination with the third implementation of the second aspect, in a fourth implementation of the second aspect of the present disclosure, the method further includes:

[0192] In response to the frequency adjustment count value being 0, the maximum frequency of the target processor core is set as the processor core maximum frequency.

[0193] Figure 7 Schematic diagram of a computer system suitable for implementing a method according to an embodiment of the present disclosure. Figure 7 As shown, the computer system 400 includes a processing unit 401, which can perform various processes in the embodiments shown in the above figures according to the program stored in the read-only memory (ROM) 402 or the program loaded from the storage part 408 to the random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the system 400 are also stored. The processing unit 401, the ROM 402 and the RAM 403 are connected to each other through a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0194] The following components are connected to the I / O interface 405: an input section 406 including a keyboard, a mouse, etc.; an output section 407 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, a modem, etc. The communication section 409 performs communication processing via a network such as the Internet. The drive 410 is also connected to the I / O interface 405 as needed. Removable media 411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 410 as needed, so that the computer program read therefrom is installed into the storage section 408 as needed. Among them, the processing unit 401 can be implemented as a processing unit such as a CPU, a GPU, a TPU, an FPGA, an NPU, etc.

[0195] In particular, according to an embodiment of the present disclosure, the method described above with reference to the accompanying drawings can be implemented as a computer software program. Exemplarily, an embodiment of the present disclosure includes a computer program product, which includes a computer program tangibly contained on a readable medium thereof, and the computer program includes a program code for executing the method in the accompanying drawings. In such an embodiment, the computer program can be downloaded and installed from a network through a communication portion 409, and / or installed from a removable medium 411. Exemplarily, an embodiment of the present disclosure includes a readable storage medium on which computer instructions are stored, and when the computer instructions are executed by a processor, the program code for executing the method in the accompanying drawings is implemented.

[0196] The flowchart and block diagram in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the road map or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. Exemplary, two boxes represented in succession can be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0197] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0198] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the computer system described in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0199] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. The above exemplary features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) to form a technical solution.

Claims

1. A processor, wherein: The processor includes at least one processor core and at least one upper limit register; The upper limit register is used to store an upper limit rate. When a first rate at which a target processor core corresponding to the target upper limit register generates a split lock splitlock is greater than or equal to a target upper limit rate in the target upper limit register, a maximum frequency of the target processor core is reduced, and / or the target processor core triggers an alignment check exception. The target upper limit register belongs to the at least one upper limit register, and the target processor core belongs to the at least one processor core. Wherein, the processor further comprises a frequency control logic circuit, and the at least one processor core and the at least one upper limit register are both connected to the frequency control logic circuit; The frequency control logic circuit is used to obtain the rate at which at least one processor core generates splitlock, and read the upper limit rate from at least one upper limit register, and in response to the first rate being greater than or equal to the target upper limit rate, reduce the maximum frequency of the target processor core; The frequency control logic circuit is further used for: in response to the third rate at which the target processor core currently generates splitlock being less than the target upper limit rate, increasing the maximum frequency of the target processor core according to the frequency before the increase, the current frequency adjustment count value and the third rate; the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase; The current frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold according to the count decreasing speed starting from the moment when the frequency of the target processor core is controlled to be reduced.

2. The processor according to claim 1, wherein: The step of reducing the maximum frequency of the target processor core comprises: Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate; The maximum frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the maximum frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

3. The processor according to claim 1 or 2, wherein: The frequency control logic circuit is further used for: A third rate at which the current target processor core generates splitlock is obtained.

4. The processor according to claim 3, wherein: The frequency control logic circuit is further used for: The current frequency adjustment count value and the current frequency of the target processor core before the increase are obtained.

5. The processor according to claim 4, wherein: The method of obtaining the increased highest frequency includes: The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

6. The processor according to claim 5, wherein: The processor further includes a frequency adjustment count threshold register for storing the frequency adjustment count threshold and a frequency adjustment count value register for storing the frequency adjustment count value, wherein the frequency adjustment count threshold register and the frequency adjustment count value register are both connected to the frequency control logic circuit; The frequency control logic circuit is used to store the frequency adjustment count threshold read from the frequency adjustment count threshold register in the frequency adjustment count value register when controlling the frequency of the target processor core to decrease, and continuously decrease the frequency adjustment count threshold in the frequency adjustment count value register according to the count decrease speed; The obtaining of the current frequency adjustment count value includes: The current frequency adjustment count value is read from the frequency adjustment count value register.

7. A processor control method, wherein: The method comprises: Obtaining a rate at which at least one processor core of a processor generates a split lock splitlock and an upper limit rate corresponding to at least one processor core; In response to a first rate at which a target processor core among the at least one processor core generates splitlock being greater than or equal to a target upper limit rate corresponding to the target processor core, reducing a maximum frequency of the target processor core, and / or causing the target processor core to trigger an alignment check exception; The method further comprises: In response to the third rate at which the target processor core currently generates splitlock being less than the target upper limit rate, the maximum frequency of the target processor core is increased according to the frequency before the increase, the current frequency adjustment count value and the third rate; the third rate and the frequency adjustment count value are both negatively correlated with the maximum frequency after the increase; The current frequency adjustment count value is obtained by continuously decreasing the frequency adjustment count threshold according to the count decreasing speed starting from the moment when the frequency of the target processor core is controlled to be reduced.

8. The processor control method according to claim 7, wherein: The step of reducing the maximum frequency of the target processor core comprises: Obtaining the reduced maximum frequency of the target processor core, and adjusting the maximum frequency of the target processor core to the reduced maximum frequency until the second rate at which the target processor core generates splitlock is less than the target upper limit rate; The maximum frequency after reduction is obtained according to Ft1=Fc1*R / C1, Ft1 is the maximum frequency after reduction, Fc1 is the frequency of the target processor core before reduction, R is the target upper limit rate, and C1 is the first rate.

9. The processor control method according to claim 7 or 8, wherein: The method further comprises: A third rate at which the current target processor core generates splitlock is obtained.

10. The processor control method according to claim 9, wherein: The method further comprises: The current frequency adjustment count value and the current frequency of the target processor core before the increase are obtained.

11. The processor control method according to claim 10, wherein: The method of obtaining the increased highest frequency includes: The highest frequency Ft2 after the increase is obtained according to Ft2=Fc2+Fc2*(R / C2-1)*((T-Tc) / T), where Fc2 is the frequency before the increase, R is the target upper limit rate, C2 is the third rate, T is the frequency adjustment count threshold, and Tc is the frequency adjustment count value.

12. An electronic device, characterized in that: It comprises a memory and at least one processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the at least one processor to implement the method steps described in any one of claims 7-11.

13. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method steps described in any one of claims 7 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method steps described in any one of claims 7 to 11 are implemented.

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