FPGA-based flash application verification system

Abstract

The application discloses a FLASH application verification system based on FPGA, which comprises a PC, an FPGA application verification board and a FLASH subboard. The FPGA application verification board is provided with two FPGA chips; each FPGA chip is connected with the FLASH and can independently access the FLASH to perform verification operation; each FPGA is externally connected with a large-capacity 160Mb SRAM; and the NOR_FLASH and the SPI_FLASH can be verified by replacing the FLASH subboard. The application also discloses a verification method based on the system, which comprises the following steps: determining power-on sequence, JTAG function verification, digital logic verification and read-write function verification. The application has comprehensive verification function, strong universality and important significance for application verification of a series of FLASH.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of chip application verification, and relates to application verification in the field of non-volatile memory, in particular to a FLASH application verification system based on FPGA. BACKGROUND

[0002] With the development of science and technology, data storage and processing are becoming more and more important; non-volatile memory has a very wide range of applications due to its characteristic that data will not be lost after power failure.

[0003] At present, there are relatively few domestic manufacturers designing and producing FLASH for spaceflight, and the FLASH verification project is not sufficient, and cannot be compatible with different models, and most of the application verification systems and verification methods mainly verify the timing matching of FLASH, and do not have universality. Therefore, a FLASH application verification system needs to be developed, which can be used for various FLASH memories to meet the application verification requirements of non-volatile memory. SUMMARY

[0004] The technical problem of the present application is to overcome the shortcomings of the prior art and provide a FLASH application verification system with strong universality and comprehensive verification functions for the application verification of various FLASH.

[0005] To achieve the above purpose, the following technical scheme is adopted in the present application:

[0006] A FLASH application verification system based on FPGA, comprising a PC, a FLASH application verification board and a program-controlled power supply;

[0007] The FLASH application verification board comprises two FPGAs, a serial port module, a power supply module, a configuration memory connector, a JTAG and an SRAM; wherein the two FPGAs are respectively denoted as FPGA_A and FPGA_B;

[0008] When verifying the erase, write and read functions of the measured FLASH, the measured FLASH is connected with the IO port of FPGA_A; when verifying the JTAG function and the memory configuration function of the measured FLASH, the measured FLASH is connected with the configuration memory connector, which is the configuration interface of the FPGA;

[0009] The serial port module is used for connecting the PC and FPGA_A, sending the erase, write and read instructions of the PC to FPGA_A, and feeding back the results fed back by FPGA_A to the PC;

[0010] FPGA_A carries out erasing, writing and reading test to the measured FLASH according to the erasing, writing and reading instructions from the PC, collects the output data of the measured FLASH, judges whether the measured FLASH works normally according to the output data, and feeds back the judging result to the serial module;

[0011] FPGA_B collects all input and output data of the measured FLASH which is working, and sends the data to the PC through the configuration memory connector and JTAG;

[0012] PC: when verifying the erasing, writing and reading functions of the measured FLASH, sends erasing, writing and reading instructions to the serial module, receives the feedback result from FPGA_A and displays the result; when verifying the JTAG function of the measured FLASH, sends erasing, writing and reading instructions to the measured FLASH through JTAG, reads the feedback result from the measured FLASH through JTAG and displays the result; sends program configuration instructions to the measured FLASH through JTAG to verify the memory configuration function of the measured FLASH; and displays all input and output data of the measured FLASH collected by FPGA_B in real time;

[0013] The power module is used for supplying power to the FLASH application verification board, and the program-controlled power supplies power to the power module.

[0014] Preferably, the FPGA_A integrates a FLASH controller and a controllable clock unit, the FLASH controller receives the erasing, writing and reading instructions from the PC, verifies the erasing, writing and reading functions of the measured FLASH according to the instructions, collects the output data of the measured FLASH, judges whether the measured FLASH works normally, and feeds back the judging result to the serial module; the controllable clock unit is a PLL in the FPGA_A, which is used for generating two kinds of clock frequencies, one of which is used for maintaining the normal work of the FPGA_A, and the other of which is used as the input clock frequency of the measured FLASH.

[0015] Preferably, the method for verifying the erasing, writing and reading functions of the measured FLASH by the FLASH controller is as follows:

[0016] After receiving the erasing instruction from the PC, the FLASH controller sends the erasing control signal and the address to the measured FLASH, and the measured FLASH executes the erasing instruction; after the execution, the FLASH controller collects the data of all addresses of the measured FLASH, if the data is FF, it means that the erasing is successful, otherwise, the erasing fails;

[0017] After receiving the writing instruction from the PC, the FLASH controller sends the writing control signal, the input data and the address to the measured FLASH, until all addresses are written;

[0018] The FLASH controller receives the read instruction sent by the PC, collects the output data of the corresponding address of the FLASH to be tested, compares the input data and the output data, and when the read operation is completed, if the input data and the output data are always the same, the read and write functions of the FLASH to be tested are normal, and if the input data and the output data are inconsistent, the read and write functions of the FLASH to be tested are abnormal.

[0019] Preferably, the PC verifies the implementation of the JTAG function of the FLASH to be tested in the following manner:

[0020] The PC reads the preloaded data;

[0021] The PC reads the ID of the FLASH to be tested through JTAG;

[0022] The PC sends an erase instruction to the FLASH to be tested through JTAG, and after the FLASH to be tested completes the execution of the erase instruction, the PC checks the data of the corresponding address of the FLASH to be tested through JTAG by using checksum and null checking, and if the data checking is successful, it indicates that the erasing is successful, otherwise it fails;

[0023] The PC sends a write instruction to the FLASH to be tested through JTAG, and writes the preloaded data into the specified address of the FLASH to be tested;

[0024] The PC sends a read instruction to the FLASH to be tested through JTAG, reads the data from the specified address, and checks the read data with the preloaded data, and if they are consistent, it is considered that the writing and reading are successful.

[0025] Preferably, the implementation method for verifying the memory configuration function of the FLASH to be tested is as follows:

[0026] The PC sends a program configuration instruction and configuration code type data to the FLASH to be tested through JTAG, and the FLASH to be tested loads the configuration code type data; the FPGA_A is provided with an LED lamp, and the configuration code type data is used to control the LED lamp to realize the running light function;

[0027] After the FLASH to be tested completes the loading, the LED lamp on the FPGA_A is observed to see whether it can realize the running light function, and if not, the memory configuration function of the FLASH to be tested is abnormal; if it can, the FLASH to be tested is powered off and then powered on again, at this time, if it cannot realize the running light function, the memory configuration function of the FLASH to be tested is abnormal, and if it can still realize the running light function, the FLASH to be tested is soft reset;

[0028] After the soft reset, if it cannot realize the running light function, the memory configuration function of the FLASH to be tested is abnormal; if it can still realize the running light function, the memory configuration function of the FLASH to be tested is normal.

[0029] Preferably, the FPGA_B internally integrates a FLASH controller and a controllable clock unit, and externally connects the SRAM, and can send control signals, clock, address and data to the SRAM and collect the output data of the SRAM.

[0030] Preferably, the FPGA_B can also be used as a FLASH, and the JTAG of the FPGA_A is connected with the IO port of the FPGA_B.

[0031] The PC accesses the FPGA_B through JTAG instructions, and downloads a test program into the FPGA_B, and the FPGA_B becomes a FLASH to be tested.

[0032] The PC accesses the FPGA_A through JTAG instructions, and verifies the erase, write and read functions of the FPGA_B as the FLASH to be tested.

[0033] Preferably, the FLASH to be tested can also be tested for digital logic, and the method is as follows:

[0034] The JTAG of the FPGA_A is connected with the IO port of the FPGA_B, and the FLASH to be tested is connected with the IO port of the FPGA_A, and the FPGA_B at this time is regarded as a false FLASH.

[0035] The PC sends operation instructions to the FPGA_A through a serial port module, and the FPGA_A controls the FLASH to be tested to perform corresponding operations according to the operation instructions, and collects real-time data of the FLASH to be tested and feeds back the real-time data to the PC through the serial port module.

[0036] Meanwhile, the PC sends operation instructions to the FPGA_A through JTAG, and the FPGA_A controls the false FLASH to perform corresponding operations according to the operation instructions, and collects real-time data of the false FLASH and feeds back the real-time data to the PC through JTAG.

[0037] The PC simultaneously monitors the working states of the data terminals of the FLASH to be tested and the false FLASH when working, so as to determine whether the digital logic of the FLASH to be tested is accurate.

[0038] Preferably, the power module comprises a first power module and a second power module, the first power module supplies power for the FPGA_A, the serial port module and the FLASH to be tested, and the second power module supplies power for the FPGA_B and the externally connected SRAM.

[0039] Preferably, the FLASH to be tested is an SPI subboard, a NOR_FLASH subboard or a PROM subboard.

[0040] Compared with the prior art, the application has the following beneficial effects:

[0041] The FLASH application verification board can cover the application verification of nonvolatile memories such as SPI_FLASH, NOR_FLASH and PROM, and can realize function verification and configuration verification, and solves the problem that the existing FLASH application verification board can only verify a single FLASH, and greatly improves the coverage of application verification.

[0042] The FLASH application verification board has two independent FPGAs, one of which can be used as a controller, and the other as a processor, which can monitor the working state in real time and feed back to the PC, and can verify digital logic, compared with real reference devices, which can facilitate the discovery of design problems of the device to be verified, accelerate the debugging process and speed up the maturation of the device. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 It is a principle block diagram of the FLASH application system;

[0044] Figure 2 It is a signal connection diagram of the FLASH and FPGA_A;

[0045] Figure 3 It is a connection diagram of the FLASH subboard and the configuration memory connector; DETAILED DESCRIPTION

[0046] Referring to Figure 1 The FLASH application verification system includes a PC, a FLASH application verification board and a program-controlled power supply.

[0047] The FLASH application verification board includes two FPGAs, a serial module, a power module, a configuration memory connector, a JTAG, a 160Mb capacity SRAM and a FLASH to be tested.

[0048] The serial module is used for connecting the PC and the FPGA_A, sending the instructions of the PC to the FPGA_A, and feeding back the results fed back by the FPGA_A to the PC.

[0049] The FPGA_A internally integrates a FLASH controller and a controllable clock unit, the FLASH controller is connected with the FLASH to be tested, the FLASH controller receives the instructions of the PC, sends control signals, clock, address and data to the FLASH to be tested, and collects the output data of the FLASH to be tested; the controllable clock unit is an internal PLL of the FPGA, which is used for generating two clock frequencies, one of which is used to maintain the normal work of the FPGA, and the other clock frequency is used as the input clock frequency of the FLASH to be tested; whether the FLASH to be tested works normally is judged according to the output data of the FLASH to be tested, and the result is fed back to the serial module.

[0050] FPGA_B integrates FLASH controller and controllable clock unit inside, and its functions cover all the functions of FPGA_A. In addition, FPGA_B is externally connected with 160Mb SRAM, and can send control signal, clock, address and data to SRAM, and can collect the output data of SRAM.

[0051] The power module takes LTM4644 as the core device to supply power for FPGA and serial port module. The power supply is divided into two sets, and FPGA_A and FPGA_B are independently powered, and are independent of each other, and are independently controlled in power-on sequence, so as to meet the power-on sequence requirements of FPGA and the power-on sequence requirements of the measured FLASH.

[0052] The configuration memory connector is the configuration interface of FPGA, and adopts FMC connector. The connector is BGA package, and has the characteristics of multiple interfaces and high-speed interface, and is used to connect the measured FLASH and used as configuration memory.

[0053] The PC uses iMPACT software to send JTAG instructions through JTAG port, and executes various operations on the measured FLASH, and feeds back the results to the PC.

[0054] The PC sends instructions to the serial port module, receives results through the serial port, and displays them; sends JTAG instructions to JTAG, executes operations on the measured FLASH, and records the results; FPGA_B uses CHIPSCOP software to perform real-time data monitoring on the measured FLASH being worked on.

[0055] The program-controlled power supply supplies power for the power module.

[0056] According to the JTAG function of the measured FLASH, the PC sends access instructions to the measured FLASH through JTAG on the iMPCT software, and performs various functional operations on the measured FLASH through JTAG. First, the PC reads the preloaded data, then reads the ID of the measured FLASH, confirms the ID and state of the measured FLASH, and then performs the operation of erase, write and read instructions on the measured FLASH through JTAG. After the erase instruction is performed, the data is checked, and the data is checked. If the data is empty, it means that the erasing is successful, otherwise it fails. After the write operation is performed, the preloaded data is checked to determine whether the write and read are successful. All the operation results are displayed to the PC through JTAG. After the measured FLASH completes the erase, write and read functions, all the operations are successful, which means that the measured FLASH functions normally. The measured data is in MCS file format. In order to ensure the comprehensive function of the measured FLASH, the test data has incremental code type, 55AA code type, 00 code type and other special code type files; the code type capacity has full capacity code type, 1 / 2 capacity code type, 1 / 4 code type, etc., and all the JTAG function verification is completed.

[0057] According to the configuration function verification of the measured FLASH, the PC sends access instructions to the measured FLASH through JTAG, loads the configuration code type data, and the data can realize the marquee function. After the measured FLASH completes the loading of the preloaded data, the working mode of the FPGA is selected correctly. Whether the FPGA system verification board can realize the marquee function is observed. After power-off and re-power-on, whether the marquee function can be loaded again is observed. After soft reset, the marquee function can still be loaded. In this way, the memory configuration function is judged. The configuration frequency of the measured FLASH is changed, the time of successful data loading is changed, and the configuration function verification is completed.

[0058] According to the digital logic prototype verification method, the FPGA_A is used as a controller of the verification system to perform all performance operations on the FLASH. The FPGA_B is used as a processor of the verification system, can be used as the measured FLASH, and can also process data in real time and monitor the working state of the port.

[0059] The external 160Mb SRAM of the FPGA_B can expand the verification data capacity to 160Mbit. The capacity of the FPGA itself is insufficient to support large-capacity data verification, and a large-capacity memory needs to be added. The operation instruction of the SRAM is simple and easy to use, so a large-capacity SRAM is selected. The 128M data erase, write and read can be verified. In the future, if needed, it can be directly expanded to 256Mbit or larger capacity.

[0060] The iMPACT software performs this function verification. The PC accesses the FPGA_B through JTAG instructions to download the test program into the FPGA_B. At this time, the FPGA is used as the measured FLASH. Then, the PC accesses the FPGA_A through JTAG instructions to perform various operations on the FLASH. This system can verify whether the digital logic functions of the FLASH, such as erase, write and read, are correct. The JTAG of the FPGA_A is connected to the IO port of the FPGA_B, which can monitor the working state of the data terminal of the real FLASH and the fake FLASH when they are working.

[0061] The FPGA_B adds control signals, which can be used as fake FLASH and can monitor the various instruction operations of the measured FLASH by the FPGA_A. The data is observed by CHIPSCOP. When the PC executes instruction operations on the FPGA_A, the instructions are given to the real FLASH, that is, the measured FLASH added by the FPGA_B. At the same time, the instructions are given to the fake FLASH, that is, the FPGA_B is used as fake FLASH. The data is observed in real time. In this way, whether the digital logic of each instruction is different from the reference device is compared, so as to judge the accuracy of the digital logic, facilitate the discovery of the design problems of the to-be-verified device, speed up the debugging process and accelerate the maturation of the device.

[0062] FPGA_B uses CHIPSCOP to observe data in real time, JTAG accesses the Program, Erase, BlankCheck, Verify and other instructions of FPGA_A, and the data grabbing of each instruction is completed by CHIPSCOP, the data integrity of each instruction is not guaranteed, a counter can be added in the program, all data can be saved by CHIPSCOP, the abnormal data points can be triggered, the error instruction can be grabbed, and the data saving is completed.

[0063] Referring to Figure 2 According to the working mode of the measured FLASH, the PC sends corresponding function instructions to the FPGA through a serial module:

[0064] The FPGA sends control signals, data and addresses to the measured FLASH through a FLASH controller, and executes an erase instruction; after execution, the FPGA compares the saved data of all addresses, whether it is FF, if the output data is FF, it represents that the erasing is successful, and the result is fed back to the FPGA;

[0065] The FPGA sets the input clock frequency of the measured FLASH through a controllable clock unit, and sends control signals, data and addresses to the measured FLASH through a FLASH controller, the input data can be incremental code type, 00 code type, 55AA code type and the like, until all addresses are written;

[0066] The FPGA executes a read operation, and compares the input data and the output data, if the input data and the output data are the same, the program will be continued to execute, when the program execution ends, if the input data and the output data are always the same, it represents that the read and write functions of the measured FLASH are normal, if the input data and the output data are inconsistent, it represents that the read and write functions of the measured FLASH are abnormal;

[0067] The FPGA transmits the final erasing, writing and reading results to the PC through a serial module, and the PC records and displays.

[0068] Referring to Figure 3 The FLASH subboard is connected with the configuration memory connector, and is used as a configuration memory, the FLASH subboard has SPI, NOR_FLASH subboard, and more needs in the future, different types of FLASH subboards can be added, the subboard can be replaced, different types of FLASH can be verified, and the universality is extremely strong, and the cost is saved.

[0069] In one aspect, the measured FLASH adopts a connector mode, and the functions of different types of FLASH can be verified, and in another aspect, two FPGAs are adopted, each system works independently, and the working state of the other FPGA can be monitored in real time.

[0070] In summary, the application provides a FLASH application verification system and method with comprehensive verification items and strong universality. Different types of FLASH can be tested under the system, high-frequency and multi-interface connectors are used, and different types of FLASH can be verified by replacing sub-boards, thereby saving hardware costs. The application verification method based on the system has comprehensive verification functions and strong universality, which is of great significance for FLASH application verification.

[0071] The contents not described in detail in the specification of the application belong to the known technology of the skilled in the art.

Claims

1. An FPGA-based FLASH application verification system, characterized in that: The PC, the FLASH application verification board and the program-controlled power supply are included; The FLASH application verification board includes two FPGAs, a serial port module, a power supply module, a configuration memory connector, a JTAG and an SRAM, wherein the two FPGAs are denoted as FPGA_A and FPGA_B respectively; When the erasing, writing and reading functions of the FLASH under test are verified, the FLASH under test is connected with the IO port of FPGA_A; when the JTAG function and the memory configuration function of the FLASH under test are verified, the FLASH under test is connected with the configuration memory connector, which is the configuration interface of the FPGA; The serial port module is used for connecting the PC and FPGA_A, sending the erasing, writing and reading instructions of the PC to FPGA_A, and feeding back the results fed back by FPGA_A to the PC; FPGA_A performs the erasing, writing and reading test on the FLASH under test according to the erasing, writing and reading instructions of the PC, collects the output data of the FLASH under test, judges whether the FLASH under test works normally according to the output data, and feeds back the judging result to the serial port module; FPGA_B collects all the input and output data of the FLASH under test which is working, and sends the data to the PC through the configuration memory connector and the JTAG; The PC: when the erasing, writing and reading functions of the FLASH under test are verified, sends the erasing, writing and reading instructions to the serial port module, receives the results fed back by FPGA_A, and displays the results; when the JTAG function of the FLASH under test is verified, sends the erasing, writing and reading instructions to the FLASH under test through the JTAG, reads the results fed back by the FLASH under test through the JTAG, and displays the results; sends the program configuration instructions to the FLASH under test through the JTAG to verify the memory configuration function of the FLASH under test; and displays all the input and output data of the FLASH under test collected by FPGA_B in real time; The power supply module is used for supplying power for the FLASH application verification board, and the program-controlled power supply supplies power for the power supply module; The FLASH controller and the controllable clock unit are integrated in FPGA_A, the FLASH controller receives the erasing, writing and reading instructions sent by the PC, verifies the erasing, writing and reading functions of the FLASH under test according to the instructions, collects the output data of the FLASH under test, judges whether the FLASH under test works normally, and feeds back the judging result to the serial port module; the controllable clock unit is the PLL in FPGA_A, which is used for generating two clock frequencies, one of which is used for maintaining the normal work of FPGA_A, and the other of which is used as the input clock frequency of the FLASH under test; The implementation method for verifying the memory configuration function of the FLASH under test is as follows: The PC sends the program configuration instructions and the configuration code type data to the FLASH under test through the JTAG, and the FLASH under test loads the configuration code type data; an LED lamp is arranged on FPGA_A, and the configuration code type data is used for controlling the LED lamp to realize the running light function. After the measured FLASH completes loading, the LED light on the FPGA_A is observed to see whether it can realize the running light function, if not, the memory configuration function of the measured FLASH is abnormal; if yes, the measured FLASH is powered off and powered on again, at this time, if it cannot realize the running light function, the memory configuration function of the measured FLASH is abnormal, if it can still realize the running light function, the measured FLASH is soft reset; After the soft reset, if it cannot realize the running light function, the memory configuration function of the measured FLASH is abnormal; If it can still realize the running light function, the memory configuration function of the measured FLASH is normal. 2.The FPGA-based FLASH application verification system of claim 1, wherein, The method for the FLASH controller to verify the erase-write-read function of the measured FLASH is as follows: After the FLASH controller receives the erase instruction sent by the PC, the erase control signal and the address are sent to the measured FLASH, and the measured FLASH executes the erase instruction; after the execution, the FLASH controller collects the data of all addresses of the measured FLASH, if the data is FF, it represents that the erase is successful, otherwise, the erase fails; After the FLASH controller receives the write instruction sent by the PC, the write control signal, the input data and the address are sent to the measured FLASH until all addresses are written; After the FLASH controller receives the read instruction sent by the PC, the output data of the corresponding address of the measured FLASH is collected, the input data and the output data are compared, when the read operation is executed, if the input data and the output data are always the same, the read-write function of the measured FLASH is normal, if the input data and the output data are inconsistent, it represents that the read-write function of the measured FLASH is abnormal.

3. The FPGA-based FLASH application verification system of claim 1, wherein, The implementation manner for the PC to verify the JTAG function of the measured FLASH is as follows: The PC reads the preloaded data; The PC reads the ID of the measured FLASH through JTAG; The PC sends the erase instruction to the measured FLASH through JTAG, after the measured FLASH executes the erase instruction, the PC checks the data of the corresponding address of the measured FLASH through JTAG by checksum and empty checking, if the data empty checking is successful, it means that the erase is successful, otherwise, it fails; The PC sends the write instruction to the measured FLASH through JTAG, and writes the preloaded data into the specified address of the measured FLASH; The PC sends the read instruction to the measured FLASH through JTAG, reads the data from the specified address, and checks the read data and the preloaded data, if they are consistent, it is considered that the write and read are successful.

4. The FPGA-based FLASH application verification system of claim 1, wherein: The FPGA_B internally integrates the FLASH controller and the controllable clock unit, the FPGA_B externally hangs the SRAM, can send the control signal, the clock, the address and the data to the SRAM, and can collect the output data of the SRAM.

5. The FPGA-based FLASH application verification system of claim 4, wherein, The FPGA_B can also be used as the FLASH, at this time, the JTAG of the FPGA_A is connected with the IO port of the FPGA_B; The PC accesses the FPGA_B through the JTAG instruction, downloads the test program into the FPGA_B, at this time, the FPGA_B becomes the measured FLASH; PC accesses FPGA_A through JTAG instruction, and verifies the erase, write and read functions of FPGA_B as the measured FLASH.

6. The FPGA-based FLASH application verification system of claim 5, wherein, The measured FLASH digital logic verification can also be performed by the following method: The JTAG of FPGA_A is connected with the IO port of FPGA_B, and the measured FLASH is connected with the IO port of FPGA_A; the FPGA_B at this time is recorded as a false FLASH; The PC sends operation instructions to FPGA_A through the serial port module, and FPGA_A controls the measured FLASH to perform corresponding operation according to the operation instructions, and collects the real-time data of the measured FLASH and feeds back to the PC through the serial port module; Meanwhile, the PC sends operation instructions to FPGA_A through JTAG, and FPGA_A controls the false FLASH to perform corresponding operation according to the operation instructions, and collects the real-time data of the false FLASH and feeds back to the PC through JTAG; The PC simultaneously monitors the working state of the data end of the measured FLASH and the false FLASH in working, so as to judge whether the digital logic of the measured FLASH is accurate or not.

7. The FPGA-based FLASH application verification system of claim 4, wherein: The power module includes a first power module and a second power module, the first power module supplies power for FPGA_A, the serial port module and the measured FLASH, and the second power module supplies power for FPGA_B and the external SRAM.

8. The FPGA-based FLASH application verification system of claim 1, wherein: The measured FLASH is an SPI subboard, a NOR_FLASH subboard or a PROM subboard.

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