Layout Design Method for Filling Cells

Abstract

The present invention provides a layout design method for filling cells. The method provides different first and second standard cells, wherein the first and second standard cells are respectively composed of third and fourth standard cells and fifth and sixth standard cells symmetrically arranged along a baseline, and the layout shapes of the first and second standard cells at the baseline are identical. A third standard cell is designed, wherein the layout of the third standard cell has the same shape as the third and sixth standard cells spliced ​​along the baseline; and the third standard cell is inserted between the first and second standard cells. The present invention enables a set of standard cell libraries to be applicable to two design standard platforms, thereby improving development efficiency, saving development costs, and optimizing the design and development process of the standard cell library.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout design method for a filling unit. Background Art

[0002] Under the current layout design rules, the standard cell library in the prior art provides two standard cell design standards, depending on whether there is horizontal offset or not, which are applicable to different design platforms. Figure 1 、 2 They are the typical standard units of these two sets of design standards. Figure 1 The left and right edges of CELLBNDY (standard cell boundary layer) coincide with the center line of Poly (gate). Figure 2 CELLBNDY will extend outward (half the distance between adjacent Poly). Due to different design standards, the two standard cells can only be used independently.

[0003] Therefore, a filling cell that can be applied to both design standards is needed to improve development efficiency, save development costs, and optimize the design and development process of the standard cell library. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a layout design method for filling cells, which is used to solve the problem in the prior art that under the current layout design rules, two standard cells can only be used independently due to different design standards.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a layout design method for a filling unit, comprising:

[0006] Step 1: providing first and second standard cells for different design standards, wherein the first and second standard cells have the same design standards at the baseline;

[0007] Step 2: designing a third standard cell, wherein the design standards of the left and right parts of the layout of the third standard cell are respectively the same as the design standards of the left and right parts of the first and second standard cells;

[0008] Step 3: Insert a third standard cell between the first and second standard cells. Preferably, the design standards for the layouts of the first, second, and third standard cells in steps 1 to 3 include: cell height, power bus width, ground bus width, gate horizontal wiring spacing, P / N region boundary, N-well edge, and active area edge.

[0009] Preferably, the design standard of the third standard cell in step 2 is determined based on basic parameters of a corresponding standard cell library and minimum design rules in a design rule file required for tape-out.

[0010] Preferably, in step three, the distance between the third standard cell and the first and second standard cells is zero or half the distance between two adjacent gate center lines.

[0011] Preferably, the first standard cell in step 1 includes: a first standard cell boundary layer, a first active area pattern located within the first standard cell boundary layer, and first gate patterns equidistantly distributed on the active area pattern, wherein the gate patterns at both ends partially overlap with edges of the first active area pattern and the first standard cell boundary layer;

[0012] The second standard cell includes: a second standard cell boundary layer, a second active area pattern located in the second standard cell boundary layer, second gate patterns equidistantly distributed in the active area pattern, and second gate patterns equidistantly distributed on the active area pattern, wherein the second gate patterns at both ends share the same boundary with the second active area pattern.

[0013] Preferably, in step 1, the first and second standard cell boundary layers and the first and second gate patterns have the same height.

[0014] Preferably, the third standard cell in step 2 includes: a third standard cell boundary layer, a third active area pattern located in the third standard cell boundary layer, third gate patterns equidistantly distributed in the active area pattern, and third gate patterns equidistantly distributed on the active area pattern, wherein one end of the third active area pattern shares a same boundary with the third standard cell boundary layer, the third gate pattern at one end partially overlaps with the third active area pattern and the third standard cell boundary layer at the shared boundary, and the third gate pattern on the other side shares a same boundary with the third active area pattern.

[0015] Preferably, the graphic designs of the first, second and third standard cells in steps one to three include rectangular patterns and edges.

[0016] Preferably, the method is used for layout design of FinFETs.

[0017] As described above, the layout design method of the filling unit of the present invention has the following beneficial effects:

[0018] The present invention enables one set of standard cell libraries to be applicable to two design standard platforms, thereby improving development efficiency, saving development costs, and optimizing the design and development process of the standard cell library. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram showing a standard cell of a design standard in the prior art;

[0020] Figure 2 A schematic diagram of a standard cell showing another design standard of the prior art;

[0021] Figure 3 Shown is a schematic diagram of a filling unit of the present invention;

[0022] Figure 4 Shown is a schematic diagram of the filling unit layout of the present invention;

[0023] Figure 5 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] See also Figure 5 The present invention provides a layout design method for a filling unit, comprising:

[0026] Step 1: providing first and second standard units (10, 20) with different design standards, wherein the design standards of the first and second standard units (10, 20) are the same at a reference line, wherein the reference line is a center line of the same design standard structure of the first and second standard units (10, 20);

[0027] For example, Figure 1 、 Figure 2 In the two standard cells shown respectively, the position of the reference line is the midline of the middle poly.

[0028] In an optional embodiment, the layout design is formed by multiple layers of different layers, see Figure 1 and Figure 2 The first standard cell 10 in step 1 includes: a first standard cell boundary layer 103, a first active area pattern 104 located within the first standard cell boundary layer 103, and first gate patterns 105 equidistantly distributed on the active area pattern, wherein the gate patterns at both ends partially overlap with the edge portions of the first active area pattern 104 and the first standard cell boundary layer 103;

[0029] The second standard cell 20 includes: a second standard cell boundary layer 203, a second active area pattern 204 located within the second standard cell boundary layer 203, second gate patterns 205 equidistantly distributed within the active area pattern, and second gate patterns 205 equidistantly distributed on the active area pattern. The second gate patterns 205 at both ends share the same boundary with the second active area pattern 204.

[0030] In an optional embodiment, the first and second gates on both sides may be dummy gate layouts.

[0031] In an optional embodiment, in step 1, the heights of the boundary layers of the first and second standard cells (10, 20) and the heights of the first and second gate patterns are the same.

[0032] Step 2: designing a third standard cell 30, wherein the design standards of the left and right parts of the layout of the third standard cell 30 are respectively the same as the design standards of the left and right parts of the first and second standard cells along the baseline;

[0033] It should be understood that the design standards of the left and right parts of the layout of the third standard cell 30 may also be the same as the design standards of the left and right parts of the second and first standard cells, respectively.

[0034] In an optional implementation manner, the design standard of the third standard cell in step 2 is determined based on basic parameters of a corresponding standard cell library and minimum design rules in a design rule file required for tape-out.

[0035] In an optional embodiment, referring to 3, the third standard cell 30 in step 2 includes: a third standard cell boundary layer 303, a third active area pattern 304 located within the third standard cell boundary layer 303, third gate patterns 305 equidistantly distributed within the active area pattern, and third gate patterns 305 equidistantly distributed on the active area pattern, wherein one end of the third active area pattern 304 shares a common boundary with the third standard cell boundary layer 303, the third gate pattern 305 at one end partially overlaps with the third active area pattern 304 and the third standard cell boundary layer 303 at the shared boundary, and the third gate pattern 305 at the other side shares a common boundary with the third active area pattern 304.

[0036] In an optional embodiment, the graphic design of the first, second, and third standard cells in steps one to three includes rectangular patterns and edges, and the basic parameters of the filling cell (third standard cell 30) are determined based on the corresponding standard cell library parameters. The basic parameters of the standard cell library include: cell height, power bus width, ground bus width, Poly (gate) horizontal wiring spacing, P / N region boundary, N well edge, and active area edge; the basic parameters of the layout design of the filling cell include: cell height, power bus width, ground bus width, Poly horizontal wiring spacing, P / N region boundary, N well edge, and active area edge, and the layout design is performed based on these basic parameters;

[0037] Design the filling cells in the layout design software according to the basic parameters of the filling cells and the layout design rules. Specifically:

[0038] Determine the fill cell height. The fill cell height is the same as the relative height of all cells in the corresponding standard cell library, and the relative height is the height relative to the origin;

[0039] Determine the power bus width of the fill cell. The power bus width of the fill cell is the same as the power bus width of all cells in the corresponding standard cell library;

[0040] Determine the ground bus width of the fill cell. The ground bus width of the fill cell is the same as the ground bus width of all cells in the corresponding standard cell library;

[0041] Determine the spacing size of the horizontal Poly wiring track of the filling unit;

[0042] Determine the position of the boundary between the PMOS region and the NMOS region of the filling cell. The position of the boundary between the PMOS region and the NMOS region of the filling cell is the same as the relative position of all cells in the corresponding standard cell library, and the relative position is the position relative to the origin;

[0043] Determine the N-well area of ​​the fill cell;

[0044] Determine the active area of ​​the filled cell.

[0045] Step 3, please refer to Figure 4 , a third standard cell 30 is inserted between the first and second standard cells (10, 20).

[0046] In an optional embodiment, in step three, the distance between the third standard cell 30 and the first and second standard cells (10, 20) is zero or half the distance between two adjacent gate center lines.

[0047] In an optional embodiment, the method is used for layout design of a FinFET.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] In summary, the present invention enables a single standard cell library to be compatible with two design standard platforms, improving development efficiency, reducing development costs, and optimizing the design and development process for the standard cell library. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A layout design method for filling cells, characterized in that: At least: Step 1: providing first and second standard cells for different design standards, wherein the first and second standard cells have the same design standards at the baseline; Step 2: Design a third standard cell, wherein the design standards of the left and right portions of the layout of the third standard cell are respectively the same as the design standards of the left and right portions of the first and second standard cells along the reference line, wherein the third standard cell comprises: a third standard cell boundary layer, a third active area pattern located within the third standard cell boundary layer, third gate patterns equidistantly distributed within the active area pattern, and third gate patterns equidistantly distributed on the active area pattern, wherein one end of the third active area pattern shares a common boundary with the third standard cell boundary layer, the third gate pattern at one end partially overlaps with the third active area pattern and the third standard cell boundary layer at the common boundary, and the third gate pattern at the other side shares a common boundary with the third active area pattern; Step 3: inserting a third standard cell between the first and second standard cells.

2. The method for designing a layout of a filling unit according to claim 1, wherein: The design standards for the layouts of the first, second and third standard cells in steps one to three include: cell height, power bus width, ground bus width, gate horizontal wiring spacing, P / N region boundary, N well edge and active area edge.

3. The method for designing a layout of a filling unit according to claim 1, wherein: The design standard of the third standard cell in step 2 is determined based on basic parameters of a corresponding standard cell library and minimum design rules in a design rule file required for tape-out.

4. The method for designing a layout of a filling unit according to claim 3, wherein: In step three, the distance between the third standard cell and the first and second standard cells is zero or half the distance between two adjacent gate center lines.

5. The method for designing a layout of a filling unit according to claim 1, wherein: The first standard cell in step 1 includes: a first standard cell boundary layer, a first active area pattern located within the first standard cell boundary layer, and first gate patterns equidistantly distributed on the active area pattern, wherein the gate patterns at both ends partially overlap with edges of the first active area pattern and the first standard cell boundary layer; The second standard cell includes: a second standard cell boundary layer, a second active area pattern located in the second standard cell boundary layer, second gate patterns equidistantly distributed in the active area pattern, and second gate patterns equidistantly distributed on the active area pattern, wherein the second gate patterns at both ends share the same boundary with the second active area pattern.

6. The method for designing a layout of a filling unit according to claim 5, wherein: In step 1, the heights of the first and second standard cell boundary layers and the first and second gate patterns are the same.

7. The method for designing a layout of a filling unit according to claim 1, wherein: The graphic designs of the first, second and third standard cells in steps one to three include rectangular patterns and edges.

8. The method for designing a layout of a filling unit according to claim 1, wherein: The method is used for the layout design of a FinFET.

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