A method for identifying a device in a current leakage loop

Abstract

The present invention provides a method for identifying a device in a current leakage loop, including: obtaining layout information, identifying M0 that connects at least two active regions as the first M0; respectively denoting the enclosed regions formed by adjacent first M0s and the two active regions they connect as loop_holes, and expanding the loop_holes into the smallest rectangles and identifying them as the first rectangles; identifying the overlapping regions between the expanded first rectangles and the first M0 as the first regions; in the graphic region obtained by subtracting M0 from the effective active regions, denoting the regions in contact with the first rectangles as the first active regions; and determining whether the device is a device in the current leakage loop according to the positional relationship between both sides of the gate of the device and the first active regions. It provides an effective and concise method for optimizing design, improving production efficiency, improving processes, and reducing quality risks.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor design and production, and in particular relates to a method for identifying whether a device is in a current leakage loop according to a layout. Background Art

[0002] As the design scale of integrated circuits continues to expand, the density of electronic devices on a single chip is increasing, and the characteristic size of electronic devices is getting smaller and smaller. At the same time, the integrated circuit process contains many complex process steps, and each step has a specific process manufacturing deviation, which leads to a decrease in the yield of integrated circuit chips. In the context of manufacturability design, in order to improve the yield of integrated circuit products and shorten the yield maturity cycle, the industry generally adopts a testing method based on specially designed test chips, and obtains the necessary data for process and design yield improvement through testing of test chips.

[0003] In some finished test chips, the M1 and upper metal layers in the product layout will be removed first, and then after selecting the device in the product layout, a new layer of M1 will be added to implement the connection test. When selecting the test device after removing M1 and upper metal layers, when the device in the current leakage loop is selected as the test object, all other devices in the loop should be turned off, but in fact, other devices are in a suspended state not connected to any pad, the potential is unstable, and the on-off state cannot be controlled. They may be turned on to generate leakage current, and then interfere with the current flowing through the target device through the current leakage loop. Therefore, when selecting the test object, you should try to avoid selecting devices in the current leakage loop. If it is unavoidable, you need to mark the device as being in the current leakage loop to facilitate the consideration of the influence of the floating gate when analyzing the data.

[0004] Therefore, how to quickly and effectively find the device in the current leakage loop in this case becomes the key. It can be seen that if there is no effective method that can be used to identify whether a device is in the current leakage loop, it is very unfavorable to optimize the design and improve production efficiency, and it is also not conducive to improving the process and reducing quality risks. Summary of the invention

[0005] The present invention is made based on all or part of the problems of the above-mentioned prior art, and aims to provide a method for identifying devices in a current leakage loop to guide the improvement of design, production and process.

[0006] All explanations or definitions of the terms and related technical principles involved in the following description of this application are merely illustrative and not restrictive.

[0007] A method for identifying devices in a current leakage loop provided by the present invention includes: Step S1. Obtain layout information, including an active region layer, an M0 layer, a gate layer, an M0 cut layer, and a polysilicon cut layer; the M0 is used to connect the active regions; the M0 connecting at least two active regions is identified as the first M0. Step S2. Respectively record the closed regions surrounded by adjacent first M0s and the two active regions they connect as loop_holes, and expand the loop_holes into the smallest rectangles to be identified as the first rectangles; assume the gate extension direction is the vertical direction, and the direction perpendicular to the gate extension direction is the horizontal direction; move the vertical sides of the first rectangles outward along the horizontal direction by a preset distance to expand the first rectangles, and the overlapping regions of the expanded first rectangles and the first M0s are identified as the first regions. Step S3. In the graphic region obtained by subtracting M0 from the effective active regions, the regions in contact with the first rectangles are recorded as the first active regions; the effective active regions refer to the active regions in the active region layer minus the active regions after the gates in the gate layer. Step S4. Determine whether the device is a device in the current leakage loop according to the positional relationship between the two sides of the gate of the device and the first active regions. In general, in step S4, the identification method is that if the active regions contacted by both sides of the device gate are the first active regions, then the device is in the current leakage loop.

[0008] The layout information further includes a polysilicon cut layer, and the gate is the effective gate region obtained by subtracting the cut region in the polysilicon cut layer from the gate region in the gate layer.

[0009] As a further improvement, the preset distance in step S2 is less than the width of M0; the width of M0 refers to the width in the horizontal direction of the M0 pattern.

[0010] As an exemplary embodiment, the preset distance is 1 nm.

[0011] The M0 layer is preferably the first metal layer.

[0012] In a feasible implementation, the layout information further includes the M0 cut layer, and the M0 is the effective M0 region obtained by subtracting the cut region in the M0 cut layer from the M0 pattern region in the M0 layer.

[0013] In an advantageous embodiment, the device is a MOSFET device.

[0014] Identify the first active region diagonally adjacent to the first region as the second active region.

[0015] In a preferred embodiment of the present invention, the risk level of the device in the current leakage loop is also evaluated.

[0016] Specifically, the risk level is at least divided into three levels, as follows: If the active regions contacted on both sides of the gate of the device are both the first active regions but not the second active regions, that is, the gate of the device only contacts the first active regions that are not the second active regions, the risk level of the device is evaluated as low; if one side of the gate of the device contacts the first active region but not the second active region, and the other side contacts the second active region, that is, one side of the gate of the device contacts the first active region that is not the second active region, and the other side contacts the second active region, the risk level of the device is evaluated as medium; if the active regions contacted on both sides of the gate of the device are both the second active regions, that is, the gate of the device only contacts the second active regions, the risk level of the device is evaluated as high.

[0017] The present invention has the following beneficial effects: According to a method for identifying a device in a current leakage loop involved in the present invention, by identifying the first active region, the positional relationship between both sides of the gate of the device and the first active region can be intuitively judged to identify whether the device in the layout is in the current leakage loop. Since constructing the first region can identify the second active region, the device in the current leakage loop can be more accurately identified, and the risk level can be evaluated. It is convenient to subsequently count the quantity and distribution of such risks in the layout, and provide guidance for the positioning and analysis of such risks in the layout and the design of the test structure. It provides an effective and simple method for the optimization of the design, the improvement of production efficiency, the improvement of the process, and the reduction of quality risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a method for identifying a device in a current leakage loop in Embodiment 1 of the present invention.

[0019] Figure 2 is a schematic diagram of the process of forming the first rectangle and the first region in Embodiment 1 of the present invention.

[0020] Figure 3 is a schematic diagram of the first active region in Embodiment 1 of the present invention.

[0021] Figure 4 is a schematic diagram of the second active region in Embodiment 2 of the present invention.

[0022] Figure 5 is a schematic diagram of evaluating different risk levels in Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings.

[0024] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure. In the following embodiments, the operations of the embodiments are depicted in a specific order. The description of these orders is for better understanding of the details in the embodiments to comprehensively understand the present invention, but the description of these orders does not necessarily correspond one-to-one with the method of the present invention, nor can the scope of the present invention be limited thereby.

[0025] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible operation processes of the methods according to the embodiments of the present invention. It should also be noted that in some alternative implementations, the functions marked in the blocks may also occur in a different order than that marked in the accompanying drawings. For example, two consecutively represented blocks may actually be executed substantially in parallel, and they may sometimes be executed in an interleaved manner, depending on the purposes to be achieved by the steps involved. In addition, each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and manual operations.

[0026] In the embodiments of the present invention, a MOSFET device is taken as an example of the device for illustration. In the layout, an effective MOSFET device refers to the overlapping region located between each active region and the gate, and the overlapping region needs to meet the following conditions: 1) Both sides of the overlapping region are in contact with the active region. If the gate located at the edge of the active region has an active region on only one side, it cannot be used as a device; 2) The overlapping region is covered by a layer representing N- or P-type doping, as well as other layers characterizing the basic conditions of the device; 3) The overlapping region is not covered by any layer indicating a non-MOSFET device. The above example is for facilitating the understanding of the present invention, but the scope of the present invention cannot be limited thereby.

[0027] When removing the M1 and higher-level metals in the product layout, only M0 can connect the active regions, and the distribution and routing of M0 are regular and must be in the middle of the gate (gate). Therefore, it can provide as Figure 1A method for judging whether a device is in a current leakage loop according to a layout, which is used to judge MOSFET devices in the front-middle section layout. In an integrated circuit, the front-end process FEOL for manufacturing the device part refers to the front section, the semiconductor middle process MEOL for manufacturing M0 and CT refers to the middle section, and the back-end process BEOL for the connection part after manufacturing refers to the back section. The steps of the method for judging whether a device is in a current leakage loop according to the layout are specifically introduced below.

[0028] Embodiment 1

[0029] As Figure 1 shown, the method for identifying a device in a current leakage loop disclosed in the embodiment of the present invention includes: Step S1. Obtain layout information, including an active region layer, an M0 layer, a gate layer, an M0 cut layer, and a polysilicon cut layer; the M0 is used to connect the active regions; the M0 connecting at least two active regions is identified as the first M0; Step S2. Respectively record the enclosed regions formed by adjacent first M0s and the two active regions they connect as loop_holes, and expand the loop_holes into the smallest rectangles and identify them as the first rectangles; assume that the gate extension direction is the vertical direction, and the direction perpendicular to the gate extension direction is the horizontal direction; move the vertical sides of the first rectangles along the horizontal direction outward by a preset distance respectively to expand the first rectangles, and the overlapping regions of the expanded first rectangles and the first M0 are identified as the first regions; Step S3. In the graphic region obtained by subtracting M0 from the effective active regions, the regions in contact with the first rectangles are recorded as the first active regions; the effective active regions refer to the active regions in the active region layer minus the active regions after the gates in the gate layer; Step S4. Judge whether the device is a device in a current leakage loop according to the positional relationship between both sides of the gate of the device and the first active region.

[0030] Combined with Figure 2 shown, for the convenience of understanding rather than limiting the present invention, in this embodiment, a better case is taken as an example for description. Among them, the M0 layer is the first metal M0 layer. For the gate and M0, only the effective gate and effective M0 are referred to. The effective gate refers to the gate region in the gate layer minus the cut region in the polysilicon cut layer, and the effective M0 refers to the M0 region in the M0 layer minus the cut region in the M0 cut layer. The M0 layer is used to connect the active regions, and the M0 connecting at least two active regions, that is, the first M0, is denoted as M0A_connection. Among them, there is M0A_connection that only connects two active regions, and there is also M0A_connection that connects more than 2 active regions (such as Figure 2 the 3 active regions shown in the example).

[0031] In this embodiment, in step S2, the first rectangle is formed by expanding the region loop_holes enclosed by two adjacent first M0s, namely M0A_connection and the two active regions it connects, in the gate extension direction, and respectively obtaining the rectangle with the smallest area containing it, denoted as loop_holes_fix, that is, the first rectangle. Assume the orientation of M0 is longitudinal and the orientation of the active region is transverse; move the longitudinal sides of the loop_holes_fix outward by a preset distance respectively to achieve the expansion of loop_holes_fix; the overlapping region between the expanded loop_holes_fix and M0A_connection, that is, the first region, is denoted as loop_M0A. In a better case, the preset distance is less than the width of M0. In this embodiment, a preferred preset distance is 1 nm.

[0032] The effective active region is denoted as sd, that is, the source / drain region obtained by subtracting the gate region in the gate layer from the active region in the layer. The region in the graphic region obtained by subtracting M0 from sd and in contact with the loop_holes_fix is denoted as loop_region, that is, the first active region.

[0033] In this embodiment, for each MOSFET device in the layout, it is judged that: if the active regions on both sides of the gate of the device are both loop_region, that is, the gate of the device is in contact with the loop_region, it indicates that the device is in the current leakage loop.

[0034] Embodiment 2

[0035] The difference between Embodiment 2 and Embodiment 1 is only that in step S4, the risk level of the device in the current leakage loop is also evaluated. As Figure 4 shown and with reference to Figure 5 . In step S4, the region in the first active region loop_region that is diagonally connected to the first region loop_M0A is identified as the second active region, denoted as loop_sd_connection. If the active regions on both sides of the gate of the device are both the loop_region, that is, the gate of the device only contacts the loop_region, it indicates that the device is in the current leakage loop and the risk level is level 1, and it is evaluated as having a low risk. For reference, see Figure 5Devices marked as 1 in the figure; if the active area on one side of the gate of the device is the loop_region, and the active area on the other side is the loop_sd_connection, that is, one side of the gate of the device is in contact with the loop_region, and the other side is in contact with the loop_sd_connection, then it indicates that the device is in the current leakage loop, and the risk level is level 2, which is assessed as having a medium risk. One side of the source / drain region of the device directly forms a current loop through M0, which can be referred to Figure 5 Device marked as 2 in the figure; if the active areas on both sides of the gate of the device are the loop_sd_connection, that is, the gate of the device is only in contact with the loop_sd_connection, it means that the device is in the current leakage loop, and the risk level is level 3, which is assessed as high risk. The source / drain areas of the device directly form a current loop through M0, which can be referred to Figure 5 The device marked as 3 in the figure. Figure 5 The black box in the middle indicates the current leakage loop. The above classification into 1-3 levels to indicate low, medium and high risks is only an example for the convenience of explanation in this embodiment, and more levels can also be pre-classified according to actual needs, and it is not limited.

[0036] It should be noted that the above examples are only specific embodiments of the present invention. Obviously, the present invention is not limited to the above examples, and many variations are possible. All variations that can be directly derived or associated with the contents disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

[0037] The above embodiments are preferred examples of the present invention and are not intended to limit the scope of protection of the present invention. For the purpose of clear description, many implementation details are described together in the above description. However, it should be understood that these implementation details should not be used to limit the present invention.

[0038] The technical solutions between some practices described in the embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in the field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

Claims

1. A method for identifying a device in a current leakage loop, characterized in that: Including: Step S1. Obtain layout information, including an active region layer, an M0 layer, a gate layer, an M0 cut layer, and a polysilicon cut layer; The M0 is used to connect active regions; the M0 connecting at least two active regions is identified as the first M0; Step S2. Respectively denote the enclosed regions formed by adjacent first M0s and the two active regions they connect as loop_holes, and expand the loop_holes into the smallest rectangles and identify them as the first rectangles; Assume the gate extension direction is the vertical direction, and the direction perpendicular to the gate extension direction is the horizontal direction; move the vertical sides of the first rectangle outward along the horizontal direction by a preset distance to expand the first rectangle, and identify the overlapping region between the expanded first rectangle and the first M0 as the first region; Step S3. In the graphic region obtained by subtracting M0 from the effective active regions, denote the region in contact with the first rectangle as the first active region; The effective active region refers to the active region in the active region layer minus the active region after the gate in the gate layer; Step S4. Determine whether the device is a device in the current leakage loop according to the positional relationship between the two sides of the gate of the device and the first active region.

2. The method for identifying a device in a current leakage loop according to claim 1, wherein: In step S4, the discrimination method is that if the active regions contacted by both sides of the device gate are the first active region, then the device is in the current leakage loop.

3. A method for identifying a device in a current leakage loop according to claim 1, characterized in that: The layout information further includes a polysilicon cut layer, and the gate is the effective gate region obtained by subtracting the cut region in the polysilicon cut layer from the gate region in the gate layer.

4. A method for identifying a device in a current leakage loop according to claim 1, characterized in that: The preset distance in step S2 is less than the width of M0; the width of M0 refers to the width in the horizontal direction of the M0 pattern.

5. A method for identifying a device in a current leakage loop according to claim 4, characterized in that: The preset distance is 1 nm.

6. A method for identifying a device in a current leakage loop according to claim 1, characterized in that: The layout information further includes the M0 cut layer, and the M0 is the effective M0 region obtained by subtracting the cut region in the M0 cut layer from the M0 pattern region in the M0 layer.

7. A method for identifying a device in a current leakage loop according to claim 1, characterized in that: The device is a MOSFET device.

8. A method for identifying a device in a current leakage loop according to any one of claims 1-7, characterized in that: Identify the first active region diagonally connected to the first region as the second active region.

9. A method for identifying a device in a current leakage loop according to claim 8, characterized in that: It further includes evaluating the risk level of the device in the current leakage loop.

10. A method for identifying a device in a current leakage loop according to claim 9, characterized in that: The risk level is at least divided into three levels; among them: If the active regions contacted by both sides of the device gate are the first active region but not the second active region, that is, the gate of the device only contacts the first active region that is not the second active region, then evaluate the risk level of the device as low; If one side of the device gate contacts the first active region that is not the second active region, and the other side contacts the second active region, that is, one side of the device gate contacts the first active region that is not the second active region, and the other side contacts the second active region, then evaluate the risk level of the device as medium; If the active regions contacted by both sides of the device gate are the second active region, that is, the gate of the device only contacts the second active region, then evaluate the risk level of the device as high.

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