System and method for dual pulse programming

Abstract

A non-volatile memory device includes control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line corresponding to a first set of data states are inhibited from programming with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to discharge a first voltage of the selected word line to a second voltage level corresponding to a second program voltage, such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming. A method of programming memory cells of a non-volatile memory is also disclosed.

Description

Technical Field

[0001] This invention relates to the operation of memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, etc. In EEPROM or flash NAND array architectures, memory cells can be arranged in a matrix of rows and columns, such that the gate of each memory cell is coupled to a word line via a row. Memory cells can also be arranged in strings, such that memory cells in a given string are coupled together in series from source to drain via a common source line and a common bit line. Summary of the Invention

[0003] One aspect of this disclosure relates to a non-volatile memory including control circuitry for performing programming and verification operations to program an array of memory cells of the non-volatile memory. The control circuitry is configured to apply a first programming voltage to a selected word line during repeated execution of the programming and verification operations. The selected word line may include a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states. Programming of corresponding memory cells in the first subset of memory cells with the first programming voltage may be disabled. The first programming voltage may be applied to the second subset of memory cells corresponding to the second set of data states. The control circuitry may be further configured to discharge a first voltage level on the selected word line corresponding to the first programming voltage to a second voltage level corresponding to a second programming voltage, such that the second programming voltage is applied to at least the first subset of memory cells. The control circuitry may be further configured to perform a verification portion of the programming and verification operations to verify whether the first subset and the second subset of memory cells have been successfully programmed.

[0004] Another aspect of this disclosure relates to a method for programming memory cells of a non-volatile memory. The method includes, as an iterative part of programming and verification operations, applying a first programming voltage to a selected word line. The selected word line may include a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states. Programming of corresponding memory cells in the first subset of memory cells with the first programming voltage may be disabled. The first programming voltage may be applied to the second subset of memory cells corresponding to the second set of data states. The method further includes discharging a first voltage level on the selected word line corresponding to the first programming voltage to a second voltage level corresponding to a second programming voltage, such that the second programming voltage is applied to at least the first subset of memory cells. The method further includes, as an iterative part of programming and verification operations, performing a verification operation to verify whether the first subset and the second subset of memory cells have been successfully programmed.

[0005] Another aspect of this disclosure relates to a memory device including control circuitry for programming memory cells. The memory cells may be part of an array of memory cells of non-volatile memory. The control circuitry may be configured to apply a first programming voltage to a selected word line. The selected word line may include a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states. Programming of corresponding memory cells in the first subset of memory cells with the first programming voltage may be disabled. The first programming voltage may be applied to the second subset of memory cells corresponding to the second set of data states. The control circuitry may be further configured to discharge a first voltage level of the selected word line corresponding to the first programming voltage to a second voltage level corresponding to a second programming voltage, such that the second programming voltage is applied to at least the first subset of memory cells. The control circuitry may be further configured to perform a verification portion of programming and verification operations to verify whether the first subset and the second subset of memory cells have been successfully programmed. Attached Figure Description

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of this disclosure and, together with the description, serve to explain its principles. Where convenient, the same reference numerals will be used throughout the drawings to refer to the same or similar elements.

[0007] Figure 1A A block diagram illustrating an example memory device.

[0008] Figure 1B The diagram illustrates a block diagram of an example control circuit, including programming circuits, counting circuits, and determining circuits.

[0009] Figure 2A schematic diagram illustrating three memory string architectures based on the principles of this disclosure.

[0010] Figure 3 This illustrates the memory cell blocks in an example two-dimensional configuration of the memory array in Figure 1.

[0011] Figure 4A This illustrates a cross-sectional view of an example floating-gate memory cell in a NAND string.

[0012] Figure 4B illustrate Figure 4A The structure is shown in the cross-sectional view along line 429.

[0013] Figure 5A This shows a cross-sectional view of an instance charge-trapping memory cell in a NAND string.

[0014] Figure 5B illustrate Figure 5A The structure is shown in the cross-sectional view along line 429.

[0015] Figure 6A This is an example block diagram illustrating the sensing block SB1 in Figure 1.

[0016] Figure 6B Another example block diagram illustrating the sensing block SB1 in Figure 1.

[0017] Figure 7A This is a perspective view illustrating the block set in an example three-dimensional configuration of the memory array in Figure 1.

[0018] Figure 7B illustrate Figure 7A A cross-sectional view of a portion of a block.

[0019] Figure 7C illustrate Figure 7B A plot of the diameter of the memory holes in the stack.

[0020] Figure 7D illustrate Figure 7B A close-up image of the stacked area 622.

[0021] Figure 8A illustrate Figure 7B A top view of the stacked instance word line layer WLL0.

[0022] Figure 8B illustrate Figure 7B A top view of the stacked instance of the top dielectric layer DL19.

[0023] Figure 9A illustrate Figure 8A The NAND string of the sub-blocks SBa to SBd.

[0024] Figure 9B This describes another instance view of the NAND string within the sub-block.

[0025] Figure 10 Describe the Vth distribution of memory cells in an instance programming operation with four data states.

[0026] Figure 11 Describe the Vth distribution of memory cells in an instance programming operation with eight data states.

[0027] Figure 12 Describe the Vth distribution of memory cells in an instance programming operation with sixteen data states.

[0028] Figure 13 Describe the Vth distribution of memory cells in instance programming and verification operations with at least four data states.

[0029] Figure 14 This describes the voltages applied to the various components of the memory block during instance programming and verification operations.

[0030] Figures 15A to 15F This describes an example procedure for programming memory cells selected word lines.

[0031] Figure 16 A flowchart illustrating a method for performing programming and verification operations to program a set of memory cells for a selected word line, based on the principles of this disclosure. Detailed Implementation

[0032] The following discussion relates to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure (including the claims). Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is merely illustrative and not intended to imply that the scope of this disclosure (including the claims) is limited to the described embodiments.

[0033] Programming and verifying an array of memory cells typically involves applying a series of programming voltages to selected word lines of memory cells after they have been provided in an erased data state. Each programming voltage is provided in a programming loop, also known as an iteration of the programming and verifying operation. For example, the programming voltage may be applied to a word line connected to the control gate of a memory cell. In one approach, incremental step pulse programming is performed, where the programming voltage increases by one step in each programming loop. A verification operation may be performed after each programming voltage to determine whether the memory cell has been successfully programmed. Upon successful programming of a memory cell, it may be locked to prevent further programming as other memory cells are programmed in subsequent programming loops. The programming and verifying operation may be a multi-step programming and verifying operation, a full-sequence or single-step programming and verifying operation, or another type of programming and verifying operation.

[0034] Each memory cell can be associated with a data state based on the data written in the programming command. A memory cell can be in an erased data state (referred to herein as the erased data state) or can be programmed to a programmed data state different from the erased data state (referred to herein as the programmed data state). For example, in a two-bit memory device per cell, there are four data states, including the erased data state and three programmed data states referred to as data states A, B, and C (see [link to documentation]). Figure 10 In each three-cell memory device, there are eight data states, including an erased data state and seven programmed data states referred to as A, B, C, D, E, F, and G (see [link to relevant documentation]). Figure 11 In each four-bit memory unit, there are sixteen data states, including erased data states called Er, A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O, and fifteen programmed data states (see [link to documentation]). Figure 12 These states can also be numerically referred to as data states 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15.

[0035] When a programming command is issued, the data to be written is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell is to be programmed. Each programmed data state is associated with a verification voltage such that the memory cell is considered programmed when a read (sensing) operation determines that the threshold voltage (Vth) of the memory cell with a given data state is higher than the associated verification voltage. The read (sensing) operation determines whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, such that Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, such that Vth is higher than the control gate voltage.

[0036] However, many techniques or configurations for programming memory cells are not efficient and / or effective at enabling fast programming. For example, in one known method, an incrementally increasing programming pulse is applied with each repetition of the programming operation. Under this method, the long charging time of selected and unselected word lines can delay the completion of the programming operation. In this and other methods, inefficient techniques for programming typically require more repetitions to complete the programming (e.g., compared to the techniques described herein), further increasing the total programming time and / or total verification time.

[0037] Some embodiments described herein include control circuitry for a memory device that uses multiple programming pulses to program a set of memory cells on a selected word line. For example, the control circuitry may apply a first programming voltage (VpgmH) to the selected word line, which includes a first subset of memory cells corresponding to a low data state and a second subset of memory cells corresponding to a high data state. Programming of the first subset of memory cells corresponding to the low data state with the first programming voltage (VpgmH) may be disabled. For example, the control circuitry may have previously provided a programmable disable voltage (VDDSA) to the bit line associated with the first subset of memory cells. Thus, the first programming voltage (VpgmH) can be used to program the second subset of memory cells corresponding to the high data state (instead of the first subset of memory cells corresponding to the low data state).

[0038] Furthermore, the control circuitry can discharge the voltage level of the bit lines associated with a first subset of memory cells from a first voltage level corresponding to the programmable disable voltage (VDDSA) to a second voltage level corresponding to zero volts. This will allow programming of the first subset of memory cells. Next, the control circuitry can discharge the voltage level of the selected word line from a first voltage level corresponding to the first programming voltage (VpgmH) to a smaller second voltage level corresponding to the second programming voltage (VpgmL). For example, the control circuitry can be configured to wait for a threshold time period before verifying whether the memory cells of the selected word line have been programmed. During the threshold wait time period, the voltage level of the selected word line (and / or the voltage level at each corresponding memory cell) can dissipate to a value corresponding to the second programming voltage (VpgmL). This will allow programming of the first subset of memory cells corresponding to the low data state using the second programming voltage (VpgmL), while programming of the second subset of memory cells corresponding to the high data state using or to be used with the first programming voltage (VpgmH). The control circuitry can then perform a verification operation to verify whether both the first and second subsets of memory cells have been programmed.

[0039] In this way, the control circuit uses multiple programming voltages to program the set of memory cells for a selected word line. Furthermore, the control circuit saves resources (e.g., processing resources, memory resources, etc.) by reducing the execution time of programming and verification operations compared to other known systems and methods (e.g., requiring more voltage pulses for programming, having higher total programming time, etc.).

[0040] Figure 1A This is a block diagram of an example memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 (e.g., a memory cell array), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through decoder 132. Read / write circuitry 128 includes multiple sensing blocks SB1, SB2…SBp (sensing circuitry) and allows for parallel reading or programming of memory cell pages. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0041] Memory structure 126 may be two-dimensional or three-dimensional. Memory structure 126 may include one or more memory cell arrays, including three-dimensional arrays. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory layers are formed on (but not within) a single substrate (e.g., a wafer), without intervening in the substrate. Memory structure 126 may include any type of non-volatile memory, which is monolithically formed in one or more physical layers of a memory cell array having active regions disposed on a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is on or within the substrate.

[0042] Control circuitry 110 collaborates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations.

[0043] For example, a storage area 113 may be provided for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact wire connector thickness parameters, verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire array of NAND strings, the location of the memory cell within a specific group of NAND strings, the location of the memory cell on a specific plane, etc. Contact wire connector thickness parameters may indicate the thickness of the contact wire connector, the substrate or material included with the contact wire connector, etc.

[0044] On-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operation. The power control module may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0045] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than memory structure 126 (individually or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any one or a combination of the following: control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2...SBp, read / write circuit 128, controller 122, etc.

[0046] The control circuitry may include programming circuitry configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuitry performs programming on a word line, after which the programming circuitry applies a verification signal to the word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for the one data state. The control circuitry may also include a determining circuit configured to determine a specific programming and verification iteration among the plurality of programming and verification iterations based on an amount by which the count exceeds a threshold, in which a verification test for another data state is performed on the memory cells assigned to represent another data state.

[0047] For example, Figure 1B This is a block diagram of an example control circuit 150, which includes a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0048] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct several read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0049] Storage devices 122a and 122b include code, such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from a reserved area of ​​memory cells in storage device 126a of memory structure 126, such as one or more word lines. For example, controller 122 may use the code to access memory structure 126, for example, for programming, reading, and erasing operations. The code may include startup code and control code (e.g., an instruction set). Startup code is software that initializes controller 122 during a startup or boot process and enables controller 122 to access memory structure 126. Controller 122 may use the code to control one or more memory structures 126. Upon power-up, processor 122c fetches startup code from ROM 122a or storage device 126a for execution, and the startup code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code contains drivers for performing basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0050] Generally, control code may contain instructions for performing the functions described herein (including steps in the flowcharts discussed further below) and provide voltage waveforms, including voltage waveforms discussed further below.

[0051] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices for communicating with one or more processors.

[0052] Other types of non-volatile memory besides NAND flash memory can also be used.

[0053] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”); non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices can be configured in either NAND or NOR configurations.

[0054] Memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optionally steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0055] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. As a non-limiting example, a flash memory device (NAND memory) configured as NAND typically contains memory elements connected in series. A NAND string is an example of a series-connected collection of transistors including memory cells and SG transistors.

[0056] NAND memory arrays can be configured such that the array consists of multiple memory strings, wherein a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two-dimensional or three-dimensional form, such as two-dimensional memory structures or three-dimensional memory structures.

[0057] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device layer. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory elements (e.g., in an xy-direction plane). The substrate may be a wafer on which the memory elements are formed, or it may be a carrier substrate attached to the memory elements after the memory elements are formed. As a non-limiting example, the substrate may contain a semiconductor such as silicon.

[0058] Memory elements can be arranged in an ordered array of rows and / or columns within a single memory device hierarchy. However, memory elements can be arranged irregularly or non-orthogonally. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0059] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device layers, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the z direction is generally perpendicular to the main surface of the substrate, and the x and y directions are generally parallel to the main surface of the substrate).

[0060] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device layers. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., extending generally perpendicular to the main surface of the substrate, i.e., columns extending in the y-direction), each column having multiple memory elements. These columns can be arranged, for example, in a two-dimensional configuration in the xy-plane, thereby producing a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

[0061] In a non-limiting example, in a three-dimensional NAND string array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0062] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared, or intervening layers may be present between memory device levels.

[0063] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory layers on individual substrates and then stacking the memory layers on top of each other. The substrate can be thinned or removed from the memory device layers before stacking, but since the memory device layers are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Additionally, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on individual chips and then packaged together to form a stacked-chip memory device.

[0064] Figure 2 The diagram illustrates three types of memory architectures utilizing interleaved memory strings. For example, reference numeral 201 shows a schematic diagram of a first instance memory architecture, reference numeral 203 shows a schematic diagram of a second instance memory architecture, and reference numeral 205 shows a schematic diagram of a third instance memory architecture. In some embodiments, as shown, the memory architecture may comprise an array of interleaved NAND strings.

[0065] Referring to memory architecture 201, memory strings are shown in rows 207-0 to 207-7 of memory architecture 201. A memory string may contain a collection of memory cells (e.g., a collection corresponding to memory holes). Each row is shown as having four ends to the memory string. Memory strings may be connected to adjacent strings at the ends (not visible below this figure). The first group of rows 207-0 to 207-3 is shown on the upper left of dummy row 208. The second group of rows 207-4 to 207-7 is shown on the upper right of dummy row 208. Dummy row 208 separates the two groups of rows in eight interleaved rows. Source line 209 is located at the edge of the first group and away from dummy row 208. Source line 210 is located at the edge of the second group and away from dummy row 208 and source line 209.

[0066] Aside from the addition of extra groups, memory architectures 203 and 205 can be similar to the architecture of memory architecture 201. Memory architecture 203 can be twice the size of memory architecture 201 and can contain sixteen strings, where each group of four rows is separated by a dummy line. Memory architecture 205 can be larger than both memory architectures 201 and 203. Memory architecture 205 can contain twenty strings, where each group of four rows is separated by a dummy line 208.

[0067] In some embodiments, memory architectures 201, 203, and / or 205 may include an under-array chip structure. For example, memory architectures 201, 203, and / or 205 may include an under-array chip structure, thereby controlling circuitry under a memory array comprising a group of memory strings. Using an under-array chip structure, the memory strings may include direct strip contacts for source lines for read and erase operations.

[0068] In memory architecture 205, there may be five NAND string groups. In the example shown, each corresponding NAND string group may be separated by dummy rows 208. In this example, there are two outermost NAND string groups, two inner NAND string groups (inner being relative to the outermost NAND string groups), and one innermost NAND string group.

[0069] In some embodiments, memory architecture 205 may be a three-dimensional memory architecture comprising one or more three-dimensional blocks. In this case, the three-dimensional block may be logically segmented into multiple sub-blocks corresponding to NAND string groups. The three-dimensional block may also be segmented into multiple planes. Further block descriptions are provided herein.

[0070] It should be understood that Figure 2 The memory architectures shown are provided as examples. In practice, the techniques described herein can be implemented on any number of different memory architectures, such as pipe-type BiCS (P-BiCS), vertical recessed array transistor (VRAT) architectures, and / or any other type of EEPROM or flash memory architecture.

[0071] Figure 3The memory cell blocks 300 and 310 in an example two-dimensional configuration of the memory structure 126 of Figure 1 are illustrated. The memory structure 126 may contain a plurality of such blocks 300 and 310. Each example block 300, 310 contains several NAND strings and corresponding bit lines, such as BL0, BL1, etc., which are shared within the block. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND string is connected at the other end to a source-side select gate (SGS), which is then connected to a common source line 320. For example, sixteen word lines, WL0 to WL15, extend between the SGS and the SGD. In some cases, dummy word lines without user data may also be used in memory arrays adjacent to the select gate transistors. Such dummy word lines can protect edge data word lines from certain edge effects.

[0072] One type of non-volatile memory that can be provided in a memory array is, for example... Figure 4A and 4B The floating gate memory shown is of the type illustrated. However, other types of non-volatile memory can also be used. This will be discussed in further detail below. Figure 5A and 5B In another example shown, a charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric, formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”), is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a finite region. This stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. Similar cells can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0073] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain. The charge of one data bit is located adjacent to the drain in the dielectric layer, and the charges of other data bits are located adjacent to the source in the dielectric layer. Multi-state data storage is obtained by individually reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0074] Figure 4ACross-sectional views of example floating-gate memory cells 400, 410, and 420 in a NAND string are shown. In this figure, the bit line or NAND string direction enters the page, and the word line direction is from left to right. As an example, word line 424 extends across the NAND string containing corresponding channel regions 406, 416, and 426. Memory cell 400 includes a control gate 402, a floating gate 404, a tunnel oxide layer 405, and a channel region 406. Memory cell 410 includes a control gate 412, a floating gate 414, a tunnel oxide layer 415, and a channel region 416. Memory cell 420 includes a control gate 422, a floating gate 421, a tunnel oxide layer 425, and a channel region 426. Each memory cell 400, 410, and 420 is located in a different corresponding NAND string. An inter-silicon dielectric (IPD) layer 428 is also shown. Control gates 402, 412, and 422 are portions of the word line. Figure 4B A cross-sectional view along line 429 is provided.

[0075] Control gates 402, 412, and 422 are wound around floating gates 404, 414, and 421, thereby increasing the surface contact area between control gates 402, 412, and 422 and floating gates 404, 414, and 421. This results in higher IPD capacitance, leading to a higher coupling ratio that makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between memory cells 400, 410, and 420 becomes smaller, so there is almost no space between two adjacent control gates 402, 412, and 422 for control gates 402, 412, and IPD layer 428.

[0076] As an alternative example, such as Figure 5A and 5B As shown, planar or flat memory cells 500, 510, and 520 have been developed, wherein control gates 502, 512, and 522 are planar or flat; that is, the control gate does not wrap around the floating gate and it only contacts the charge storage layer 528 above it. In this case, there is no advantage in having a high floating gate. In fact, it makes the floating gate thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0077] Figure 5ACross-sectional views depicting example charge-trapping memory cells 500, 510, and 520 in a NAND string are shown. The views are taken in the word line direction of memory cells 500, 510, and 520, which are two-dimensional examples of memory cells 500, 510, and 520 in memory structure 126 of FIG. 1, including a flat control gate and charge-trapping regions. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator, such as a SiN film, to store electrons, compared to floating-gate MOSFET technology which uses conductors such as doped polysilicon to store electrons. As an example, word line 524 extends across a NAND string containing corresponding channel regions 506, 516, and 526. A portion of the word line provides control gates 502, 512, and 522. Below the word line are IPD layer 528, charge-trapping layers 504, 514, and 521, polysilicon layers 505, 515, and 525, and tunneling layers 509, 507, and 508. Each charge trapping layer 504, 514, 521 extends continuously within the corresponding NAND string. The flat configuration of the control gate can be thinner than that of a floating gate. Additionally, memory cells can be placed closer together.

[0078] Figure 5B illustrate Figure 5A The structure is shown in a cross-sectional view along the contact line connector 529. The NAND string 530 includes an SGS transistor 531, instance memory cells 500, 533…535, and an SGD transistor 536. Passages in the IPD layer 528 of the SGS transistor 531 and SGD transistor 536 allow the control gate 502 to communicate with the floating gate layer. For example, the control gate 502 and the floating gate layer may be polysilicon and the tunnel oxide layer may be silicon oxide. The IPD layer 528 may be, for example, a stack of nitride (N) and oxide (O) in a NONON configuration.

[0079] NAND strings can be formed on a substrate including a p-type substrate region 555, an n-type well 556, and a p-type well 557. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0080] Figure 6AThis illustrates an example block diagram of the sensing block SB1 in Figure 1. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 650a, 651a, 652a, and 653a are associated with data latches 650b, 651b, 652b, and 653b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and handled by a corresponding processor in each sensing block. For example, a sensing circuit controller 660 in SB1 can communicate with the collection of sensing circuits and latches. The sensing circuit controller 660 may include a precharge circuit 661 that provides voltage to each sensing circuit for setting a precharge voltage. In one possible approach, for example via... Figure 6B The data bus 603 and local buses (e.g., LBUS1 or LBUS2) independently supply voltage to each sensing circuit. In another possible method, for example via... Figure 6B The contact lines 605 in the circuit provide a common voltage to each sensing circuit in parallel. The sensing circuit controller 660 may also include a memory 662 and a processor 663. The memory 662 may store code executable by the processor to perform the functions described herein. These functions may include reading latches 650b, 651b, 652b, 653b associated with sensing circuits 650a, 651a, 652a, 653a, setting bit values ​​in the latches, and providing voltages for setting pre-charge levels in the sensing nodes of sensing circuits 650a, 651a, 652a, 653a. Further illustrative details of the sensing circuit controller 660 and sensing circuits 650a and 651a are provided below.

[0081] refer to Figure 6B The sensing circuit controller 660 can communicate with different sensing circuits 650a, 651a, for example, in a time-multiplexed manner. In one method, contact line 605 can be connected to voltage clamps 621, 641 in each sensing circuit 650a, 651a.

[0082] Each sensing circuit 650a, 651a includes latches 650b, 651b, which include trip latches 626, 646, offset verification latches 627, 647, and data status latches 628, 648. Voltage clamps 621, 641 can be used to set the pre-charge voltage at sensing nodes 622, 642. Sensing nodes are selectively allowed to communicate with bit lines 625, 645 by bit line (BL) switches 623, 643, and voltage clamps 624, 644 can set the voltage on bit lines 625, 645, for example, during sensing or programming operations. Bit lines 625, 645 are connected to one or more memory cells, such as memory cells MC1 and MC2. In some cases, local buses LBUS1 and LBUS2 allow the sensing circuit controller 660 to communicate with components in sensing circuits 650a and 651a, such as latches 650b and 651b and voltage clamps 621 and 641. To communicate with sensing circuits 650a and 651a, the sensing circuit controller 660 provides voltage to transistors 604 and 606 via contact lines 601 and 602 to connect LBUS1 and LBUS2 to DBUS 603. Communication may include sending data to and / or receiving data from sensing circuits 650a and 651a.

[0083] Sensing circuit 650a may be a first sensing circuit including a first trip latch 626, and sensing circuit 651a may be a second sensing circuit including a second trip latch 646. Sensing circuit 650a is an example of a first sensing circuit including a sensing node 622, wherein the first sensing circuit is associated with a first memory cell MC1 and a bit line 625. Sensing circuit 651a is an example of a second sensing circuit including a sensing node 642, wherein the second sensing circuit is associated with a second memory cell MC2 and a bit line 645.

[0084] In some embodiments, a memory cell may include a flag register containing a set of latches storing flag bits. In some embodiments, the value of the flag register may correspond to a value of data state. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the flag bits may modify associated logic of the device, such as address decoding circuitry, to select a specific cell block. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag registers or a combination of flag registers and address registers, as in implicit addressing, or alternatively by direct addressing using only address registers.

[0085] Figure 7AThis is a perspective view of a block set 700 in an example three-dimensional configuration of the memory structure 126 of Figure 1. The substrate has example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 704 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 705 that can be connected to the control gate layer of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, control gate layers at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are driven together. The substrate 701 may also carry the circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned along conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in an intermediate region 702 of the memory device. In an upper region 703 of the memory device, one or more upper metal layers are patterned along conductive paths to carry signals from the circuitry. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked region of memory cells, wherein alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides, with vertical direct contacts extending upwards from said layered sides to an upper metal layer to form connections to conductive paths. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y directions may be used.

[0086] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0087] Figure 7B illustrate Figure 7A A cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3 is shown. The block comprises a stack 710 of alternating conductive and dielectric layers. In this example, in addition to the data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, a region of the stack 710 comprising NAND strings NS1 and NS2 is illustrated. Each NAND string encompasses memory vias 718 and 719, which are filled with material forming memory cells adjacent to the word lines. Figure 7D The region 722 of stack 710 is shown in more detail below and discussed in further detail below.

[0088] Stack 710 includes a substrate 711, an insulating film 712 on the substrate 711, and a portion of a source line SL. NS1 has a source terminal 713 at the bottom 714 of the stack and a drain terminal 715 at the top 716 of the stack 710. Contact line connectors (e.g., slots, such as metal-filled slots) 717, 720 may be provided periodically across the stack 710 as interconnects extending through the stack 710 to connect source lines to specific contact lines above the stack 710. Contact line connectors 717, 720 may be used during word line formation and subsequently metal-filled. A portion of a bit line BL0 is also illustrated. A conductive via 721 connects the drain terminal 715 to BL0.

[0089] Figure 7C illustrate Figure 7B A plot of the diameter of the memory holes in the stack. The vertical axis is perpendicular to... Figure 7B The stack alignment and the width (wMH) of memory holes 718 and 719 are indicated, for example, the diameter. Figure 7A Word line layers WLL0 to WLL10 are repeated as examples and are located at corresponding heights z0 to z10 in the stack. In this memory device, the memory vias etched through the stack have extremely high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory vias can vary along the length of the via. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, making the diameter slightly wider before gradually decreasing from the top to the bottom of the memory via.

[0090] Due to the non-uniformity of memory via width, the programming speed, which includes the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via (e.g., based on the height of the memory cell in the stack). Using smaller diameter memory vias results in a relatively stronger electric field across the tunnel oxide, leading to relatively higher programming and erase speeds. One approach is to define a group of adjacent word lines with similar memory via diameters (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line within the group. Different groups can have different optimized verification schemes.

[0091] Figure 7D illustrate Figure 7BA close-up view of region 722 of stack 710. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 780, 781 are provided above dummy memory cells 782, 783 and data memory cells MC. Several layers may be deposited, for example, along the sidewalls (SW) of memory via 730 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 730) may include a charge trapping layer or film 763 (e.g., SiN or other nitrides), a tunneling layer 764, a polysilicon body or channel 765, and a dielectric core 766. Word line layers may include a barrier oxide / bulk high-k material 760, a metal barrier 761, and a conductive metal 762 (e.g., tungsten) as a control gate. For example, control gates 790, 791, 792, 793, and 794 are provided. In this example, all layers except the metal are provided in memory via 730. In other methods, some of the layers may be located within the control gate layer. Additional pillars are similarly formed within different memory vias. The pillars can form pillared active regions (AA) of the NAND string.

[0092] When programming a memory cell, electrons are stored in a portion of a charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through a tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0093] Each of the memory vias 730 may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer 763, a tunneling layer 764, and a channel layer. The core region of each of the memory vias 730 is filled with the host material, and the multiple annular layers are located between the core region and the word line in each of the memory vias 730.

[0094] NAND strings can be viewed as having floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0095] Figure 8A illustrate Figure 7B A top view of an example word line layer WLL0 of stack 710. As mentioned, a three-dimensional memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for SG transistors and memory cells. The layer for the SG transistors is an SG layer and the layer for the memory cells is a word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. As a result, a vertical NAND string is formed. Source lines are connected to the NAND string below the stack, and bit lines are connected to the NAND string above the stack.

[0096] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each sub-block comprising a group of NAND strings sharing a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBBa, SBb, SBc, and SBd, respectively. Furthermore, the word line layer within the block can be divided into regions. Each region is located within a corresponding sub-block and can extend between contact line connectors (e.g., slots) periodically formed in a stack to process the word line layer during the manufacturing process of the memory device. This processing may involve replacing the sacrificial material of the word line layer with metal. Typically, the distance between contact line connectors should be relatively small to account for limitations on the distance that etchant can travel laterally to remove the sacrificial material, and the distance that metal can travel to fill gaps (created by the removal of sacrificial material). For example, the distance between contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also consider limitations on the number of bit lines that can extend across regions when each bit line is connected to a different memory cell. After processing the word line layer, the contact line connectors can optionally be filled with metal to provide interconnects across the stack.

[0097] In this example, four rows of memory holes exist between adjacent contact line connectors. Here, the rows are groups of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the density of the memory holes. The word line layer or word line is divided into regions WLL0a, WLL0b, WLL0c, and WLL0d, each connected by a free contact line 813. In one method, the last region of the word line layer in a block may be connected to the first region of the word line layer in the next block. The contact line 813 is then connected to a voltage driver for the word line layer. Region WLL0a has example memory holes 810, 811 along contact line 812. Region WLL0b has example memory holes 814, 815. Region WLL0c has example memory holes 816, 817. Region WLL0d has example memory holes 818, 819. Figure 8B The memory holes are also shown. Each memory hole can be a portion of the corresponding NAND string. For example, memory holes 810, 814, 816, and 818 can be portions of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0098] Each circle represents a cross-section of a memory via at a word line layer or SG layer. Example circles shown in dashed lines represent memory cells containing material within the memory via and supplied by adjacent word line layers. For example, memory cells 820 and 821 are in WLL0a, memory cells 824 and 825 are in WLL0b, memory cells 826 and 827 are in WLL0c, and memory cells 828 and 829 are in WLL0d. These memory cells are at a common height in the stack.

[0099] Contact line connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, 804 may be located between and adjacent to the edges of regions WLL0a to WLL0d. Contact line connectors 801, 802, 803, 804 provide a conductive path from the bottom to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, wherein the conductive line is connected to a voltage driver in a peripheral region of the memory device. Figure 8A For further details on the subblocks SBa to SBd, see also Figure 9A .

[0100] Figure 8B illustrate Figure 7B The image shows a top view of the top dielectric layer DL19 of an example stack. The dielectric layer is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows for the parallel programming of a set of memory cells in a region of the word line layer, where each memory cell is located in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0101] Region DL19a has example memory holes 810, 811 along contact line 812a, which coincides with bit line BL0. Several bit lines extend above the memory holes and connect to memory holes as indicated by the "X" symbol. BL0 connects to a set of memory holes including memory holes 811, 815, 817, and 819. Another example bit line BL1 connects to a set of memory holes including memory holes 810, 814, 816, and 818. Also described is from... Figure 8A The contact line connectors (e.g., slits, such as metal-filled slits) 801, 802, 803, 804, extend vertically through the stack. The contact lines can be numbered sequentially from BL0 to BL23 across the DL19 layers in the x-direction.

[0102] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in the adjacent cell row (the first row adjacent to the right edge). BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in the adjacent memory cell row (the first row adjacent to the left edge).

[0103] Figure 9A illustrate Figure 8A The NAND string of the sub-blocks SBa to SBe. Sub-blocks and Figure 7B The structure is consistent. The conductive layers in the stack are illustrated on the left for reference. Each sub-block contains multiple NAND strings, with one instance NAND string specified. For example, SBa includes instance NAND string NS0, SBb includes instance NAND string NS1, SBc includes instance NAND string NS2, SBd includes instance NAND string NS3, and SBe includes instance NAND string NS4.

[0104] Additionally, NS0_SBa includes SGS transistors 900 and 901, dummy memory cells 902 and 903, data memory cells 904, 905, 906, 907, 908, 909, 910, 911, 912, 913 and 914, dummy memory cells 915 and 916, and SGD transistors 917 and 918.

[0105] NS1_SBb includes SGS transistors 920 and 921, dummy memory cells 922 and 923, data memory cells 924, 925, 926, 927, 928, 929, 930, 931, 932, 933 and 934, dummy memory cells 935 and 936, and SGD transistors 937 and 938.

[0106] NS2_SBc includes SGS transistors 940 and 941, dummy memory cells 942 and 843, data memory cells 944, 945, 946, 947, 948, 949, 950, 951, 952, 953 and 954, dummy memory cells 955 and 956, and SGD transistors 957 and 958.

[0107] NS3_SBd includes SGS transistors 960 and 961, dummy memory cells 962 and 963, data memory cells 964, 965, 966, 967, 968, 969, 970, 971, 972, 973 and 974, dummy memory cells 975 and 976, and SGD transistors 977 and 978.

[0108] NS4_SBe includes SGS transistors 980 and 981, dummy memory cells 982 and 983, data memory cells 984, 985, 986, 987, 988, 989, 990, 991, 992, 993 and 994, dummy memory cells 995 and 996, and SGD transistors 997 and 998.

[0109] At a given height within a block, the memory cells in each sub-block are at a common height. For example, a set of memory cells (containing memory cell 904) is situated among multiple memory cells formed along tapered memory vias in a stack of alternating conductive and dielectric layers. This set of memory cells is at a specific height z0 within the stack. Another set of memory cells (containing memory cell 924) connected to a word line (WLL0) is also at a specific height. In another approach, another set of memory cells (e.g., containing memory cell 912) connected to another word line (e.g., WLL8) is at another height (z8) within the stack.

[0110] Figure 9B This illustrates another instance view of the NAND strings within a sub-block. The NAND strings comprise NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, each with 48 word lines (e.g., WL0 to WL47). Each sub-block comprises a group of NAND strings extending in the x-direction and sharing a common SGD line (e.g., SGD0, SGD1, SGD2, SGD3, or SGD4). In this simplified example, only one SGD transistor and one SGS transistor exist in each NAND string. The NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe reside in sub-blocks SBa, SBb, SBc, SBd, and SBe, respectively. Furthermore, an instance grouping of word lines G0, G1, and G2 is illustrated.

[0111] Figure 13The waveforms illustrate the example programming and verification operations. The horizontal axis indicates the programming loop number, and the vertical axis indicates the programming voltage and the programming verification voltage. Each iteration of the example programming and verification operation may involve applying multiple programming voltages (e.g., VpgmH and VpgmL) and one or more verification voltages (e.g., VvA, VvB, etc.) to a selected word line. In some embodiments, this may be based on a given memory cell corresponding to a low data state (e.g., S1 to S8 or...). Figure 12 In the middle of the state (A to H), it is still a high data state (e.g., S9 to S15 or...). Figure 12 The states I to O in the code are used to apply each programming voltage to a specific memory cell or group of memory cells on a selected word line. This is combined with... Figures 15A to 15F Additional information related to these embodiments is described.

[0112] For simplicity, a waveform is described for each programming or verification voltage. The waveform can be any number of shapes, such as the shape shown, a square, a multi-layered shape, a slanted shape, etc. Furthermore, although one or more embodiments refer to multiple programming voltages as including two programming voltages (VpgmH and VpgmL), it should be understood that this is provided by way of example. In practice, more than two programming voltages can be used to program memory cells. For example, the memory cells of a selected word line can be segmented into three or more groups of memory cells, where each group corresponds to a set or range of data states. In this example, a separate programming voltage can be used to program each corresponding group of memory cells.

[0113] As used herein, the set of programming voltages and the set of verification voltages used for programming and verification operations can be collectively referred to as a pulse train. The set of programming voltages may contain a first subset and a second subset of programming voltages. The first subset of programming voltages may be applied to memory cells corresponding to high data states and may be represented as VpgmH1, VpgmH2…VpgmH… n , where n equals the number of iterations performed to successfully program the memory cell. A second subset of the programming voltage can be applied to the memory cells corresponding to the low data state, and can be represented as VpgmL1, VpgmL2...VpgmL n , where n equals the number of iterations performed to successfully program the memory cell. In some embodiments, the control circuitry may be configured to increase the amplitude of each programming voltage (e.g., VpgmH, VpgmL, etc.) for each successive iteration of the programming and verification operation. For example, a voltage bias (dVpgm) and / or similar voltage values ​​may be used to increase the programming voltage. In some embodiments, the number of verification voltages used to verify whether a memory cell has been programmed may be based, for example, on the number of target data states for positive verification. The number of target data states for positive verification may, for example, correspond to the number of memory cells associated with a word line.

[0114] In some embodiments, each repetition of the programming and verification operation may include a pulse train of two programming voltages and one or more verification voltages. The following description will illustrate seven example repetitions of the programming and verification operation.

[0115] As a basic step (not shown), a programmable disable voltage (VDDSA) may first be provided to the bit lines associated with the low data state, temporarily disabling the programming of memory cells connected to each corresponding bit line. To begin programming the memory cells corresponding to the high data state, a first programming voltage, such as programming voltage 1001, is provided to the selected word line. Programming of the memory cells associated with the low data state is disabled based on the provided programmable disable voltage (VDDSA).

[0116] Next, the bit line associated with the low data state memory cell can be discharged from a voltage level corresponding to the programmable disable voltage (VDDSA) to zero volts (or the voltage level that enables programming for each memory cell associated with the low data state). Next, the voltage level of the selected word line can be discharged from a voltage level corresponding to the first programming voltage to a voltage level corresponding to, for example, the programming voltage 1008.

[0117] After the voltage level of the selected word line is discharged to the voltage level corresponding to the second programming voltage, a first verification voltage, such as verification voltage 1015, is provided to the selected word line. The programming voltage and the corresponding verification voltage can be separated by applying zero volts (0V) to the selected word line between the programming voltage and the verification voltage. In this way, the first programming voltage can be used to begin programming memory cells corresponding to a high data state, the second programming voltage can be used to begin programming memory cells corresponding to a low data state, and the first verification voltage can be used to attempt to verify at least a subset of all memory cells.

[0118] The second repetition of the programming and verification operation may include a first programming voltage 1002, a second programming voltage 1009, and a verification voltage 1015. The first programming voltage 1002 and the second programming voltage 1009 have each been increased by dVpgm from the first programming voltage 1001 and the second programming voltage 1008, respectively. Subsequent repetitions of the programming and verification operation continue this pattern. Specifically, the third repetition may include a first programming voltage 1003, a second programming voltage 1010, and a verification voltage 1015. The fourth repetition may include a first programming voltage 1004; a second programming voltage 1011; and two verification voltages including a verification voltage 1016 followed by a smaller verification voltage 1015. The fifth repetition may include a first programming voltage 1005, a second programming voltage 1012, and verification voltages 1016 and 1015. The sixth repetition may include a first programming voltage 1006, a second programming voltage 1013, and verification voltages 1016 and 1015. The seventh iteration may include a first programming voltage 1007; a second programming voltage 1014; and three verification voltages: a first verification voltage 1017, followed by a smaller verification voltage 1016, and finally a still smaller verification voltage 1015. The seven iterations shown are intended to be a subset of the total number of iterations for programming and verification operations. For example, a word line may have sixteen memory cells, and additional iterations may be performed when an additional subset of memory cells is programmed.

[0119] Figure 14 This describes plots capturing various voltage levels applied to the word line (WLn) during programming and verification operations. Specifically, Figure 14 This describes the conditions applied to the selected SGD, unselected SGD, unselected control gate (CG), selected CG associated with WLn, disabled bit line (BL) that will not be programmed, and states S1 through 8 that will be programmed (e.g., Figure 12 The selection lines associated with memory cells A to H in the diagram, and the states S9 to 15 to be programmed (e.g., ... Figure 12 The voltage of the selected bit lines associated with the memory cells (I to O) in the memory. At time t0, the voltage level applied to the disabled bit lines and the selected bit lines corresponding to states S1 to 8 increases to the disabled voltage VDDSA to prevent those bit lines from being programmed at this time, while the voltage level applied to the selected bit lines corresponding to states S9 to 15 remains at or close to zero volts (0V).

[0120] While the voltage level of the selected bit line remains constant (or the voltage level of the selected bit line corresponding to states S9 to 15 increases slightly according to the anomaly discussed below), the voltage level of the selected control gate ramps up to the first programming voltage VpgmH, which arrives at approximately time t2 to begin programming the bit lines corresponding to states S9 to 15 without programming the bit lines corresponding to states S1 to 8.

[0121] At approximately time t3, the voltage level of the selected control gate begins to slope down from the first programming voltage VpgmH to a smaller second programming voltage VpgmL, while the voltage level of the bit lines corresponding to states S1 to 8 decreases from VDDSA to approximately zero volts (0V) to allow programming of the bit lines corresponding to states S1 to 8 to begin.

[0122] At approximately time t4, the voltage levels of the bit lines corresponding to states S1 to S8 are approximately zero volts (0V), and the voltage levels of both the unselected and selected control gates may temporarily rise and then fall to their respective Vpass and VpgmL levels to offset any decrease in these voltages, which may be caused by the decrease in the voltage applied to the bit lines to be programmed to states S1 to 8 starting at time t3.

[0123] At approximately time t5, the loop programming is complete, and the voltage level of the selected control gate is reduced. The loop verification portion can then be programmed and verified.

[0124] In specific programming and verification loops, such as those associated with the second phase of a two-phase programming cycle, the voltage levels of selected bit lines can be controlled to allow for more precise and controlled programming. At time t1 (between times t0 and t2), the voltage level of the bit lines corresponding to states S9 through 15 increases to a voltage level QPW greater than zero volts (0V) but less than VDDSA. Alternatively or additionally, the voltage level of the bit lines corresponding to states S1 through 8 decreases from VDDSA to QPW.

[0125] Figures 15A to 15F This description is used to program selected word lines (shown as WL). n The instance procedure 1100 of the memory cell set 1106. Combined with... Figures 15A to 15F One or more embodiments described may be implemented using a non-volatile memory device 1102 comprising control circuitry 1104 and a memory cell set 1106. For example, as will be shown, control circuitry 1104 may program the memory cell set by performing programming and verification operations, each iteration of which includes two programming voltages and one or more verification voltages. In some embodiments, the programming and verification operations may include a first portion and a second portion. For example, the first portion of the programming and verification operations may be a first stage of a multi-stage operation, and the second portion of the programming and verification operations may be a second stage of a multi-stage operation.

[0126] Control circuitry 1104 may include a state machine capable of communicating with each corresponding memory cell of a selected word line. In some embodiments, the selected word line may include sixteen four-level cells (QLCs). For ease of illustration, in Figures 15A to 15FThe examples shown depict only a portion of these memory cells (e.g., memory cells (MC)0, MC1, MC2, MC7, MC8, and MC15). Selected word lines may be connected to a set of bit lines comprising bit lines (BL)0, BL1, BL2, ..., and BL15. Figures 15A to 15F A subset of these bit lines (e.g., BL 0, BL 1, BL 2, BL 7, BL 8, and BL 15) is shown in the diagram. It should be understood that this is provided by way of example, and in practice, one or more features and / or techniques described herein can be implemented on any number of memory cells connected to any number of word lines and / or bit lines.

[0127] In some embodiments, the memory cell set 1106 may include memory cells corresponding to a high data state and memory cells corresponding to a low data state. In several parts of this document, the memory cells corresponding to the low data state may be referred to as a first subset of the memory cells in the set of memory cells in the selected word line. Alternatively, these memory cells may be referred to herein as low data state memory cells. Additionally, the memory cells corresponding to the high data state may be referred to as a second subset of the memory cells in the set of memory cells in the selected word line. Alternatively, these memory cells may be referred to herein as high data state memory cells. As will be described, a first programming voltage (VpgmH) can be used to program the memory cells corresponding to the high data state, and a second programming voltage (VpgmL) can be used to program the memory cells corresponding to the low data state.

[0128] like Figure 15A As shown by reference numeral 1108 in the accompanying drawings, control circuitry 1104 can disable programming of memory cells corresponding to one or more low data states. For example, control circuitry 1104 can provide a programmable disable voltage (VDDSA) to corresponding memory cells in a first subset of memory cells corresponding to low data states, thereby temporarily disabling programming of these memory cells.

[0129] The programmable disable voltage (VDDSA) can refer to the supply voltage, such as the supply voltage of a sense amplifier and / or a similar type of voltage. Based on the memory cell being configured to be programmed to one of the first eight data states (e.g., in a sequence of sixteen data states), the memory cell may correspond to a low data state. For example, each memory cell may have up to four bits. In the example shown, each memory cell may have four bits. Therefore, based on the memory cell being configured to be programmed to data state 0000, data state 0001, data state 0010, data state 0011, data state 0100, data state 0101, data state 0110, or data state 0111, the memory cell may correspond to a low data state.

[0130] In some embodiments, control circuitry 1104 may provide a programmable disable voltage (VDDSA) to bit lines associated with a first subset of memory cells corresponding to low data states. For example, control circuitry 1104 may provide a programmable disable voltage (VDDSA) to a bit line connected to each corresponding memory cell in the first subset of memory cells, thereby disabling programming of each memory cell.

[0131] In some embodiments, control circuitry 1104 may disable programming of memory cells corresponding to one or more other word lines (e.g., word lines other than the selected word line). For example, control circuitry 1104 may provide another programmable disable voltage (VPass) to one or more other word lines (e.g., adjacent word lines near the selected word line) such that programming of memory cells on one or more other word lines is prohibited by the programming voltage used to program memory cells on the selected word line. The other programmable disable voltage (VPass) may, for example, have a voltage value of eight volts, nine volts, ten volts, and / or similar voltage values.

[0132] like Figure 15B As shown by reference numeral 1110 in the accompanying drawings, control circuit 1104 may identify a programming voltage used to program a set of memory cells. For example, control circuit 1104 may identify a first programming voltage (VpgmH) for programming a second subset of memory cells corresponding to a high data state, and / or may identify a second programming voltage (VpgmL) for programming a first subset of memory cells corresponding to a low data state.

[0133] In some embodiments, the control circuit 1104 may receive programming command data (e.g., from a controller associated with a non-volatile memory device), and the programming command data may specify the data state to which each corresponding memory cell will be programmed. Alternatively, the control circuit may identify the data state by performing one or more read operations (sometimes referred to as sensing operations). For example, the control circuit may perform a read operation that includes providing a signal to a data latch of the memory cell. This signal may cause the data latch to provide a return signal to the control circuit that identifies the data state. The control circuit may perform a read operation on each corresponding memory cell connected to a selected word line.

[0134] In this way, the control circuit 1104 can identify multiple programming voltages used during each corresponding repetition of the programming and verification operation.

[0135] like Figure 15CAs shown by reference numeral 1112 in the accompanying drawings, control circuit 1104 can provide a first programming voltage (VpgmH) to a second subset of memory cells corresponding to high data states. For example, control circuit 1104 can provide the first programming voltage (VpgmH) to the control gate of each memory cell in the second subset of memory cells. The first programming voltage (VpgmH) can be provided as part of the first repetition of the programming portion of the programming and verification operation. Furthermore, because an inhibit voltage (VDDSA) is provided to the first subset of memory cells, the first subset of memory cells is charged to a voltage level that would inhibit programming of the first subset of memory cells with the first programming voltage.

[0136] By disabling the programming of a first subset of memory cells, the control circuit 1104 can begin programming a second subset of memory cells, while the first programming voltage does not affect memory cells corresponding to low data states.

[0137] like Figure 15D As shown by reference numeral 1114 in the accompanying drawings, control circuitry 1104 can discharge bit lines associated with a first subset of memory cells to enable programming of that first subset of memory cells. For example, control circuitry 1104 can discharge bit lines associated with the first subset of memory cells (which corresponds to a low data state) from a first voltage level corresponding to a programmable disable voltage (VDDSA) to a second voltage level of zero volts (or another voltage level that allows programming of each memory cell, such as a second voltage level corresponding to VBLC-QPW).

[0138] The control circuit 1104 can discharge the bit line by waiting for a threshold time period before performing the next part of the programming and verification operation. The threshold time period can be any time period sufficient to allow the bit line to discharge to the configured voltage level (e.g., zero volts).

[0139] In this way, the control circuit 1104 removes the programmable disable voltage (VDDSA), making it possible to program a first subset of the memory cells.

[0140] like Figure 15E As shown by reference numeral 1116 in the accompanying drawings, the control circuit 1104 can discharge the voltage level of the selected word line to a voltage level corresponding to the second programming voltage (VpgmL1). For example, the control circuit 1104 can discharge the voltage level of the selected word line from a first voltage level corresponding to the first programming voltage (VpgmH1) to a second voltage level corresponding to the second programming voltage (VpgmL1). The voltage level of the selected word line can be discharged as a first repetition of the programming portion of the programming and verification operation.

[0141] Since the disable programming voltage (VDDSA) has been discharged from the first subset of memory cells, the second programming voltage (VpgmL1) will be used to program each corresponding memory cell in the first subset of memory cells. Although the second programming voltage (VpgmL1) is also provided to the second subset of memory cells, this will not affect the programming of these memory cells because each of these memory cells is configured with a higher threshold voltage.

[0142] In some embodiments, to allow the voltage level of a selected word line to discharge, the control circuit 1104 may wait for a threshold time period before performing the verification portion of the programming and verification operation. This allows the voltage level of the selected word line to dissipate from the first programming voltage (VpgmH1) to the second programming voltage (VpgmL1). In some embodiments, the threshold time period used in conjunction with the selected word line may differ from the threshold time period used in conjunction with the bit lines associated with a first subset of memory cells corresponding to a low data state.

[0143] In some embodiments, the discharge of bit lines associated with a first subset of memory cells can reduce the strength of one or more programming voltages (Vpgm, VPass, etc.). In this case, control circuitry 1104 can be configured to spike the programming voltage to offset the reduction in one or more programming voltages caused by the bit line discharge. For example, as will be described, a boost programming voltage (e.g., dVpgm) can be applied during each successive iteration of the programming and verification operation. Control circuitry 1104 can be configured, for example, to spike the programming voltage by applying a compensating programming voltage (spiked Vpgm) for one of the subsequent iterations of the programming and verification operation (e.g., while other iterations will simply apply a voltage that has been increased by the boost programming voltage). In some embodiments, the compensating programming voltage can have a loop-dependent voltage level. For example, the voltage level applied as the compensating programming voltage can vary based on the extent to which the discharged bit line has affected the programming voltage (Vpgm) of the selected word line. Alternatively or additionally, control circuitry 1104 can cause a similar spike in the prohibition programming voltage (VPass) provided to other word lines near the selected word line.

[0144] In this way, the control circuit 1104 performs the first iteration of the programming part of the programming and verification operation.

[0145] like Figure 15F As shown by reference numeral 1118 in the accompanying drawings, control circuitry 1104 can perform a first iteration of the verification portion of the programming and verification operations. For example, control circuitry 1104 can perform a first iteration of the verification operation on first and second subsets of memory cells of selected word lines.

[0146] In some embodiments, the control circuit 1104 may use one or more bit line voltage biases to perform a verification operation. For example, the control circuit 1104 may apply a bit line voltage bias to one or more bit lines corresponding to a positive verification memory cell, apply an initial verification voltage (VvA) to a selected word line, and / or verify whether each corresponding memory cell has been programmed based on whether each memory cell has a threshold voltage Vth that satisfies (e.g., is higher than) the initial verification voltage (VvA).

[0147] Alternatively, the control circuit 1104 may use one or more sensing times to perform the verification operation. For example, the control circuit 1104 may perform the verification operation by using one or more sensing times to adjust the threshold voltage (Vth) of a memory cell in a selected word line. As a particular example, during the verification operation, one or more sensing times may be used to control the precharge voltage (PCV) affecting the threshold voltage of the corresponding memory cell. The sensing time may, for example, indicate the duration for which a capacitor can charge the sensing node of the memory cell corresponding to the bit line connected to the selected word line. To apply one or more sensing times, the control circuit 1104 may provide a signal to a voltage clamp to set the precharge voltage at a specific sensing node associated with the memory cell. The control gate voltage (VCG) of the memory cell may ramp up over time within the duration indicated by the given sensing time.

[0148] In some embodiments, control circuitry 1104 may verify all memory cells of a selected word line. In some embodiments, control circuitry 1104 may verify a subset of memory cells of a selected word line. For example, if an initial verification voltage (VvA) is being used for the first iteration of the verification operation, control circuitry 1104 may be configured to attempt to verify only a subset of memory cells corresponding to a low data state. This saves resources compared to attempting to verify all memory cells (e.g., because some memory cells will have data states corresponding to threshold voltages (Vth) that will not be satisfied (e.g., higher than) the initial verification voltage (VvA).

[0149] In this manner, control circuit 1104 verifies whether memory cells contained in first and second subsets of memory cells have been programmed. This saves resources (e.g., computing resources, power resources, memory resources, etc.) compared to verifying the first and second subsets of memory cells separately (e.g., during separate iterations of programming and verification operations). For example, by verifying the first and second subsets of memory cells separately, control circuit 1104 saves resources by reducing the total number of iterations of programming and verification operations required to program the memory cells of the selected word line.

[0150] In some embodiments, control circuitry 1104 may lock a verified memory cell to prevent further programming. For example, if control circuitry 1104 verifies that a memory cell has been programmed, it may lock the memory cell to prevent further programming, so that the memory cell remains unaffected while other memory cells are programmed during subsequent programming and verification iterations.

[0151] As indicated by reference numeral 1120, control circuitry 1104 can perform one or more additional iterations of programming and verification operations to program the memory cell of the selected word line. For example, control circuitry 1104 can perform one or more additional iterations of programming and verification operations by incrementally increasing the first and second programming voltages. As described above, the first and second programming voltages can be increased using a boost programming voltage (dVpgm) or a compensated programming voltage (spike-like Vpgm). Control circuitry 1104 can perform one or more additional programming and verification operations in a manner consistent with the initial iteration of the programming and verification operations described above. For example, control circuitry 1104 can increase the first programming voltage (VpgmH) and the second programming voltage (VpgmL) using the following equation:

[0152] VpgmH2 =1pgmH1 + dVpgm (1)

[0153] VpgmL2 =1pgmL1 + dVpgm (2)

[0154] In equations (1) and (2) above, VpgmH1 represents the first programming voltage during the first repetition of the programming operation, VpgmH2 represents the first programming voltage (VpgmH) during the second repetition of the programming operation, VpgmL1 represents the second programming voltage (VpgmL) during the first repetition of the programming operation, VpgmL2 represents the second programming voltage (VpgmL) during the second repetition of the programming operation, and dVpgm represents the boost voltage.

[0155] In some embodiments, the control circuitry 1104 may perform one or more additional iterations of the programming and verification operations until a stop condition is met. For example, a stop condition may be met based on all memory cells being verified, based on the final memory cell in the selected word line being verified, and / or based on the satisfaction of another type of configurable stop condition.

[0156] In this manner, control circuitry 1104 performs programming and verification operations to program and verify the set of memory cells for selected word lines. By performing the programming and verification operations as described herein, control circuitry 1104 reduces the total programming pulse count and the charging time for selected and unselected word lines (e.g., the time spent charging to Vpgm, VPass, etc.). This is a saving compared to programming and verification operations with higher programming pulse counts and / or higher charging times for selected and unselected word lines.

[0157] Figure 16 A flowchart illustrating a method 1600 for performing programming and verification operations to program a set of memory cells for a selected word line, according to the principles of this disclosure. For example, control circuitry (e.g., control circuitry 1104) may perform one or more repeated programming and verification operations to program a set of memory cells for a selected word line. The control circuitry may be a portion of, for example, a memory device 1102.

[0158] Step 1602 applies a first programming voltage to the selected word line. For example, control circuitry may apply the first programming voltage to the selected word line. The selected word line may include a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states. The first set of data states may, for example, be associated with one or more data states that are less than the data states associated with the second subset of memory cells.

[0159] In some embodiments, programming of a first subset of memory cells with a first programming voltage may be disabled. For example, before applying the first programming voltage, method 1600 may further include applying a disable programming voltage to bit lines corresponding to the first subset of memory cells, such that programming of the first subset of memory cells with the first programming voltage is disabled. Alternatively, the first programming voltage may be applied to a second subset of memory cells. As a particular example, in a QLC memory cell, a first set of data states may include data states 1 to 8, and a second set of data states may include data states 9 to 15. In this example, data states 1 to 8 may be programmed using a second programming voltage, and data states 9 to 15 may be programmed using a first programming voltage.

[0160] Step 1604 discharges the first voltage level of the selected word line to a second voltage level corresponding to the second programming voltage, such that the second programming voltage is applied to at least a first subset of the memory cells. For example, the control circuit may discharge the first voltage level of the selected word line corresponding to the first programming voltage to a second voltage level corresponding to the second programming voltage, such that the second programming voltage is applied to at least a first subset of the memory cells.

[0161] In some embodiments, method 1600 may further include discharging bit lines associated with a first subset of memory cells to zero volts. For example, control circuitry may discharge bit lines associated with the first subset of memory cells from a voltage value corresponding to a programmable disable voltage (e.g., VDDSA) to zero volts.

[0162] Step 1606 executes the verification portion of the programming and verification operation to verify whether a first subset and a second subset of memory cells have been programmed. For example, the control circuitry may perform the verification operation to verify whether the memory cells of the first and second subsets of memory cells have been programmed. In some embodiments, the control circuitry may use a set of verification voltages to verify whether one or more memory cells of a selected word line have been programmed. In some embodiments, the control circuitry may use a first set of verification voltages to verify whether a first subset of memory cells has been programmed, and may use a second set of verification voltages to verify whether a second subset of memory cells has been programmed.

[0163] In some embodiments, method 1600 may further include one or more steps for performing one or more additional repetitions of programming and verification operations. For example, control circuitry may perform one or more additional repetitions of programming and verification operations by incrementally increasing a first programming voltage and a second programming voltage during successive repetitions of programming and verification operations. In some embodiments, control circuitry may use a boost programming voltage to increase the first programming voltage and the second programming voltage. In some embodiments, control circuitry may use a compensation programming voltage to increase the first programming voltage and the second programming voltage. For example, by discharging a bit line associated with a first subset of memory cells to zero volts, control circuitry may reduce the voltage levels of the programming voltage (Vpgm) and / or the disable word line programming voltage (VPass). To offset or compensate for the reduction, control circuitry may apply a compensation programming voltage to a selected word line during one or more repetitions of programming and verification operations. This may produce spikes that can offset and / or compensate for the reduction in the voltage levels of the programming voltage (Vpgm) and / or the disable word line programming voltage (VPass). Control circuitry may perform these repetitions until a stop condition is met.

[0164] The foregoing detailed description of this disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to its precise forms. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of this disclosure and its practical application, thereby enabling others skilled in the art to best utilize this disclosure in various embodiments and with various modifications suitable for the particular intended use. The scope of this disclosure is intended to be defined by the appended claims.

[0165] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, the memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0166] Those skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art.

[0167] Various terms are used to refer to specific system components. Different companies may use different names to refer to components, and this document does not intend to distinguish between components with different names but the same function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including (but not limited to)...". Moreover, the term "coupled" means an indirect or direct connection. Thus, if a first device is coupled to a second device, the connection may be a direct connection or an indirect connection via other devices and connections.

[0168] Furthermore, when a layer or element is referred to as being "on" another layer or substrate, it may be directly on that other layer or substrate, or an intervening layer may be present. Additionally, it should be understood that when a layer is referred to as being "below" another layer, it may be directly below it, and one or more intervening layers may be present. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may be present.

[0169] As described herein, a controller includes individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), processors with control software, field-programmable gate arrays (FPGAs), or combinations thereof.

Claims

1. A non-volatile memory device comprising: a control circuit for performing program and verify operations to program an array of memory cells of the non-volatile memory, wherein the control circuit, in performing an iteration of the program and verify operations, is configured to: apply a first program voltage to a selected word line, wherein the selected word line includes a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states, wherein respective memory cells of the first subset of memory cells are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to the second subset of memory cells corresponding to the second set of data states; discharge a first voltage level of the selected word line corresponding to the first program voltage to a second voltage level corresponding to a second program voltage, such that the second program voltage is applied to at least the first subset of memory cells; and perform a verify portion of the program and verify operations to verify whether the first subset of memory cells and the second subset of memory cells have completed programming; and wherein the control circuit, prior to applying the first program voltage, is further configured to: apply an inhibit program voltage to bit lines corresponding to the first subset of memory cells, wherein each respective memory cell of the first subset of memory cells is inhibited from being programmed with the first program voltage based on the control circuit applying the inhibit program voltage to the bit lines corresponding to the first subset of memory cells.

2. The non-volatile memory device of claim 1, wherein the first program voltage has a voltage level that is higher than the second program voltage.

3. The non-volatile memory device of claim 1, wherein the control circuit is further configured to discharge bit lines associated with the first subset of memory cells to a third voltage level that is lower than the first voltage level and the second voltage level.

4. The non-volatile memory device of claim 1, wherein the control circuit is further configured to perform one or more additional iterations of the program and verify operations, and wherein the control circuit, in performing the one or more additional iterations of the program and verify operations, is configured to: incrementally increase the first program voltage and the second program voltage during successive iterations of the program and verify operations until a stop condition is satisfied.

5. The non-volatile memory device of claim 4, wherein the first program voltage and the second program voltage are increased using a compensation program voltage during at least one iteration of the program and verify operations, and wherein the first program voltage and the second program voltage are increased using a boost program voltage during one or more other iterations of the program and verify operations.

6. The non-volatile memory device of claim 1, wherein the control circuit, in performing the verify portion of the program and verify operations, is configured to: ​ verify, using a first set of verify voltages, whether one or more memory cells of the first subset of memory cells have completed programming, and verify, using a second set of verify voltages, whether one or more memory cells of the second subset of memory cells have completed programming.

7. A method of programming memory cells of a non-volatile memory, the method comprising: applying a first program voltage to a selected word line, wherein the selected word line includes a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states, wherein respective memory cells of the first subset of memory cells are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to the second subset of memory cells corresponding to the second set of data states; discharging a first voltage level of the selected word line corresponding to the first program voltage to a second voltage level corresponding to a second program voltage, such that the second program voltage is applied to at least the first subset of memory cells; and as part of an iteration of a program and verify operation, performing a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming; and wherein the method further comprises, prior to applying the first program voltage: applying an inhibit program voltage to bit lines corresponding to the first subset of memory cells, wherein the inhibit program voltage is applied to the bit lines corresponding to the first subset of memory cells based on a control circuit inhibiting each respective memory cell of the first subset of memory cells from being programmed with the first program voltage.

8. The method of claim 7, wherein the first program voltage has a voltage level that is higher than the second program voltage.

9. The method of claim 7, further comprising discharging bit lines associated with the first subset of memory cells to zero volts.

10. The method of claim 7, further comprising performing one or more additional iterations of the program and verify operation, and wherein performing the one or more additional iterations of the program and verify operation comprises: incrementally increasing the first program voltage and the second program voltage during successive iterations of the program and verify operation until a stop condition is satisfied.

11. The method of claim 10, wherein the first program voltage and the second program voltage are increased using a compensation program voltage during at least one iteration of the program and verify operation, and wherein the first program voltage and the second program voltage are increased using a boost program voltage during one or more other iterations of the program and verify operation.

12. The method of claim 7, wherein performing the verify operation comprises: verifying, using a set of verify voltages, whether one or more memory cells of the memory cells of the selected word line have completed programming.

13. A memory device, comprising: control circuitry for programming memory cells of a portion of an array of memory cells of a non-volatile memory, wherein the control circuitry is configured to: apply a first program voltage to a selected word line, wherein the selected word line includes a first subset of memory cells corresponding to a first set of data states and a second subset of memory cells corresponding to a second set of data states, wherein respective memory cells of the first subset of memory cells are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to the second subset of memory cells corresponding to the second set of data states; discharge a first voltage level of the selected word line corresponding to the first program voltage to a second voltage level corresponding to a second program voltage, such that the second program voltage is applied to at least the first subset of memory cells; and perform a verify portion of a program and verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming; and wherein the control circuitry, prior to applying the first program voltage, is further configured to: apply an inhibit program voltage to bit lines corresponding to the first subset of memory cells, wherein each respective memory cell of the first subset of memory cells is inhibited from being programmed with the first program voltage based on the control circuitry applying the inhibit program voltage to the bit lines corresponding to the first subset of memory cells.

14. The memory device of claim 13, wherein the first program voltage has a voltage level that is higher than the second program voltage.

15. The memory device of claim 13, wherein the control circuitry is further configured to discharge bit lines associated with the first subset of memory cells to zero volts.

16. The memory device of claim 13, wherein the control circuitry is further configured to perform one or more additional iterations of the program and verify operation, and wherein the control circuitry, when performing the one or more additional iterations of the program and verify operation, is configured to: incrementally increase the first program voltage and the second program voltage during successive iterations of the program and verify operation until a stop condition is satisfied.

17. The memory device of claim 16, wherein the first program voltage and the second program voltage are increased using a compensation program voltage during at least one iteration of the program and verify operation, and wherein the first program voltage and the second program voltage are increased using a boost program voltage during one or more other iterations of the program and verify operation.

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