Memory device for temporarily suspending and resuming operations

Abstract

The present disclosure relates to memory devices for temporarily suspending and resuming operations. A memory device can include an array of memory cells and a controller configured to access the array of memory cells. The controller can be further configured to receive a command to perform a program operation and, in response to the command to perform the program operation, begin execution of the program operation. The controller can be further configured to, while the program operation is being executed, receive a command to perform a read operation, in response to the command to perform the read operation, temporarily suspend the execution of the program operation, and perform the read operation with the execution of the program operation temporarily suspended.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 131,825, filed on December 30, 2020, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to memory, and more particularly, in one or more embodiments, to temporary suspension and recovery operations within a memory device. Background Technology

[0004] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. By programming the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, so named because of the logical form of its basic memory cell configuration. Typically, the memory cell array for NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., between a source select transistor and a drain select transistor). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known. Summary of the Invention

[0007] In one aspect, this disclosure relates to a memory device comprising: a memory cell array; and a controller configured to access the memory cell array, wherein the controller is further configured to: receive a command to perform a programming operation; initiate execution of the programming operation in response to the command to perform the programming operation; receive a command to perform a read operation while the programming operation is being performed; temporarily suspend the execution of the programming operation in response to the command to perform the read operation; and perform the read operation if the execution of the programming operation is temporarily suspended.

[0008] In another aspect, this disclosure relates to a memory device comprising: a memory cell array; and a controller configured to access the memory cell array, wherein the controller is further configured to: receive a command to perform an erase operation; in response to the command to perform the erase operation, initiate execution of the erase operation; while performing the erase operation, receive a command to perform a read operation; in response to the command to perform the read operation, temporarily suspend the execution of the erase operation; and, in the event that the execution of the erase operation is temporarily suspended, perform the read operation.

[0009] In another aspect, this disclosure relates to a memory device comprising: a memory cell array; and a controller configured to access the memory cell array, wherein the controller is further configured to: receive a command to perform a programming operation; in response to the command to perform the programming operation, begin execution of the programming operation; receive a command to temporarily suspend the execution of the programming operation; in response to the command to temporarily suspend the execution of the programming operation, temporarily suspend the execution of the programming operation; in the event that the execution of the programming operation is temporarily suspended, receive a command to perform a read operation; in response to the command to perform the read operation, perform the read operation; and in response to the completion of the execution of the read operation, resume the execution of the programming operation.

[0010] In another aspect, this disclosure relates to a memory device comprising: a memory cell array; and a controller configured to access the memory cell array, wherein the controller is further configured to: receive a command to perform an erase operation; in response to the command to perform the erase operation, begin execution of the erase operation; receive a command to temporarily suspend the execution of the erase operation; in response to the command to temporarily suspend the execution of the erase operation, temporarily suspend the execution of the erase operation; in the case that the execution of the erase operation is temporarily suspended, receive a command to perform a read operation; in response to the command to perform the read operation, perform the read operation; and in response to the completion of the execution of the read operation, resume the execution of the erase operation. Attached Figure Description

[0011] Figure 1 A simplified block diagram of a memory that communicates with a processor, which is part of an electronic system, according to an embodiment.

[0012] Figures 2A to 2C For reference only Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0013] Figures 3A to 3C A simplified timing diagram is provided to depict the temporary suspension and recovery operations in memory according to an embodiment.

[0014] Figures 4A to 4C A simplified timing diagram is provided to depict temporary pause and resume operations in memory according to other embodiments.

[0015] Figures 5A to 5C A simplified timing diagram is provided to depict temporary pause and resume operations in memory according to other embodiments.

[0016] Figures 6A to 6E A simplified timing diagram is provided to depict temporary pause and resume operations in memory according to other embodiments.

[0017] Figures 7A to 7D This is a flowchart of a method for operating a memory according to an embodiment.

[0018] Figures 8A to 8D This is a flowchart of a method for operating a memory according to another embodiment.

[0019] Figures 9A to 9D This is a flowchart of a method for operating a memory according to another embodiment.

[0020] Figures 10A to 10D This is a flowchart of a method for operating a memory according to another embodiment.

[0021] Figures 11A to 11G This is a flowchart of a method for operating a memory according to another embodiment.

[0022] Figures 12A to 12D This is a flowchart of a method for operating a memory according to another embodiment.

[0023] Figure 13 This is a flowchart of a method for operating a memory according to another embodiment. Detailed Implementation

[0024] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of description. In the drawings, like reference numerals describe generally similar components throughout several views. Other embodiments and structural, logical, and electrical changes may be utilized without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded as limiting.

[0025] For example, the term "semiconductor" as used herein may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0026] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0027] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will generally depend on the technology utilized in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0028] Figure 1This is a simplified block diagram illustrating a first device in the form of a memory (e.g., a memory device) 100 communicating with a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to an embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The processor 130, such as a controller external to the memory device 100, may be a memory controller or another external host device.

[0029] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (typically called a word line), while memory cells in a logical column are typically selectively connected to the same data line (typically called a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0030] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0031] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations on memory cell array 104 (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations). Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells of memory cell array 104, such as a reserved block of memory cells.

[0032] Control logic 116 can also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data, respectively. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; then, new data can be latched into cache register 118 from I / O control circuitry 112. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; then, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 can form a page buffer of memory device 100 (e.g., can form a portion thereof). The page buffer may further include sensing devices ( Figure 1 (Not shown) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0033] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0034] For example, commands can be received at the input / output (I / O) control circuitry 112 via I / O pins [7:0] of the I / O bus 134, and then written to the command register 124. Addresses can be received at the I / O control circuitry 112 via I / O pins [7:0] of the I / O bus 134, and then written to the address register 114. Data can be received at the I / O control circuitry 112 via I / O pins [7:0] for 8-bit devices or I / O pins [15:0] for 16-bit devices, and then written to the cache register 118. The data can then be written to the data register 120 for programming the memory cell array 104. In another embodiment, the cache register 118 can be omitted, and data can be written directly to the data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0035] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functions of the various block components described may not necessarily need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0036] Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0037] Figure 2A For reference only Figure 1 A schematic diagram of a portion (e.g., part of memory cell array 104) of a memory cell array 200A (e.g., a NAND memory array) of the described type. Memory array 200A includes access lines (e.g., word lines) 2020 to 202. N And data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed on a semiconductor, which may be conductively doped to have, for example, a p-type conductivity type to form a p-well, or to have an n-type conductivity type to form an n-well.

[0038] The memory array 200A can be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may further include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory, and instead are typically incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0039] Each NAND string 206 memory cell 208 can be connected in series at, for example, select gates 2100 to 210. M One of them (e.g., it may be a source-select transistor, commonly referred to as a select-gate source) has a select gate 210 (e.g., a field-effect transistor) and, for example, select gates 2120 to 212. M Between one of the select gates 212 (e.g., a field-effect transistor), which may be a drain-select transistor, commonly referred to as the select gate drain. Select gates 2100 to 210.M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0040] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0041] The drain of each select gate 212 can be connected to the data line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0042] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the data line 204, and the plane containing the data line 204 is substantially parallel to the plane containing the common source 216.

[0043] like Figure 2AAs shown, a typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or another structure configured to store charge) that can determine the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The control gate 236 of memory cell 208 is connected to (and in some cases forms) access line 202.

[0044] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given data line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may (but do not necessarily) contain all memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be designated as a single physical page for memory cell 208 (e.g., even-numbered memory cells), while those commonly connected to access line 202... N Furthermore, memory cells 208 selectively connected to odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., odd-numbered memory cells). Although data lines 2043 to 2045 are not explicitly depicted in... Figure 2A However, it is obvious from the diagram that the data line 204 of the memory cell array 200A can be from data line 2040 to data line 204. M Memory cells 208 that are commonly connected to a given access line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered as physical pages of the memory cells. A portion (in some embodiments, this may still be an entire row) of a physical page of a memory cell that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered as a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020 to 202. NAll memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, a reference to a memory cell page herein refers to the memory cell of the logical page of the memory cell.

[0045] Although combined with the NAND flash memory theory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or another data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0046] Figure 2B For reference only Figure 1 Another schematic diagram of a portion of a memory cell array 200B in a memory of the described type (e.g., as part of a memory cell array 104). Figure 2B Elements with the same number in the middle correspond to, for example, elements with the same number in the middle. Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, commonly referred to as a select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected by biasing the select line 2150 to 215. K Selective selection transistors 212, each located between NAND string 206 and data line 204, are selectively activated to connect to their respective data lines 204. Selection transistors 210 can be activated via bias selection line 214. Each access line 202 can connect to multiple rows of memory cells in memory array 200B. Rows of memory cells commonly connected to each other via specific access lines 202 are collectively referred to as a hierarchy.

[0047] A three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel transistors and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS often no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0048] Figure 2C For reference only Figure 1 Another schematic diagram of a portion of a memory cell array 200C in a memory of the described type (e.g., as part of memory cell array 104). Figure 2C Elements with the same number in the middle correspond to, for example, elements with the same number in the middle. Figure 2A The provided description. The memory cell array 200C may include, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C. Figure 2C The NAND string 206 is divided into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are commonly associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be respectively connected to memory cell blocks 2500 to 2500. L Access lines 202 and select lines 214 and 215 of any other memory cell block are not directly connected.

[0049] Data cable 2040 to 204 MIt can be connected (e.g., selectively connected) to buffer portion 240, which may be part of a data buffer for memory. Buffer portion 240 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer section 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the text).

[0050] Although Figure 2C Each memory cell block 250 is depicted as having only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are commonly associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to a buffer section 240 in response to its respective select line 215.

[0051] See below for reference Figures 3A to 3C In more detail, programming operations on selected memory cells within a memory cell array can be temporarily suspended for higher-priority read operations. Programming operations can resume once the higher-priority read operation is complete. Similarly, erasing operations on selected memory cells within a memory cell array can be temporarily suspended for higher-priority read or programming operations. Erasing operations can resume once the higher-priority read or programming operation is complete. To temporarily suspend and resume erase or programming operations, temporary suspension and resume commands can be transmitted from the host device to the memory device at an appropriate time when the memory device is ready to receive commands. Implementing these temporary suspension and resume operations utilizes the bus overhead between the host device and the memory device.

[0052] Figure 3A A simplified timing diagram is provided for temporarily suspending programming operations to perform read operations and resuming programming operations once the read operations are complete, according to an embodiment. The timing diagram includes a ready / busy control signal (R / B#) 302 (e.g., by...). Figure 1The timing diagram includes memory device 100 outputs, input / output (I / O) commands 304 (e.g., commands transferred from host device 130 to memory device 100 via I / O bus 134), and internal memory device (NAND) operations 306 (e.g., internal operations of memory device 100). For simplicity, data transfers between the memory device and the host device are not shown in the timing diagram, such as data transfers during read operations.

[0053] At time t0, in response to the previous programming command, the programming operation is in progress within the memory device. While the programming operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy executing the programming operation. At time t1, the host device transmits a programming temporary abort command to the memory device. At time t2, in response to the programming temporary abort command, the memory device begins the programming temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the programming operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0054] At time t3, programming operations are temporarily suspended, and the ready / busy control signal is released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) determines whether the programming operation is temporarily suspended. At time t4, in response to a success status check, the memory device transmits a read command to the memory device. At time t5, in response to the read command, the memory device begins execution of the read operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the read operation. In some embodiments, multiple read operations may be performed between time t5 and t6.

[0055] At time t6, the read operation completes, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check polls the memory device's status register to determine whether the programming operation can be resumed. At time t7, in response to a successful status check, the host device transmits a programming recovery command to the memory device. At time t8, in response to the programming recovery command, the memory device begins the programming recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming recovery operation. Between times t8 and t9, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the programming operation to resume. At time t9, the programming recovery operation completes, and the execution of the programming operation continues.

[0056] The read command at time t4 may include a read parameter page command, a read unique ID command, a set characteristic command, a get characteristic command, a read page multiplane command, an iWL read command, or another suitable read command. The read parameter page command can be used to read the capabilities of a memory device. The read unique ID command can be used to read a unique identifier programmed into a memory device. The set characteristic command and the get characteristic command can be used to modify the default power-on behavior of a memory device. The read page multiplane command can be used to copy data simultaneously from more than one memory plane to a specified cache register. The iWL read command can be used to read data from a memory cell connected to a middle word line (e.g., an access line located between the uppermost and lowermost access lines within a block of memory cells).

[0057] Figure 3B This is a simplified timing diagram illustrating the temporary suspension of an erase operation for a read operation and the resumption of the erase operation once the read operation is complete, according to an embodiment. The timing diagram includes a ready / busy control signal (R / B#) 302, an input / output (I / O) command 304, and an internal memory device (NAND) operation 306. For simplicity, data transfers between the memory device and the host device, such as data transfers during a read operation, are not shown in the timing diagram.

[0058] At time t0, in response to the previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits an erase temporary abort command to the memory device. At time t2, in response to the erase temporary abort command, the memory device begins the erase temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0059] At time t3, the erase operation has been temporarily suspended, and the ready / busy control signal has been released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation is temporarily suspended. At time t4, in response to a success status check, the memory device transmits a read command to the memory device. At time t5, in response to the read command, the memory device begins execution of the read operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the read operation. In some embodiments, multiple read operations may be performed between time t5 and t6.

[0060] At time t6, the read operation completes, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check polls the memory device's status register to determine if the erase operation can be resumed. At time t7, in response to a successful status check, the host device transmits an erase-recovery command to the memory device. At time t8, in response to the erase-recovery command, the memory device begins the erase-recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the erase-recovery operation. Between times t8 and t9, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the erase operation to resume. At time t9, the erase-recovery operation completes, and the execution of the erase operation continues.

[0061] The read command at time t4 can include a read parameter page command, a read unique ID command, a set characteristic command, a get characteristic command, a read page multiplane command, an iWL read command, a cache read command, a copy-back command, or another suitable read command. The cache read command can be used to output data from the cache register while simultaneously reading other data into the data register. The copy-back command can be used to transfer data within the memory plane from one page to another using the cache register.

[0062] Figure 3C This is a simplified timing diagram illustrating the temporary suspension of the erase operation for programming operations and the resumption of the erase operation once programming is complete, according to an embodiment. The timing diagram includes a ready / busy control signal (R / B#) 302, an input / output (I / O) command 304, and an internal memory device (NAND) operation 306. For simplicity, data transfers between the memory device and the host device, such as those during programming operations, are not shown in the timing diagram.

[0063] At time t0, in response to the previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits an erase temporary abort command to the memory device. At time t2, in response to the erase temporary abort command, the memory device begins the erase temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0064] At time t3, the erase operation has been temporarily suspended, and the ready / busy control signal has been released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) determines whether the erase operation is temporarily suspended. At time t4, in response to a success status check, the memory device transmits a programming command to the memory device. At time t5, in response to the programming command, the memory device begins execution of the programming operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming operation. In some embodiments, multiple programming operations may be performed between time t5 and t6.

[0065] At time t6, the programming operation is completed, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check polls the memory device's status register to determine if the erase operation can be resumed. At time t7, in response to a successful status check, the host device transmits an erase-recovery command to the memory device. At time t8, in response to the erase-recovery command, the memory device begins the erase-recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the erase-recovery operation. Between times t8 and t9, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the erase operation to resume. At time t9, the erase-recovery operation is completed, and the execution of the erase operation continues.

[0066] The programming command at time t4 may include an initial programming command, a final programming confirmation command, a multi-plane programming confirmation command, a cache programming confirmation command, or another suitable programming command. The initial programming command may be the first command transmitted from the host device to the memory device to indicate the start of a sequence of commands (e.g., commands, addresses, and data) for programming operations. The final programming confirmation command may be the last command transmitted from the host device to the memory device to indicate the end of the sequence of commands for programming operations. The multi-plane programming confirmation command may be an intermediate command within the command sequence for programming a specific plane of the memory device, following the address and data. The cache programming confirmation command may be used instead of the final programming confirmation command to enable the memory device to write data from the data register to the memory array while simultaneously loading additional data to be written to the memory array into the cache register.

[0067] This is attributed to internal memory device commands used to perform temporary pause and recovery operations, as referenced above. Figures 3A to 3CThe time required to perform the described temporary suspension and recovery operations can be unpredictable. Additionally, the host device may request a status check to determine whether the operation has been temporarily suspended or is recoverable. Due to internal memory device commands and status checks, the latency of performing temporary suspension and recovery operations is unpredictable (e.g., Figures 3A to 3C (Time delay between times t1 and t4 and between times t6 and t9).

[0068] Figure 4A A simplified timing diagram is provided according to another embodiment, illustrating the temporary suspension of programming operations for a read operation and the resumption of programming operations once the read operation is complete. The timing diagram includes a ready / busy control signal (R / B#) 402 (e.g., by...). Figure 1 The timing diagram includes memory device 100 outputs, input / output (I / O) commands 404 (e.g., commands transferred from host device 130 to memory device 100 via I / O bus 134), and internal memory device (NAND) operations 406 (e.g., internal operations of memory device 100). For simplicity, data transfers between the memory device and the host device are not shown in the timing diagram, such as data transfers during read operations.

[0069] At time t0, in response to a previous programming command, the programming operation is in progress within the memory device. While the programming operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the programming operation. At time t1, the host device transmits a read command to the memory device. At time t2, in response to the read command, the memory device begins a temporary programming halt operation (e.g., in the absence of a temporary halt command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the programming operation is temporarily halted, and the memory device is prepared to perform a read operation.

[0070] At time t3, the programming operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the programming operation, the memory device begins the execution of a read operation. At time t4, the read operation completes, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1(122) Determines whether the programming operation can be resumed. At time t5, in response to a success status check, the host device transmits a programming recovery command to the memory device. At time t6, in response to the programming recovery command, the memory device initiates the programming recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming recovery operation. Between times t6 and t7, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the programming operation to resume. At time t7, the programming recovery operation is complete, and the execution of the programming operation continues.

[0071] exist Figure 4A In this embodiment, a temporary pause command is not used. Specifically, in response to a read command, the memory device automatically temporarily suspends the execution of the programming operation and begins the execution of the read operation. Furthermore, the host device does not perform a status check (e.g., ...) before starting the read operation. Figure 3A The status check at time t3 is transmitted to the memory device. Therefore, Figure 4A The programming temporary suspension operation and subsequent read operation in the embodiment can be compared to Figure 3A The implementation in this example has less latency.

[0072] Figure 4B This is a simplified timing diagram illustrating the temporary suspension of programming operations for a read operation and the resumption of programming operations once the read operation is complete, according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 402, an input / output (I / O) command 404, and an internal memory device (NAND) operation 406. For simplicity, data transfers between the memory device and the host device, such as data transfers during a read operation, are not shown in the timing diagram.

[0073] At time t0, in response to the previous programming command, the programming operation is in progress within the memory device. While the programming operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy executing the programming operation. At time t1, the host device transmits a programming temporary abort command to the memory device. At time t2, in response to the programming temporary abort command, the memory device begins the programming temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the programming operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0074] At time t3, programming operations are temporarily suspended, and the ready / busy control signal is released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1(122) Determines whether the programming operation is temporarily suspended. At time t4, in response to the success status check, the memory device transmits a read command to the memory device. At time t5, in response to the read command, the memory device begins execution of the read operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the read operation.

[0075] At time t6, the read operation is completed, and the memory device automatically begins the programming recovery operation (e.g., in the absence of a programming recovery command). Between times t6 and t7, the memory device prepares the relevant portions of the memory device (e.g., the memory array) for the programming operation to resume. At time t7, the programming recovery operation is completed, and the execution of the programming operation continues.

[0076] exist Figure 4B In this embodiment, no recovery command is used. Specifically, in response to the completion of the read operation, the memory device automatically resumes the execution of the programming operation. Furthermore, the host device does not perform a status check (e.g., ...) before resuming the execution of the programming operation. Figure 3A The status check at time t6 is transmitted to the memory device. Therefore, Figure 4B The programmed recovery operation in the embodiments can be compared to Figure 3A The implementation in this example has less latency.

[0077] Figure 4C This is a simplified timing diagram illustrating the temporary suspension of programming operations for a read operation and the resumption of programming operations once the read operation is complete, according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 402, an input / output (I / O) command 404, and an internal memory device (NAND) operation 406. For simplicity, data transfers between the memory device and the host device, such as data transfers during a read operation, are not shown in the timing diagram.

[0078] At time t0, in response to a previous programming command, the programming operation is in progress within the memory device. While the programming operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the programming operation. At time t1, the host device transmits a read command to the memory device. At time t2, in response to the read command, the memory device begins a temporary programming halt operation (e.g., in the absence of a temporary halt command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the programming operation is temporarily halted, and the memory device is prepared to perform a read operation.

[0079] At time t3, the programming operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the programming operation, the memory device begins the execution of a read operation. At time t4, the read operation completes, and the memory device automatically begins a programming recovery operation (e.g., in the absence of a programming recovery command). Between times t4 and t5, the memory device prepares the relevant portions of the memory device (e.g., the memory array) for the programming operation to resume. At time t5, the programming recovery operation completes, and the execution of the programming operation continues.

[0080] exist Figure 4C In this embodiment, neither a pause command nor a resume command is used. Specifically, in response to a read command, the memory device automatically pauses the execution of the programming operation and begins the execution of the read operation. In response to the completion of the read operation, the memory device automatically resumes the execution of the programming operation. Furthermore, the host device does not perform a status check (e.g., ...) before temporarily pausing or resuming the execution of the programming operation. Figure 3A The status check at time t3 or t6 is transmitted to the memory device. Therefore, with Figure 3A Compared to the previous embodiment, the programming temporary suspension and resumption operation can be performed in [the following context]. Figure 4C In some embodiments, it is implemented with less latency.

[0081] Figure 5A A simplified timing diagram is provided according to another embodiment, illustrating the temporary suspension of an erase operation for a read operation and the resumption of the erase operation once the read operation is complete. The timing diagram includes a ready / busy control signal (R / B#) 502 (e.g., by...). Figure 1 The timing diagram includes memory device 100 outputs, input / output (I / O) commands 504 (e.g., commands transferred from host device 130 to memory device 100 via I / O bus 134), and internal memory device (NAND) operations 506 (e.g., internal operations of memory device 100). For simplicity, data transfers between the memory device and the host device are not shown in the timing diagram, such as data transfers during read operations.

[0082] At time t0, in response to a previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a read command to the memory device. At time t2, in response to the read command, the memory device begins a temporary pause operation on the erase process (e.g., in the absence of a temporary pause command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily paused, and the memory device is prepared to perform a read operation.

[0083] At time t3, the erase operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the erase operation, the memory device begins the execution of the read operation. At time t4, the read operation is completed, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation can be recovered. At time t5, in response to a success status check, the host device transmits an erase-recovery command to the memory device. At time t6, in response to the erase-recovery command, the memory device begins the erase-recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the erase-recovery operation. Between times t6 and t7, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the erase operation to be recovered. At time t7, the erase-recovery operation is complete, and the execution of the erase operation continues.

[0084] exist Figure 5A In this embodiment, a temporary pause command is not used. Specifically, in response to a read command, the memory device automatically temporarily suspends the erase operation and begins the read operation. Furthermore, the host device does not perform a status check (e.g., ...) before beginning the read operation. Figure 3B The status check at time t3 is transmitted to the memory device. Therefore, Figure 5A The erase temporary suspension operation and subsequent read operation in the embodiment can be compared to Figure 3B The implementation in this example has less latency.

[0085] Figure 5B This is a simplified timing diagram illustrating the temporary suspension of an erase operation for a read operation and the resumption of the erase operation once the read operation is complete, according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 502, an input / output (I / O) command 504, and an internal memory device (NAND) operation 506. For simplicity, data transfers between the memory device and the host device, such as data transfers during a read operation, are not shown in the timing diagram.

[0086] At time t0, in response to the previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits an erase temporary abort command to the memory device. At time t2, in response to the erase temporary abort command, the memory device begins the erase temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0087] At time t3, programming operations are temporarily suspended, and the ready / busy control signal is released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation is temporarily suspended. At time t4, in response to the success status check, the memory device transmits a read command to the memory device. At time t5, in response to the read command, the memory device begins execution of the read operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the read operation.

[0088] At time t6, the read operation is completed, and the memory device automatically begins the erase recovery operation (e.g., if no erase recovery command is received). Between times t6 and t7, the memory device prepares the relevant portions of the memory device (e.g., the memory array) for the erase operation. At time t7, the erase recovery operation is completed, and the execution of the erase operation continues.

[0089] exist Figure 5B In this embodiment, no recovery command is used. Specifically, in response to the completion of the read operation, the memory device automatically resumes the execution of the erase operation. Furthermore, the host device does not perform a status check (e.g., ...) before resuming the execution of the erase operation. Figure 3B The status check at time t6 is transmitted to the memory device. Therefore, Figure 5B The erase and restore operation in the embodiments can be compared to Figure 3B The implementation in this example has less latency.

[0090] Figure 5CThis is a simplified timing diagram illustrating the temporary suspension of an erase operation for a read operation and the resumption of the erase operation once the read operation is complete, according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 502, an input / output (I / O) command 504, and an internal memory device (NAND) operation 506. For simplicity, data transfers between the memory device and the host device, such as data transfers during a read operation, are not shown in the timing diagram.

[0091] At time t0, in response to a previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a read command to the memory device. At time t2, in response to the read command, the memory device begins a temporary pause operation on the erase process (e.g., in the absence of a temporary pause command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily paused, and the memory device is prepared to perform a read operation.

[0092] At time t3, the erase operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the erase operation, the memory device begins the execution of the read operation. At time t4, the read operation completes, and the memory device automatically begins the erase recovery operation (e.g., in the absence of an erase recovery command). Between times t4 and t5, the memory device prepares relevant portions of the memory device (e.g., the memory array) to recover from the erase operation. At time t5, the erase recovery operation completes, and the execution of the erase operation continues.

[0093] exist Figure 5C In this embodiment, neither a pause command nor a resume command is used. Specifically, in response to a read command, the memory device automatically pauses the erase operation and begins the read operation. In response to the completion of the read operation, the memory device automatically resumes the erase operation. Furthermore, the host device does not perform a status check (e.g., ...) before temporarily pausing or resuming the erase operation. Figure 3B The status check at time t3 or t6 is transmitted to the memory device. Therefore, with Figure 3B Compared to the previous embodiment, the erase temporary suspension and restore operations can be performed in [the following context]. Figure 5C In some embodiments, it is implemented with less latency.

[0094] Figure 6AA simplified timing diagram is provided for temporarily suspending the erase operation to perform a programming operation and resuming the erase operation once the programming operation is complete, according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 602 (e.g., by...). Figure 1 The timing diagram includes memory device 100 outputs, input / output (I / O) commands 604 (e.g., commands transferred from host device 130 to memory device 100 via I / O bus 134), and internal memory device (NAND) operations 606 (e.g., internal operations of memory device 100). For simplicity, data transfers between the memory device and the host device are not shown in the timing diagram, such as data transfers during programming operations.

[0095] At time t0, in response to a previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a programming command to the memory device. At time t2, in response to the programming command, the memory device begins a temporary pause operation on the erase process (e.g., in the absence of a temporary pause command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily paused, and the memory device is prepared to perform a programming operation.

[0096] At time t3, the erase operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the erase operation, the memory device begins the programming operation. At time t4, the programming operation is completed, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation can be recovered. At time t5, in response to a success status check, the host device transmits an erase-recovery command to the memory device. At time t6, in response to the erase-recovery command, the memory device begins the erase-recovery operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the erase-recovery operation. Between times t6 and t7, the memory device prepares the relevant portion of the memory device (e.g., the memory array) for the erase operation to be recovered. At time t7, the erase-recovery operation is complete, and the execution of the erase operation continues.

[0097] exist Figure 6AIn this embodiment, a temporary pause command is not used. Specifically, in response to a programming command, the memory device automatically temporarily pauses the erase operation and begins the programming operation. Furthermore, the host device does not perform a status check (e.g., ...) before beginning the programming operation. Figure 3C The status check at time t3 is transmitted to the memory device. Therefore, Figure 6A The erase temporary suspension operation and subsequent programming operation in the embodiment can be compared to Figure 3C The implementation in this example has less latency.

[0098] Figure 6B A simplified timing diagram is provided according to another embodiment, illustrating the temporary suspension of the erase operation for a programming operation and the resumption of the erase operation once the programming operation is complete. The timing diagram includes a ready / busy control signal (R / B#) 602, an input / output (I / O) command 604, and an internal memory device (NAND) operation 606. For simplicity, data transfers between the memory device and the host device, such as those during the programming operation, are not shown in the timing diagram.

[0099] At time t0, in response to the previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits an erase temporary abort command to the memory device. At time t2, in response to the erase temporary abort command, the memory device begins the erase temporary abort operation. Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily suspended, and the memory device is prepared to receive other commands.

[0100] At time t3, programming operations are temporarily suspended, and the ready / busy control signal is released to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation is temporarily suspended. At time t4, in response to the success status check, the memory device transmits a programming command to the memory device. At time t5, in response to the programming command, the memory device begins execution of the programming operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming operation.

[0101] At time t6, the programming operation is completed, and the memory device automatically begins the erase / restore operation (e.g., in the absence of an erase / restore command). Between times t6 and t7, the memory device prepares the relevant portions of the memory device (e.g., the memory array) for the erase operation. At time t7, the erase / restore operation is completed, and the execution of the erase operation continues.

[0102] exist Figure 6B In this embodiment, no recovery command is used. Specifically, in response to the completion of the programming operation, the memory device automatically resumes the execution of the erase operation. Furthermore, the host device does not perform a status check (e.g., ...) before resuming the execution of the erase operation. Figure 3C The status check at time t6 is transmitted to the memory device. Therefore, Figure 6B The erase and restore operation in the embodiments can be compared to Figure 3C The implementation in this example has less latency.

[0103] Figure 6C A simplified timing diagram is provided according to another embodiment, illustrating the temporary suspension of the erase operation for a programming operation and the resumption of the erase operation once the programming operation is complete. The timing diagram includes a ready / busy control signal (R / B#) 602, an input / output (I / O) command 604, and an internal memory device (NAND) operation 606. For simplicity, data transfers between the memory device and the host device, such as those during the programming operation, are not shown in the timing diagram.

[0104] At time t0, in response to a previous erase command, the erase operation is in progress within the memory device. While the erase operation is in progress, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a programming command to the memory device. At time t2, in response to the programming command, the memory device begins a temporary pause operation on the erase process (e.g., in the absence of a temporary pause command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the erase operation is temporarily paused, and the memory device is prepared to perform a programming operation.

[0105] At time t3, the erase operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the erase operation, the memory device begins the execution of the programming operation. At time t4, the programming operation is completed, and the memory device automatically begins the erase recovery operation (e.g., in the absence of an erase recovery command). Between times t4 and t5, the memory device prepares relevant portions of the memory device (e.g., the memory array) to recover from the erase operation. At time t5, the erase recovery operation is completed, and the execution of the erase operation continues.

[0106] exist Figure 6C In this embodiment, neither a pause command nor a resume command is used. Specifically, in response to a programming command, the memory device automatically pauses the erase operation and begins the programming operation. In response to the completion of the programming operation, the memory device automatically resumes the erase operation. Furthermore, the host device does not perform a status check (e.g., ...) before temporarily pausing or resuming the erase operation. Figure 3C The status check at time t3 or t6 is transmitted to the memory device. Therefore, with Figure 3C Compared to the previous embodiment, the erase temporary suspension and restore operations can be performed in [the following context]. Figure 6C In some embodiments, it is implemented with less latency.

[0107] Figure 6D This is a simplified timing diagram for temporarily suspending an erase operation to perform a programming operation according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 602, an input / output (I / O) command 604, and an internal memory device (NAND) operation 606. At time t0, in response to a previous erase command, the execution of an erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a sequence of programming commands with data input for programming operations (e.g., addresses and / or data for programming) to the memory device. At time t2, in response to the sequence of programming commands with data input, the memory device begins a temporary pause operation (e.g., in the absence of a temporary pause command). The memory device may begin a temporary pause operation in response to receiving an initial programming command, address, data, or another portion of the command sequence. Between times t2 and t3, the memory device may wait until the execution breakpoint is reached, at which point the erase operation is temporarily suspended and the memory device is prepared to perform the programming operation.

[0108] At time t3, the erase operation is temporarily suspended and the ready / busy control signal remains pulled down. At time t3, in response to the temporary suspension of the erase operation, the memory device begins the execution of a programming operation (e.g., a programming setup operation based on data input). At time t4, the programming setup operation is completed, and the memory device releases the ready / busy control signal to indicate that the memory device is ready to receive other commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1(122) Determines whether the programming setup operation is complete. At time t5, in response to the success status check, the host device transmits another programming command to the memory device. At time t6, in response to the programming command, the memory device continues the execution of the programming operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming operation. Once the programming operation is complete, the erase operation can proceed as follows: Figure 6A The description states that the system recovers or restores in response to the erase / restore command. Figure 6B It will automatically recover as described in the text.

[0109] Figure 6E This is a simplified timing diagram for temporarily suspending an erase operation to perform a programming operation according to another embodiment. The timing diagram includes a ready / busy control signal (R / B#) 602, an input / output (I / O) command 604, and an internal memory device (NAND) operation 606. At time t0, in response to a previous erase command, the execution of an erase operation is in progress within the memory device. While the erase operation is in progress, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation. At time t1, the host device transmits a programming command (e.g., an initial programming command) with or without data to the memory device. At time t2, in response to the programming command, the memory device begins a temporary pause operation (e.g., in the case of not receiving a temporary pause command). Between times t2 and t3, the memory device may wait until an execution breakpoint is reached, at which point the execution of the erase operation is temporarily suspended, and the memory device is prepared to perform a programming operation.

[0110] At time t3, programming operations are temporarily suspended, and the ready / busy control signal is released to indicate that the memory device is ready to receive other programming commands. In response to the release of the ready / busy control signal, the host device requests a status check of the memory device. The status check may poll the memory device's status register (e.g., ...). Figure 1 (122) Determines whether the erase operation is temporarily suspended. At time t4, in response to a success status check, the memory device transmits another programming command (or the data of the programming command at time t1) to the memory device. At time t5, in response to the programming command (or data), the memory device begins execution of the programming operation and pulls down the ready / busy control signal to indicate that the memory device is busy performing the programming operation. Once the programming operation is complete, the erase operation can proceed as planned. Figure 6A The description states that the system recovers or restores in response to the erase / restore command. Figure 6B It will automatically recover as described in the text.

[0111] Figures 7A to 7D This is a flowchart of a method 700 for operating a memory according to an embodiment. Method 700 may at least partially correspond to Figures 4A to 4CFor example, Figures 7A to 7D This can represent a method for temporarily suspending programming operations to perform read operations and resuming programming operations once the read operations are complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0112] Method 700 can be implemented within a memory device (e.g., 100) that includes a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 7A As described at 702, the controller can receive commands for performing programming operations. At 704, the controller can initiate the execution of programming operations in response to the programming operation command. At 706, the controller can receive commands for performing read operations while performing programming operations. Commands for performing read operations may include commands to read parameter pages, read unique IDs, set characteristics, obtain characteristics, read page multiplanes, iWL read commands, or other suitable read commands.

[0113] At 708, the controller may temporarily suspend the execution of the programming operation in response to a command to perform a read operation. In one instance, the controller may temporarily suspend the execution of the programming operation without receiving a temporary suspension command. At 710, the controller may perform the read operation while the execution of the programming operation is temporarily suspended. In one instance, the controller may further resume the execution of the programming operation without receiving a resume command in response to the completion of the read operation. In another instance, the controller may further resume the execution of the programming operation in response to receiving a resume command in response to the completion of the read operation.

[0114] like Figure 7B As explained at 712, the controller may further respond to a command to perform a read operation by accepting the command and continuing the execution of the programming operation until an execution breakpoint is reached. At 714, the controller may further respond to reaching an execution breakpoint by temporarily suspending the execution of the programming operation.

[0115] like Figure 7C As described at 716, the controller may further receive multiple commands for performing corresponding multiple read operations during the execution of programming operations. At 718, the controller may perform multiple read operations if the execution of programming operations is temporarily suspended. In this embodiment, the memory device may further include a command register (e.g., Figure 1(124) The multiple commands are latched in the order in which they are received to perform the corresponding multiple read operations. Therefore, the controller can further execute the multiple read operations in the order in which they are received.

[0116] like Figure 7D As described at 720, the controller can further reduce the ready / busy control signal in response to performing a programming operation to indicate that the memory device is busy performing a programming operation. At 722, the controller can further receive a command to perform a read operation when the ready / busy control signal is reduced. At 724, the controller can further temporarily suspend the execution of the programming operation in response to a command to perform a read operation, while maintaining the ready / busy control signal reduced. At 726, the controller can further perform a read operation when the execution of the programming operation is temporarily suspended, while maintaining the ready / busy control signal reduced.

[0117] Figures 8A to 8D This is a flowchart of a method 800 for operating a memory according to another embodiment. Method 800 may at least partially correspond to Figures 5A to 5C For example, Figures 8A to 8D This can represent a method for temporarily suspending the erase operation to perform a read operation and resuming the erase operation once the read operation is complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0118] Method 800 may be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 8A As described at 802, the controller can receive a command to perform an erase operation. At 804, the controller can initiate the execution of the erase operation in response to the erase operation command. At 806, the controller can receive a command to perform a read operation while performing the erase operation. The read operation command may include a read parameter page command, a read unique ID command, a set characteristic command, a get characteristic command, a read page multiplane command, an iWL read command, a program multiplane command, a cache read command, a copy-back command, or another suitable read command.

[0119] At point 808, the controller may temporarily suspend the execution of the erase operation in response to a command to perform a read operation. In one instance, the controller may temporarily suspend the execution of the erase operation without receiving a temporary suspend command. At point 810, the controller may perform a read operation while the execution of the erase operation is temporarily suspended. In one instance, the controller may further resume the execution of the erase operation without receiving a restore command in response to the completion of the read operation. In another instance, the controller may further resume the execution of the erase operation in response to receiving a restore command in response to the completion of the read operation.

[0120] like Figure 8B As explained at 812, the controller may further respond to a command to perform a read operation by accepting the command and continuing the execution of the erase operation until an execution breakpoint is reached. At 816, the controller may further respond to reaching an execution breakpoint by temporarily suspending the execution of the erase operation.

[0121] like Figure 8C As described at 818, the controller may further receive multiple commands for performing corresponding multiple read operations during the execution of the erase operation. At 820, the controller may perform multiple read operations if the execution of the erase operation is temporarily suspended. In this embodiment, the memory device may further include a command register (e.g., Figure 1 (124) latches the multiple commands in the order in which they are received to perform the corresponding multiple read operations. Therefore, the controller can further execute the multiple read operations in the order in which they are received.

[0122] like Figure 8D As described at 822, the controller may further reduce the ready / busy control signal in response to performing an erase operation to indicate that the memory device is busy performing an erase operation. At 824, the controller may further receive a command to perform a read operation while the ready / busy control signal is reduced. At 826, the controller may further temporarily suspend the execution of the erase operation in response to a command to perform a read operation, while maintaining the ready / busy control signal reduced. At 828, the controller may further perform a read operation while the execution of the erase operation is temporarily suspended, while maintaining the ready / busy control signal reduced.

[0123] Figures 9A to 9D This is a flowchart of a method 900 for operating a memory according to another embodiment. Method 900 may at least partially correspond to Figures 4A to 4C For example, Figures 9A to 9D This can represent a method for temporarily suspending programming operations to perform read operations and resuming programming operations once the read operations are complete. The method may be, for example, stored in... Figure 1The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0124] Method 900 can be implemented within a memory device (e.g., 100) that includes a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 9A As described at 902, the controller can receive a command to perform a programming operation. At 904, the controller can begin the execution of the programming operation in response to the command. At 906, the controller can receive a command to temporarily suspend the execution of the programming operation. At 908, the controller can temporarily suspend the execution of the programming operation in response to the command. At 910, the controller can receive a command to perform a read operation while the execution of the programming operation is temporarily suspended. The command to perform a read operation can include a command to read a parameter page, a command to read a unique ID, a command to set a feature, a command to get a feature, a command to read a page multiplane, an iWL read command, or another suitable read command. At 912, the controller can perform a read operation in response to the command to perform a read operation. At 914, the controller can resume the execution of the programming operation in response to the completion of the read operation. The controller can resume the execution of the programming operation without receiving a resume command.

[0125] like Figure 9B As explained at 916, the controller can further respond to a command to temporarily suspend the execution of the programming operation and continue the execution of the programming operation until an execution breakpoint is reached. At 918, the controller can further respond to reaching an execution breakpoint and temporarily suspend the execution of the programming operation.

[0126] like Figure 9C As described at 920, the controller may further receive multiple commands to perform corresponding multiple read operations in the event that the execution of the programming operation is temporarily suspended. At 922, the controller may further execute multiple read operations in response to the multiple commands to perform the corresponding multiple read operations. In this embodiment, the memory device may further include a command register (e.g., Figure 1 (124) The multiple commands are latched in the order in which they are received to perform the corresponding multiple read operations. Therefore, the controller can further execute the multiple read operations in the order in which they are received.

[0127] like Figure 9DAs described at 924, the controller may further pull down the ready / busy control signal in response to performing a programming operation to indicate that the memory device is busy performing a programming operation. At 926, the controller may further receive a command to temporarily suspend the execution of the programming operation when the ready / busy control signal is pulled down. At 928, the controller may further release the ready / busy control signal in response to temporarily suspending the execution of the programming operation to indicate that the memory device is ready. At 930, the controller may further receive a command to perform a read operation when the ready / busy control signal is released. At 932, the controller may further pull down the ready / busy control signal in response to resuming the execution of the programming operation.

[0128] Figures 10A to 10D This is a flowchart of a method 1000 for operating a memory according to another embodiment. Method 1000 may at least partially correspond to Figures 5A to 5C For example, Figures 10A to 10D This can represent a method for temporarily suspending the erase operation to perform a read operation and resuming the erase operation once the read operation is complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0129] Method 1000 can be implemented within a memory device (e.g., 100) that includes a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 10A As described at 1002, the controller can receive a command to perform an erase operation. At 1004, the controller can begin the execution of the erase operation in response to the erase operation command. At 1006, the controller can receive a command to temporarily suspend the execution of the erase operation. At 1008, the controller can temporarily suspend the execution of the erase operation in response to the command to temporarily suspend the execution of the erase operation. At 1010, the controller can receive a command to perform a read operation while the execution of the erase operation is temporarily suspended. The command to perform a read operation can include a command to read a parameter page, a command to read a unique ID, a command to set characteristics, a command to get characteristics, a command to read a page multiplane, an iWL read command, a cache read command, a copy-back command, or another suitable read command. At 1012, the controller can perform a read operation in response to the read operation command. At 1014, the controller can resume the execution of the erase operation in response to the completion of the read operation. The controller can resume the execution of the erase operation even if a resume command is not received.

[0130] like Figure 10BAs explained at 1016, the controller can further respond to a command to temporarily suspend the execution of the erase operation and continue the execution of the erase operation until an execution breakpoint is reached. At 1018, the controller can further respond to reaching an execution breakpoint and temporarily suspend the execution of the erase operation.

[0131] like Figure 10C As described at 1020, the controller may further receive multiple commands to perform corresponding multiple read operations in the event that the execution of the erase operation is temporarily suspended. At 1022, the controller may further execute multiple read operations in response to the multiple commands to perform the corresponding multiple read operations. In this embodiment, the memory device may further include a command register (e.g., Figure 1 (124) The multiple commands are latched in the order in which they are received to perform the corresponding multiple read operations. Therefore, the controller can further execute the multiple read operations in the order in which they are received.

[0132] like Figure 10D As explained at 1024, the controller may further pull down the ready / busy control signal in response to performing an erase operation to indicate that the memory device is busy performing an erase operation. At 1026, the controller may further receive a command to temporarily suspend the execution of the erase operation when the ready / busy control signal is pulled down. At 1028, the controller may further release the ready / busy control signal in response to temporarily suspending the execution of the erase operation to indicate that the memory device is ready. At 1030, the controller may further receive a command to perform a read operation when the ready / busy control signal is released. At 1032, the controller may further pull down the ready / busy control signal in response to resuming the execution of the erase operation.

[0133] Figures 11A to 11G This is a flowchart of a method 1100 for operating a memory according to another embodiment. Method 1100 may at least partially correspond to Figures 6A to 6E For example, Figures 11A to 11D This can represent a method for temporarily suspending the erase operation to perform a programming operation and resuming the erase operation once the programming operation is complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0134] Method 1100 may be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 11AAs described at 1102, the controller can receive a command to perform an erase operation. At 1104, the controller can initiate the execution of the erase operation in response to the erase operation command. At 1106, the controller can receive a command to perform a programming operation while performing the erase operation. The programming operation command may include an initial programming command, a final programming confirmation command, a multi-plane programming confirmation command, a cache programming confirmation command, or another suitable programming command.

[0135] At 1108, the controller may temporarily suspend the erase operation in response to a command to perform a programming operation. The controller may also temporarily suspend the erase operation without receiving a temporary suspension command. At 1110, the controller may perform a programming operation while the erase operation is temporarily suspended. In one instance, the controller may resume the erase operation without receiving a restore command in response to the completion of the programming operation. In another instance, the controller may resume the erase operation in response to receiving a restore command in response to the completion of the programming operation.

[0136] like Figure 11B As explained at 1112, the controller may further respond to a programming operation command by accepting the command and continuing the erase operation until an execution breakpoint is reached. At 1114, the controller may further respond to reaching an execution breakpoint by temporarily suspending the erase operation.

[0137] like Figure 11C As described at 1116, the controller can further receive data corresponding to the initial programming command and the final programming confirmation command in the event that the execution of the erase operation is temporarily suspended. At 1118, the controller can further perform a programming operation in response to the final programming confirmation command.

[0138] like Figure 11D As described at 1120, the controller may further receive first data corresponding to the initial programming command during the execution of the erase operation. At 1122, the controller may further perform a portion of the programming operation based on the first data in the event that the execution of the erase operation is temporarily suspended. At 1124, the controller may further receive second data corresponding to the initial programming command and the final programming confirmation command. At 1126, the controller may further perform the remaining portion of the programming operation in response to the final programming confirmation command.

[0139] like Figure 11E As explained at 1128, the controller can further receive programming commands, data corresponding to the programming commands, and a final programming confirmation command during the execution of the erase operation. At 1130, the controller can further perform programming operations if the execution of the erase operation is temporarily suspended.

[0140] like Figure 11F As described at 1132, the controller may further receive multiple commands to perform corresponding multiple programming operations in the event that the execution of the erase operation is temporarily suspended. At 1134, the controller may further execute multiple programming operations in response to the multiple commands to perform the corresponding multiple programming operations. In this embodiment, the memory device may further include a command register (e.g., Figure 1 (124) latches the multiple commands in the order they are received to perform the corresponding multiple programming operations. Therefore, the controller can further execute the multiple programming operations in the order they are received.

[0141] like Figure 11G As explained at 1136, the controller may further reduce the ready / busy control signal in response to performing an erase operation to indicate that the memory device is busy performing an erase operation. At 1138, the controller may further receive a command to perform a programming operation while the ready / busy control signal is reduced. At 1140, the controller may further temporarily suspend the execution of the erase operation in response to a command to perform a programming operation, while maintaining the ready / busy control signal reduced. At 1142, the controller may further perform a programming operation while the execution of the erase operation is temporarily suspended, while maintaining the ready / busy control signal reduced.

[0142] Figures 12A to 12D This is a flowchart of a method 1200 for operating a memory according to another embodiment. Method 1200 may at least partially correspond to Figures 6A to 6E For example, Figures 12A to 12D This can represent a method for temporarily suspending the erase operation to perform a programming operation and resuming the erase operation once the programming operation is complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0143] Method 1200 may be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 12AAs described at 1202, the controller can receive a command to perform an erase operation. At 1204, the controller can begin the execution of the erase operation in response to the erase operation command. At 1206, the controller can receive a command to temporarily suspend the execution of the erase operation. At 1208, the controller can temporarily suspend the execution of the erase operation in response to the command to temporarily suspend the execution of the erase operation. At 1210, the controller can receive a command to perform a programming operation if the execution of the erase operation is temporarily suspended. The programming operation command may include an initial programming command, a final programming confirmation command, a multi-plane programming confirmation command, a cache programming confirmation command, or another suitable programming command. At 1212, the controller can perform the programming operation in response to the programming operation command. At 1214, the controller can resume the execution of the erase operation in response to the completion of the programming operation. The controller can resume the execution of the erase operation even if a resume command is not received.

[0144] like Figure 12B As explained at 1216, the controller can further respond to a command to temporarily suspend the execution of the erase operation and continue the execution of the erase operation until the execution breakpoint is reached. At 1218, the controller can further respond to reaching the execution breakpoint and temporarily suspend the execution of the erase operation.

[0145] like Figure 12C As described at 1220, the controller may further receive multiple commands to perform corresponding multiple programming operations in the event that the execution of the erase operation is temporarily suspended. At 1222, the controller may further execute multiple programming operations in response to the multiple commands to perform the corresponding multiple programming operations. In this embodiment, the memory device may further include a command register (e.g., Figure 1 (124) latches the multiple commands in the order they are received to perform the corresponding multiple programming operations. Therefore, the controller can further execute the multiple programming operations in the order they are received.

[0146] like Figure 12D As explained at 1224, the controller may further pull down the ready / busy control signal in response to performing an erase operation to indicate that the memory device is busy performing an erase operation. At 1226, the controller may further receive a command to temporarily suspend the execution of the erase operation when the ready / busy control signal is pulled down. At 1228, the controller may further release the ready / busy control signal in response to temporarily suspending the execution of the erase operation to indicate that the memory device is ready. At 1230, the controller may receive a command to perform a programming operation when the ready / busy control signal is released. At 1232, the controller may further pull down the ready / busy control signal in response to resuming the execution of the erase operation.

[0147] Figure 13 This is a flowchart of a method 1300 for operating a memory according to another embodiment. Method 1300 may at least partially correspond to Figures 6A to 6E For example, Figure 13 This can represent a method for temporarily suspending the erase operation to perform a programming operation and resuming the erase operation once the programming operation is complete. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. These computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0148] Method 1300 may be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array, as previously at least referenced. Figures 1 to 2C As described. Figure 13 As described at 1302, the controller can receive a command to perform an erase operation. At 1304, the controller can initiate the execution of the erase operation in response to the command to perform the erase operation. At 1306, the controller can receive at least a portion of a command sequence for performing a programming operation while performing the erase operation, the command sequence including at least an initial programming command, an address, and data. At 1308, the controller can temporarily suspend the execution of the erase operation in response to at least a portion of the command sequence. In one embodiment, the controller can temporarily suspend the execution of the erase operation in response to receiving an address. In another embodiment, the controller can temporarily suspend the execution of the erase operation in response to receiving data. The controller can temporarily suspend the execution of the erase operation if no temporary suspend command is received. At 1310, the controller can perform a programming operation if the execution of the erase operation is temporarily suspended. The controller can further resume the execution of the erase operation if no resume command is received.

[0149] in conclusion

[0150] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array, The controller is further configured to: Receive commands to perform programming operations; In response to the command to perform the programming operation, the execution of the programming operation begins; In response to performing the programming operation, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the programming operation; When performing the programming operation, if the ready / busy control signal is pulled down, a command to perform a read operation is received; In response to the command to perform the read operation, the execution of the programming operation is temporarily suspended while the ready / busy control signal remains pulled down. as well as The read operation is performed while the execution of the programming operation is temporarily suspended and the ready / busy control signal is pulled down, while the ready / busy control signal remains pulled down.

2. The memory device of claim 1, wherein the controller is further configured to temporarily suspend the execution of the programming operation if no temporary abort command is received.

3. The memory device of claim 1, wherein the controller is further configured to: In response to the command to perform the read operation, accept the command to perform the read operation and continue the execution of the programming operation until an execution breakpoint is reached; and In response to reaching the execution breakpoint, the execution of the programming operation is temporarily suspended.

4. The memory device of claim 1, wherein the controller is further configured to: When performing the programming operation, multiple commands are received to perform corresponding multiple read operations; and The plurality of read operations are performed when the execution of the programming operation is temporarily suspended.

5. The memory device according to claim 4, further comprising: A command register, used to latch the plurality of commands in the order in which they are received to perform the respective plurality of read operations. The controller is further configured to execute the plurality of read operations in the order in which they are received.

6. The memory device of claim 1, wherein the controller is further configured to: In response to the completion of the read operation, the execution of the programming operation is resumed if no recovery command is received.

7. The memory device of claim 1, wherein the controller is further configured to: Upon completion of the read operation, the execution of the programming operation is resumed upon receiving a recovery command.

8. The memory device of claim 1, wherein the command for performing the read operation includes one of a read parameter page command, a read unique identifier ID command, a set feature command, a get feature command, a read page multiplane command, and an intermediate word line iWL read command.

9. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array, The controller is further configured to: Receives a command to perform an erase operation; In response to the command to perform the erasure operation, the execution of the erasure operation begins; In response to performing the erase operation, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation; When performing the erase operation, if the ready / busy control signal is pulled down, a command to perform a read operation is received; In response to the command to perform the read operation, the execution of the erase operation is temporarily suspended while the ready / busy control signal remains pulled down; as well as The read operation is performed while the erase operation is temporarily suspended and the ready / busy control signal is pulled down, while the ready / busy control signal remains pulled down.

10. The memory device of claim 9, wherein the controller is further configured to temporarily suspend the execution of the erase operation if no temporary abort command is received.

11. The memory device of claim 9, wherein the controller is further configured to: In response to the command to perform the read operation, accept the command to perform the read operation and continue the execution of the erase operation until an execution breakpoint is reached; and In response to reaching the execution breakpoint, the execution of the erase operation is temporarily suspended.

12. The memory device of claim 9, wherein the controller is further configured to: During the erase operation, multiple commands are received to perform corresponding multiple read operations; and If the execution of the erase operation is temporarily suspended, the plurality of read operations are performed.

13. The memory device of claim 12, further comprising: A command register, used to latch the plurality of commands in the order in which they are received to perform the respective plurality of read operations. The controller is further configured to execute the plurality of read operations in the order in which they are received.

14. The memory device of claim 9, wherein the controller is further configured to: In response to the completion of the read operation, the execution of the erase operation is resumed if no restore command is received.

15. The memory device of claim 9, wherein the controller is further configured to: Upon completion of the read operation, the execution of the erase operation is resumed upon receiving a restore command.

16. The memory device of claim 9, wherein the command for performing the read operation includes one of a read parameter page command, a read unique identifier ID command, a set feature command, a get feature command, a read page multiplane command, an intermediate word line iWL read command, a cache read command, and a copy-back command.

17. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array, The controller is further configured to: Receive commands to perform programming operations; In response to the command to perform the programming operation, the execution of the programming operation begins; Receive a command to temporarily suspend the execution of the programming operation; In response to the command to temporarily suspend the execution of the programming operation, the execution of the programming operation is temporarily suspended; In the event that the execution of the programming operation is temporarily suspended, a command to perform a read operation is received; In response to the command to perform the read operation, the read operation is executed; In response to performing the read operation, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the read operation; as well as In response to the completion of the read operation and the pull-down of the ready / busy control signal, the execution of the programming operation is resumed while the pull-down of the ready / busy control signal is maintained.

18. The memory device of claim 17, wherein the controller is further configured to resume the execution of the programming operation in the absence of a recovery command.

19. The memory device of claim 17, wherein the controller is further configured to: In response to the command to temporarily suspend the execution of the programming operation, the execution of the programming operation continues until an execution breakpoint is reached; and In response to reaching the execution breakpoint, the execution of the programming operation is temporarily suspended.

20. The memory device of claim 17, wherein the controller is further configured to: In the event that the execution of the programming operation is temporarily suspended, multiple commands are received to perform corresponding multiple read operations; and In response to the plurality of commands that perform the respective plurality of read operations, the plurality of read operations are executed.

21. The memory device of claim 20, further comprising: A command register, used to latch the plurality of commands in the order in which they are received to perform the respective plurality of read operations. The controller is further configured to execute the plurality of read operations in the order in which they are received.

22. The memory device of claim 17, wherein the controller is further configured to: In response to performing the programming operation, the ready / busy control signal is pulled down to indicate that the memory device is busy performing the programming operation; When the ready / busy control signal is pulled down, receive the command to temporarily suspend the execution of the programming operation; In response to temporarily suspending the execution of the programming operation, the ready / busy control signal is released to indicate that the memory device is ready; as well as When the ready / busy control signal is released, the command to perform the read operation is received.

23. The memory device of claim 17, wherein the command for performing the read operation includes one of a read parameter page command, a read unique identifier ID command, a set feature command, a get feature command, a read page multiplane command, and an intermediate word line iWL read command.

24. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array, The controller is further configured to: Receives a command to perform an erase operation; In response to the command to perform the erasure operation, the execution of the erasure operation begins; Receive a command to temporarily suspend the execution of the erasure operation; In response to the command to temporarily suspend the execution of the erase operation, the execution of the erase operation is temporarily suspended; In the event that the execution of the erase operation is temporarily suspended, a command to perform a read operation is received; In response to the command to perform the read operation, the read operation is executed; In response to performing the read operation, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the read operation; as well as In response to the completion of the read operation and the pull-down of the ready / busy control signal, the execution of the erase operation is resumed while the pull-down of the ready / busy control signal is maintained.

25. The memory device of claim 24, wherein the controller is further configured to resume the execution of the erase operation if no recovery command is received.

26. The memory device of claim 24, wherein the controller is further configured to: In response to the command to temporarily suspend the execution of the erase operation, the execution of the erase operation continues until an execution breakpoint is reached; and In response to reaching the execution breakpoint, the execution of the erase operation is temporarily suspended.

27. The memory device of claim 24, wherein the controller is further configured to: In the event that the execution of the erase operation is temporarily suspended, multiple commands are received to perform corresponding multiple read operations; and In response to the plurality of commands that perform the respective plurality of read operations, the plurality of read operations are executed.

28. The memory device of claim 27, further comprising: A command register, used to latch the plurality of commands in the order in which they are received to perform the respective plurality of read operations. The controller is further configured to execute the plurality of read operations in the order in which they are received.

29. The memory device of claim 24, wherein the controller is further configured to: In response to performing the erase operation, a ready / busy control signal is pulled down to indicate that the memory device is busy performing the erase operation; When the ready / busy control signal is pulled down, receive the command to temporarily suspend the execution of the erase operation; as well as In response to temporarily suspending the execution of the erase operation, the ready / busy control signal is released to indicate that the memory device is ready; When the ready / busy control signal is released, the command to perform the read operation is received.

30. The memory device of claim 24, wherein the command for performing the read operation includes one of a read parameter page command, a read unique identifier ID command, a set feature command, a get feature command, a read page multiplane command, an intermediate word line iWL read command, a cache read command, and a copy-back command.

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