Sensing circuit for sensing two states of a memory cell

Abstract

The present application relates to a sensing circuit for sensing two states of a memory cell. A device includes a memory array and a sensing circuit coupled to the memory array. The sensing circuit includes a sensing node coupled to a data line of the memory array. A first sensing path includes a first transistor having a first gate coupled to the sensing node. A second sensing path includes a second transistor having a second gate coupled to the sensing node. A first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by a threshold voltage gap.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a sensing circuit to simultaneously sense two states of a memory cell. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of the present disclosure provides a device comprising: a memory array; and a sensing circuit coupled to the memory array, wherein the sensing circuit comprises: a sensing node coupled to a data line of the memory array; a first sensing path comprising a first transistor having a first gate coupled to the sensing node, the first transistor having a first threshold voltage; and a second sensing path comprising a second transistor having a second gate coupled to the sensing node, wherein a first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by a threshold voltage gap.

[0004] Another aspect of the present disclosure provides an apparatus comprising: a memory array; and a sensing circuit coupled to the memory array, wherein the sensing circuit comprises: a sensing node coupled to a data line of the memory array; a first sensing path comprising a first transistor having a first gate coupled to the sensing node, the first transistor being defined by an internal threshold voltage; a second sensing path comprising a second transistor having a second gate coupled to the sensing node, the second transistor being defined by the internal threshold voltage; and a voltage source coupled to a source of the second transistor to shift a trip point of the second transistor by a threshold voltage gap.

[0005] Another aspect of the present disclosure provides a method comprising: capacitively boosting a sense node of a sense circuit to an initial voltage level, wherein the sense node is coupled to a data line of a memory array of a memory device; determining a first state of the sense node relative to the initial voltage level via a first sense path of the sense circuit; simultaneously determining a second state of the sense node relative to a combination of the initial voltage level and a threshold voltage gap via a second sense path of the sense circuit; and creating a histogram from the first state and the second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings according to some embodiments of the present disclosure.

[0007] Figure 1A An example computing system including a memory subsystem in accordance with some embodiments is illustrated.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figures 2A to 2C According to the embodiment, the Figure 1B Schematic diagram of a portion of a memory cell array used in a memory of the type described.

[0010] Figure 3 According to the embodiment, the Figure 1B A block diagram of a portion of a memory cell array used in memories of the type described.

[0011] Figure 4 is a conceptual depiction of threshold voltage distributions for a plurality of memory cells of a memory array according to an embodiment.

[0012] Figures 5A to 5B is a conceptual depiction of threshold voltage distributions for a plurality of memory cells at different stages after programming for various embodiments.

[0013] Figure 6 is a schematic diagram of a sensing circuit capable of simultaneously sensing two states of a memory cell, according to some embodiments.

[0014] Figure 7A is a graph illustrating timing of obtaining histogram data from two different voltage boosts applied to a sense node during a sensing operation of a single path sensing circuit according to an embodiment.

[0015] Figure 7B is a graph illustrating the timing of boosting a sense node to an initial voltage level and then determining two different states of the sense node using two different sensing paths according to an embodiment.

[0016] Figure 8A is a graph illustrating a set of histograms obtained from five equally spaced boosted voltages applied to a sense node of a single path sensing circuit, according to an embodiment.

[0017] Figure 8B is a graph illustrating a set of histograms obtained from four different boosted voltages using two different sensing paths of a sensing circuit, wherein the sensing voltage gap is smaller than the threshold voltage gap, according to an embodiment.

[0018] Figure 8C is a graph illustrating a set of histograms obtained from four different boosted voltages using two different sensing paths of a sensing circuit, wherein the sensing voltage gap is greater than the threshold voltage gap, according to an embodiment.

[0019] Figure 9 It's a picture Figure 8B A set of histograms with Figure 8A The boost voltage is compared with the curve graph.

[0020] Figure 10 is a flow chart of an example method for simultaneously sensing two states of a memory cell using a sensing circuit having two sensing paths, according to some embodiments.

[0021] Figure 11 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure relate to a sensing circuit suitable for simultaneously sensing two states of a memory cell. Various access operations can be performed on the memory cell. For example, data can be written to the memory cell, read from the memory cell, and erased from the memory cell. The memory cells can be grouped into write units (e.g., pages). For some types of memory devices, a page is the smallest write unit. A word line can have multiple pages grouped into sub-blocks on the same word line. Typically, one sub-block is accessed at any given time. Although each sub-block has its own set of select gates coupled to the bit line, the sub-blocks share a common page buffer, also referred to herein as a "sensing circuit."

[0023] In certain memory systems, charge loss occurs within a memory cell, where the threshold voltage (Vt) of the memory cell may drift from its originally programmed level, making it more difficult to determine the logic state of the memory cell, especially as the memory cell loses more charge over time. More specifically, the read window bandwidth between adjacent threshold voltage distributions encoding two different logic states may narrow, making it more difficult to find a local minimum between adjacent threshold voltage distributions where a transition between logic states can be determined.

[0024] In these memory systems, a local media controller can cause the sensing circuitry used to access memory cells within a page buffer to perform parallel automatic read calibration on the memory cells using several boost regulators. The boost regulators can provide different boost voltages to capacitively change the voltage at a sensing node of the sensing circuitry coupled to a data line. The first boost voltage can bring the sensing node to an initial voltage, and each subsequent boost voltage can slightly change the voltage at the sensing node. In some memory systems, two separate sensing operations use a total of five different boost voltage levels to sense (e.g., attempt to read or verify) a memory cell via the data line. The sensed voltage levels along the cell's adjacent threshold voltage distribution can generate histogram data—in this case, four histograms detecting threshold voltage levels between adjacent threshold voltage distributions. By analyzing these histograms, the local media controller can determine a local minimum. The sensing circuitry can then use the voltage level associated with the local minimum as the boost voltage level for reading data from the memory cell (e.g., to distinguish between two logical states). However, performing a sensing operation in this manner is a slow process (eg, hundreds of nanoseconds per boost of the sense node), thereby causing a significant delay in performing a read operation on the memory cell.

[0025] Aspects of the present disclosure address the above and other deficiencies by eliminating at least one boost to a sense node while still generating a number of histograms (e.g., four histograms) for determining local minima. More specifically, a sense circuit for a page buffer containing a sense node can employ two sense paths rather than a single sense path. The second sense path can be designed to have a built-in difference in the trigger point for sensing a particular voltage, where the built-in difference is approximately equal to the threshold voltage gap that would be provided by a separate boost to the sense node. In this way, the addition of a small amount of hardware emulates the performance of a separate boost and thereby saves time that would otherwise be consumed by applying the separate boost.

[0026] In one embodiment, a first sensing path of the two sensing paths includes a first transistor having a first gate coupled to a sensing node. A second sensing path includes a second transistor having a second gate coupled to the sensing node. A first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by a threshold voltage gap. Each of the first and second transistors can be directly coupled to ground and can be an n-channel metal oxide semiconductor (NMOS) transistor or a p-channel metal oxide semiconductor (PMOS) transistor. For example, the channel of the second transistor can be implanted with a different dose than that of the first transistor to provide the threshold voltage gap.

[0027] In another embodiment, the second sense path includes a second transistor having a second gate coupled to the sense node, wherein the second transistor is also defined by the same internal threshold voltage (e.g., a trigger gate-source voltage, or Vgs of the transistor). However, in this embodiment, a voltage source is coupled to the source of the second transistor to shift the trip point of the second transistor by a threshold voltage gap. In one embodiment, the voltage source is a source-to-ground regulator coupled between the source of the second transistor and ground to variably adjust the voltage bias at the source of the second transistor, thereby adjusting the trip point. The trip point is the point at which Vgs equals the threshold voltage of the transistor, turning the transistor on.

[0028] Thus, advantages of systems and methods implemented according to some embodiments of the present disclosure include, but are not limited to, the ability to determine two separate states of a memory cell by sensing at a sense node of a sense circuit via two separate sensing paths, one of which senses at slightly different voltages. Reducing sensing operations by even a single voltage boost can significantly reduce the read time to complete a read operation or program verify operation. Furthermore, as will be discussed, the dual-path sensing design effectively increases the voltage sensing range, thereby providing an additional range of histogram data in the sensed voltage states of a memory cell. Additional advantages will be apparent to those skilled in the art of scanning programming word lines within a memory subsystem, as discussed below.

[0029] Figure 1A An example computing system 100 including a memory subsystem 110 is illustrated, according to some embodiments of the present disclosure. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media or memory devices. Memory subsystem 110 may be a storage device, a memory module, or a hybrid of storage devices and memory modules.

[0030] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more die. Each die may include one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page contains a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits stored. A logical state may be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0031] Memory device 130 may be composed of bits arranged in a two-dimensional or three-dimensional grid (also referred to as a memory array). Memory cells are etched on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device that are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell.

[0032] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0033] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or networked commercial device), or such a computing device that includes a memory and a processing device.

[0034] The computing system 100 may include a host system 120 that is coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is shown. The host system 120 can provide data to be stored at the memory subsystem 110 and can request to retrieve data from the memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0035] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0036] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual Inline Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0037] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0038] Some examples of non-volatile memory devices (e.g., memory device 130) include negative sum (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0039] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0040] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), negative-OR (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0041] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0042] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0043] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 is shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0044] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0045] The memory subsystem 110 may also include additional circuits or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0046] In some embodiments, memory device 130 includes a local media controller 135 that operates with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., local media controller 135) on the die and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0047] In some embodiments, memory device 130 includes sensing circuitry 138, which can be, for example, a page buffer. Sensing circuitry 138 can be designed with two sensing paths to simultaneously sense both states of a sensing node, and thus sense memory cells of a memory array coupled to the sensing node, for the purpose of obtaining histogram data. Local media controller 135 can analyze the histogram data to determine a local minimum between two adjacent threshold voltage distributions within a memory cell. Sensing circuitry 138 can then use the voltage level associated with the local minimum as a boosted voltage level to read data from the memory cell.

[0048] Figure 1B is in accordance with an embodiment with a memory subsystem (e.g., Figure 1A 1 is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem 110 (e.g., a memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical appliances, vehicles, wireless devices, mobile phones, etc. Memory subsystem controller 115 (e.g., a controller external to memory device 130) may be a memory controller or other external host device.

[0049] Memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. Memory cells ( Figure 1B (not shown) can be programmed to one of at least two target data states.

[0050] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals prior to decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch input commands.

[0051] A controller (e.g., a local media controller 135 within the memory device 130) controls access to the memory cell array 104 in response to the command and generates status information for the external memory subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuit 108 and the column decoding circuit 111 to control the row decoding circuit 108 and the column decoding circuit 111 in response to the address.

[0052] The local media controller 135 also communicates with the cache register 118 and the data register 121. The cache register 118 latches input or output data as directed by the local media controller 135 to temporarily store the data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from the cache register 118 to the data register 121 for transfer to the memory cell array 104; then, the new data may be latched in the cache register 118 from the I / O control circuit 112. During a read operation, data may be transferred from the cache register 118 to the I / O control circuit 112 for output to the memory subsystem controller 115; then, the new data may be transferred from the data register 121 to the cache register 118. The cache register 118 and / or the data register 121 may form (e.g., may form part of) a page buffer of the memory device 130. The page buffer may further include a sensing device, such as a sensing circuit 138 ( Figure 1A ), also known as a sense amplifier, to sense the data state of a memory cell connected to the memory cell array 104, for example, by sensing the state of a data line of the memory cell. The status register 122 can communicate with the I / O control circuit 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0053] The memory device 130 receives control signals from the local media controller 135 at the memory subsystem controller 115 via a control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be received via the control link 132. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 134, and outputs the data to the memory subsystem controller 115 via the I / O bus 134.

[0054] For example, a command may be received at the I / O control circuit 112 via input / output (I / O) pins [7:0] of the I / O bus 134 and may be written to the command register 124. An address may be received at the I / O control circuit 112 via input / output (I / O) pins [7:0] of the I / O bus 134 and may be written to the address register 114. Data may be received at the I / O control circuit 112 via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device and may be written to the cache register 118. The data may then be written to the data register 121 to program the memory cell array 104.

[0055] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although reference may be made to I / O pins, these may include any conductive nodes, such as conventional conductive pads or conductive bumps, that enable electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115).

[0056] Those skilled in the art will appreciate that additional circuits and signals may be provided, and Figure 1B The memory device 130 has been simplified. It should be appreciated that the reference Figure 1B The functions of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Additionally, although specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0057] Figures 2A to 2C According to the embodiment, the Figure 1B Schematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) used in a memory of the type described (e.g., used as part of the memory cell array 104). The memory array 200A includes access lines (e.g., word lines 2020 to 2024). N ) and data lines (eg, bit lines 2040 to 204 M ). The word lines 202 may be connected to the Figure 2AFor some embodiments, memory array 200A may be formed over a semiconductor, which, for example, may be conductively doped to have a conductivity type such as p-type conductivity (e.g., to form a p-well) or n-type conductivity (e.g., to form an n-well).

[0058] The memory array 200A may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060 through 206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 may represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 may be connected in series at a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 210 M One of the transistors (eg, which may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 is connected to the drain select transistor 2100. M The gates 2120 to 212 may be commonly connected to a select line 214, such as a source select line (SGS), and the select gates 2120 to 212 M They may be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as conventional field effect transistors, select gates 210 and 212 may utilize a structure similar to (e.g., identical to) that of memory cell 208. Select gates 210 and 212 may represent a plurality of select gates connected in series, with each select gate configured in series to receive the same or independent control signals.

[0059] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of a corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0060] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0061] Figure 2A The memory array in can be a quasi-two-dimensional memory array and can have a substantially planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and perpendicular to a plane containing the bit lines 204, which can be substantially parallel to the plane containing the common source 216.

[0062] The typical structure of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, etc.) that can determine the data state of the memory cell (e.g., by changing the threshold voltage) and a control gate 236, such as Figure 2A . Data storage structure 234 can include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. Memory cell 208 has its control gate 236 connected to (and in some cases forming) word line 202.

[0063] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 may be memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may generally be divided into one or more physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 may generally be divided into one or more physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. NThe memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be one physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 typically connected to the word lines 202 N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of memory cells 208 (eg, odd memory cells).

[0064] Although bit lines 2043 to 2045 are not Figure 2A It is clearly depicted in the figure, but it is obvious from the figure that the bit line 204 of the memory cell array 200A can be from the bit line 2040 to the bit line 204 M 202. Other groupings of memory cells 208 that are commonly connected to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all of the memory cells that are commonly connected to a given word line may be considered a physical page of memory cells. A portion of a physical page of memory cells (which may still be an entire row in some embodiments) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 202. N All memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished otherwise, references to a page of memory cells herein refer to memory cells of a logical page of memory cells. Although discussed in conjunction with NAND flash memory, Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0065] Figure 2B It is available in the reference Figure 1B Another schematic diagram of a portion of a memory cell array 200B (eg, as part of memory cell array 104) for use in a memory of the type described. Figure 2B The same numbered elements in the Figure 2A Provide a description. Figure 2BAdditional details of one example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as the channel region of the memory cells of the NAND string 206. The NAND strings 206 can each be selectively connected to bit lines 2040 through 204 through select transistors 212 (e.g., which can be drain select transistors, often referred to as select gate drain). M , and are selectively connected to a common source 216 through a select transistor 210 (e.g., which may be a source select transistor, often referred to as a select gate source). Multiple NAND strings 206 may be selectively connected to the same bit line 204. Subsets of NAND strings 206 may be selectively connected to the same bit line 204 by biasing select lines 2150 to 215 K The word lines 202 are connected to their corresponding bit lines 204 to selectively activate each particular select transistor 212 between the NAND string 206 and the bit line 204. The select gate transistors 210 can be activated by biasing the select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells connected to each other by a particular word line 202 can generally be referred to as a layer.

[0066] Figure 2C It is available in the reference Figure 1B Another schematic diagram of a portion of a memory cell array 200C (eg, as part of memory cell array 104) for use in a memory of the type described. Figure 2C The same numbered elements in the Figure 2A The memory cell array 200C may include a memory cell string (e.g., a NAND string) 206, an access (e.g., word) line 202, a data (e.g., bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216 connected in series. Figure 2A For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C.

[0067] Figure 2C Depicts grouping the NAND strings 206 into memory cell blocks 250, for example, memory cell blocks 2500 through 250. L Memory cell blocks 250 may be groupings of memory cells 208 that may be erased together in a single erase operation, sometimes referred to as erase blocks. Each memory cell block 250 may represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The sources 216 of the memory cell blocks 2500 may be the same as the source of the memory cell blocks 250. L For example, each memory cell block 2500 to 250L Typically, the access line 202 and the select lines 214 and 215 of one memory cell block 250 may not be directly connected to the memory cell blocks 250 to 250, respectively. L The access line 202 and the select lines 214 and 215 of any other memory cell block are connected.

[0068] Data lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to a buffer portion 240, which may be part of a page buffer of a memory. The buffer portion 240 may correspond to a memory plane (eg, a group of memory cell blocks 2500 to 250 L ). The buffer portion 240 may include sensing circuitry (eg, Figures 1A to 1B sensing circuit 138).

[0069] Figure 3 It is available in the reference Figure 1B 3. A block diagram of a portion of a memory cell array 300 used in a memory of the type described. The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500 through 3503), each in communication with a respective buffer portion 240 that may collectively form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may generally be in communication with the page buffer 352. Each memory plane 350 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 through 2503). L ).

[0070] Figure 4 is a conceptual depiction of the threshold voltage ranges for multiple memory cells. Figure 4 An example of a threshold voltage range and its distribution for a population of sixteen-level memory cells (eg, QLC memory cells) is shown. For example, such memory cells can be programmed to fall within sixteen different threshold voltage ranges 4300 to 4300. 15 Each threshold voltage range is used to represent a data state corresponding to a four-bit bit pattern. The threshold voltage range 4300 generally has a higher threshold voltage than the remaining threshold voltage ranges 4301 to 430 15 The larger width, because the memory cells are generally in data states corresponding to the threshold voltage range 4300, and then a subset of these memory cells are subsequently programmed to have data states in the threshold voltage range 4301 to 430 15 Since programming operations are typically more incrementally controlled than erase operations, these threshold voltage ranges 4301 to 430 15tend to have a tighter distribution.

[0071] Threshold voltage range 4300, 4301, 4302, 4303, 4304, 4305, 4306, 4307, 4308, 4309, 430 10 , 430 11 , 430 12 , 430 13 , 430 14 and 430 15 Each of the data states can be represented by a separate data state, such as L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15. For example, if the threshold voltage of a memory cell is within the first threshold voltage range 4300 of the sixteen threshold voltage ranges, the memory cell may store data state L0 having a data value of logic "1111" and is generally referred to as the erased state of the memory cell. If the threshold voltage is within the second threshold voltage range 4301 of the sixteen threshold voltage ranges, the memory cell may store data state L1 having a data value of logic "0111". If the threshold voltage is within the third threshold voltage range 4302 of the sixteen threshold voltage ranges, the memory cell may store data state L2 having a data value of logic "0011", and so on. Table 1 provides one possible correspondence between data states and their corresponding logical data values. Other assignments of data states to logical data values ​​are known or foreseeable. As used herein, memory cells remaining in the lowest data state (eg, the erased state or the L0 data state) will be considered to be programmed to the lowest data state.

[0072] Data Status Logical data values Data Status Logical data values L0 1111 L8 1100 L1 0111 L9 0100 L2 0011 L10 0000 L3 1011 L11 1000 L4 1001 L12 1010 L5 0001 L13 0010 L6 0101 L14 0110 L7 1101 L15 1110

[0073] Table 1

[0074] Figures 5A to 5BThis is a conceptual depiction of the threshold voltage distributions of multiple memory cells at different stages after programming for an embodiment. After programming, the threshold voltage of a memory cell may shift due to phenomena such as quick charge loss (QCL). QCL is the process by which electrons near the gate dielectric interface are trapped outward into the channel region of the memory cell and can cause a Vt shift shortly after the programming pulse. When the memory cell passes a verify operation, the programmed threshold voltage may appear higher due to trapped charge in the gate dielectric layer. When the memory cell is read after the programming operation has completed, the Vt of the memory cell may be lower than the Vt achieved during the program verify operation due to charge leakage from the gate dielectric layer into the channel region. The threshold voltage of a memory cell may further shift due to accumulated charge loss over the age of its programmed data (e.g., the period between programming the data and reading the data, referred to herein as data age). Charge loss is also affected by the age of the memory cell. In contrast to data age, the age of a memory cell is typically indicated by the number of program / erase cycles the memory cell has undergone. These various phenomena may cause the threshold voltage distribution to widen and shift over time. Various embodiments provide apparatus and methods that may facilitate alleviating these problems.

[0075] Figure 5A is a conceptual depiction of the threshold voltage distribution of a plurality of memory cells after (eg, immediately following) a programming operation, and Figure 5B is a conceptual depiction of those same threshold voltage distributions at some later time after the programming operation. Figure 5A and Figure 5B Threshold voltage distribution 530 d to 530 d+1 Can indicate when the programming operation of the memory cell is completed Figure 4 The threshold voltage range is 4300 to 430 15 some part of the distribution.

[0076] refer to Figure 5A , adjacent threshold voltage distributions 530 are typically separated by a certain margin 532 (e.g., a dead zone) when programming is complete. Applying a sensing voltage (e.g., a read voltage) within the margin 532 to the control gates of multiple memory cells can be used to distinguish the threshold voltage distributions 530. d (and any lower threshold voltage distributions) with the threshold voltage distribution 530 d+1 (and any higher threshold voltage distribution), can be assumed to be error-free.

[0077] refer to Figure 5B , the adjacent threshold voltage distribution can be widened so that the threshold voltage distribution 530 d and threshold voltage distribution 530 d+1The two adjacent threshold voltage distributions may merge as represented by curve 534, which indicates the sum of the two adjacent threshold voltage distributions. Curve 534 may have a local minimum 536. In the event that such merging of adjacent threshold voltage distributions occurs, the threshold voltage distribution 530 may be distinguished from the distribution of the threshold voltage distribution 530. d The memory cells in the threshold voltage distribution 530 are intended to be d+1 536 will typically result in some errors. For example, applying a sensing voltage having a voltage level corresponding to local minimum 536 to the control gates of a plurality of memory cells can be expected to produce a minimum number of memory cells having data states different from their target (e.g., intended) data states, but a certain number of errors will typically be unavoidable. Applying a sensing voltage at a voltage level higher or lower than the voltage level corresponding to local minimum 536 can be expected to produce a greater number of errors. While applying a sensing voltage having a voltage level corresponding to local minimum 536 of curve 534 can produce the least number of errors, it can be difficult to determine at what voltage level this local minimum 536 occurs.

[0078] Sense circuits are often used in memory devices to facilitate performing a sensing (eg, reading and / or verifying) operation on each of one or more selected (eg, target) memory cells in the memory device. Figure 6 is a schematic diagram of a sensing circuit 600 capable of simultaneously sensing two states of a memory cell according to some embodiments. In one embodiment, the sensing circuit 600 is part of a page buffer, as previously discussed. The sensing circuit 600 is shown connected to a specific NAND string 206 via a specific data line 204, e.g. Figure 2A More detailed diagram in . Note that Figure 6 Not shown are select gate transistors 210 and 212 that selectively connect the NAND string 206 to the source 216 and the data line 204, respectively. While the discussion is directed to the sensing circuit 600 for use with the NAND string 206, other memory structures and architectures are suitable for use with the sensing circuit 600 in which a current path from the data line 204 to the source 216 can be selectively created depending on the data state of the memory cell selected for sensing.

[0079] As part of a sensing operation, such as a precharge portion, sensing circuit 600 may precharge a sensing node (e.g., tc node) 640 by activating precharge transistor 644 (e.g., an n-type field-effect transistor, or nFET) by biasing (e.g., driving) signal line 642 to a specific voltage level (e.g., the voltage level of control signal blpre) sufficient to activate precharge transistor 644. Control signals for sensing circuit 600 may be provided by an internal controller of memory device 130 (e.g., local media controller 135). Such control signals (e.g., both voltage levels and timing) may be defined by the sensing operation and distinguished from signals generated in response to performing the sensing operation (e.g., output signals sa_out1 and sa_out2 or the voltage level generated on sensing node 640). The sensing operation may be, for example, a read operation for providing data output from a memory cell array, or a verify operation for verifying whether a programming pulse successfully changed the threshold voltage of a target memory cell to indicate its desired data state.

[0080] In some embodiments, pre-charge transistor 644 is connected between voltage node 646 and sense node 640. Voltage node 646 can be configured to receive a power supply voltage, such as Vcc. For some embodiments, voltage node 646 can be a variable voltage node. Capacitor 648 coupled to sense node 640 can represent the capacitance at sense node 640 and additional circuitry connected thereto (e.g., transistors 644, 650, 652, and 672). Voltage node 654 (e.g., a variable voltage node) is configured to apply a voltage level to capacitor 648 that can cause a change in the voltage level on sense node 640, such as to boost sense node 640 to a higher voltage level through capacitive coupling.

[0081] To provide a boosted voltage to voltage node 654, voltage node 654 may be coupled to a plurality of boost regulators 680A, 680B, 680C, and 680D. Multiplexer 690 may be operatively connected between boost regulators 680A...680D and voltage node 640 to couple to capacitor 648, for example. A select line 691 of multiplexer 690 may be coupled to local media controller 135 ( Figure 1B ) coupled, the local media controller 135 can thus control the selection of one of the boost regulators 680A ... 680D for pre-changing the capacitor 648 or selectively adjusting the charge of the capacitor 648 after pre-charging in order to perform a sensing operation. In various embodiments, the boost regulators 680A ... 680D and the multiplexer 690 are integrated within the sensing circuit 600 or are part of a page buffer of which the sensing circuit 600 is a part.

[0082] Additional transistor paths of the sensing circuit 600 facilitate sensing of the voltage level on the sense node 640. In this embodiment, at least two sense paths are provided, such as a first sense path 649 and a second sense path 669, although additional sense paths are contemplated. In some embodiments, the first sense path 649 includes a first select transistor 658 having a gate coupled to the first sense signal line 656, a drain coupled to the voltage node 660, and a source coupled to the first sense transistor 650 of the first sense path 649. The first sense transistor 650 may have a gate coupled to the sense node 640, a drain coupled to the source of the first select transistor 658, and a source coupled to ground. Thus, the first sense transistor 650 is configured to respond to the voltage level present on the sense node 640. The output of the first sense path 649 (sa_out1) may be taken from the source of the first sense transistor 650. The first sense signal line 656 can be configured to receive a control signal sen1 that facilitates isolating the first sense transistor 650 from a voltage node 660, which can be configured to receive a power supply voltage (e.g., Vcc). In various embodiments, the first select transistor 658 and the first sense transistor 650 can be either n-channel metal oxide semiconductor (NMOS) transistors comprising nFETs (as shown) or p-channel metal oxide semiconductor (PMOS) transistors comprising pFETs.

[0083] In some embodiments, the second sense path 669 includes a second select transistor 678 having a gate coupled to the second sense signal line 676, a drain coupled to the voltage node 662, and a source coupled to the second sense transistor 672 of the second sense path 669. The second sense transistor 672 can have a gate also coupled to the sense node 640, a drain coupled to the source of the second select transistor 658, and a source coupled to ground. Thus, the second sense transistor 672 is configured to respond to the voltage level present on the sense node 640. The output (sa_out2) of the second sense path 669 can be taken from the source of the second sense transistor 676. The second sense signal line 676 can be configured to receive a control signal sen2 that helps isolate the second sense transistor 672 from the voltage node 662, which can be configured to receive a power supply voltage (e.g., Vcc). In various embodiments, the first select transistor 658 and the first sense transistor 650 are either n-channel metal oxide semiconductor (NMOS) transistors comprising nFETs (as shown) or p-channel metal oxide semiconductor (PMOS) transistors comprising pFETs.

[0084] To create a threshold voltage gap between the first sensing path 649 and the second sensing path 669, the first sensing transistor 650 and the second sensing transistor 672 in these different sensing paths can be fabricated differently (e.g., with different Vt) or biased to different trip points, as will be explained below. The sensing circuit 600 can be designed to generate a threshold voltage gap between the two sensing paths, for example, between 150 and 220 millivolts (mV). In one embodiment, the threshold voltage gap is 180 mV, provided as an example (see Figure 7B ).

[0085] More specifically, in one embodiment, the first sensing transistor 650 may have a first threshold voltage (Vt), and the second sensing transistor 676 may have a second threshold voltage 684 (e.g., Vt2) that differs from the first threshold voltage by a threshold voltage gap, e.g., Vt+Vt(gap). Because this is an optional embodiment, Vt2, which is shown as the second threshold voltage 684, is surrounded by a dashed line. For example, if the second sensing transistor 672 is an NMOS transistor, the n-channel of the second sensing transistor 672 includes a different n-type implant dose than the n-channel of the first sensing transistor 650, and the different n-type implant dose is used to provide the threshold voltage gap. Furthermore, for example, if the second sensing transistor 672 is a PMOS transistor, the p-channel of the second transistor includes a different p-type implant dose than the p-channel of the first transistor, and the different p-type implant dose is used to provide the threshold voltage gap.

[0086] In another embodiment, each of the first sense transistor 650 and the second sense transistor 672 has the same threshold voltage (e.g., the same Vgs value within manufacturing tolerances), and the second sense path further includes a voltage source 682 coupled to the source of the second sense transistor 672 to shift the trip point of the second sense transistor 672 by a threshold voltage gap. For example, where the source of the first sense transistor 650 is coupled to (or connected to) ground, the source of the second sense transistor 672 is coupled to (or connected to) the voltage source 682, where the voltage source 682 is coupled to ground. In one embodiment, the voltage source 682 is a source-to-ground regulator coupled between the source of the second sense transistor 672 and ground to variably adjust the voltage bias at the source of the second transistor, thereby adjusting the trip point.

[0087] In various embodiments, the sense circuit output lines (e.g., sa_out1 and sa_out2) may be connected to additional circuitry (not shown) of the memory device 130 that is configured to respond to the sense circuit 600 as part of a sensing operation. For example, the sense circuit 600 may be Figure 1B1 and sa_out2, and its outputs sa_out1 and sa_out2 may be provided as inputs to the cache register 118 for outputting the sensed data state from the memory device 130. The output signal sa_out1 on the output line may include a signal generated by a latch (e.g., a latch circuit not shown) that represents a logic level, such as a logic “high” (e.g., represented by Vcc) or a logic “low” (e.g., represented by Vss) level indicative of the sensed data state of the selected memory cell of the NAND string 206.

[0088] During the precharge portion of the sensing operation, the gate of precharge transistor 644 can be biased by a voltage level on signal line 642 (e.g., the voltage level of control signal blpre) to precharge sense node 640 by injecting a precharge current into sense node 640. An additional voltage level (e.g., the voltage level of control signal blclamp) can be applied to signal line 666 to activate transistor 668 (e.g., an nFET), and another voltage level (e.g., the voltage level of control signal tc_iso) can be applied to signal line 670 to activate transistor 652 (e.g., an nFET). Activating transistors 644, 652, and 668 can be used to connect data line 204 to voltage node 646, thereby precharging sense node 640 and data line 204.

[0089] After precharging the sense node 640 and the data line 204, a second portion of the sensing operation can be performed to detect whether the data line 204 and the sense node 640, which were precharged during the sensing operation, have discharged, thereby determining the data state of the memory cell selected for sensing. Because the sensing circuit 600 utilizes two different sensing paths 649 and 669, a single sensing operation can be performed to detect two different states of a memory cell, for example, with reference to a first threshold voltage and a different second threshold voltage, or with reference to the same threshold voltage but with different trip points for the second sense transistor 672.

[0090] In some embodiments, after precharging sense node 640 and data line 204, sense node 640 can be isolated from data line 204, for example, by deactivating transistor 668 and / or deactivating transistor 652. Data line 204 can then be selectively connected to source 216 depending on whether the memory cell selected for sensing is activated or deactivated in response to the sense voltage applied to its control gate. After giving data line 204 an opportunity to discharge, if current flows through NAND string 206, sense node 640 can be reconnected to data line 204 by activating transistors 652 and 668.

[0091] In various embodiments, if the voltage level of data line 204 drops below the precharge voltage level due to current flowing through NAND string 206, the voltage level of sense node 640 may also drop. If the voltage level of data line 204 remains at the precharge voltage level, such as when the memory cell selected for sensing remains disabled, the voltage level of sense node 640 may remain at its precharge (or boosted) voltage level. When transistors 658 and 678 are activated and the voltage level of sense node 640 is applied to the control gates of first sense transistor 650 and second sense transistor 672, voltage nodes 660 and 662 may be selectively connected to sense outputs sa_out1 and sa_out2 depending on the voltage level of sense node 640. As discussed, a latch may also be coupled to each of these sense outputs of sense circuit 600 to track and provide an output for sensing the voltage level of sense node 640 with reference to the trip points of first sense transistor 650 and second sense transistor 672. In one embodiment, each of the sense outputs sa_out1 and sa_out2 is coupled to the same latch, and the sen1 and sen2 signals are switched one at a time to create a histogram, which will be discussed in more detail. In another embodiment, a set of latches is employed, one latch for holding sa_out1 and another latch for holding sa_out2, where no switching is required and both states associated with the two sense paths can be stored simultaneously.

[0092] Various embodiments may utilize boosting and depressurizing of the sense node 640 during sensing operations. For example, boosting (e.g., capacitively coupling a first boosted voltage level to) and depressurizing (e.g., capacitively coupling a second, lower boosted voltage level to) the sense node 640 may be used to facilitate higher development overhead. By boosting the sense node 640 before the sense node develops, the voltage level of the sense node 640 may be allowed to develop for a longer period of time without prematurely indicating current flow in the data line 204. After isolating the NAND string 206 from the data line 204, the subsequent depressurization of the sense node 640 may allow the voltage level of the sense node 640 to drop below the trip point (e.g., threshold voltage) of the first sense transistor 650 and the second sense transistor 672, indicating that current flow (e.g., threshold level of current flow) has been detected. In sequential sensing performed by the sense circuit 600 during one or more sensing operations, multiple boost regulators 680A...680D may be used to provide boosted voltages to the voltage node 654 (e.g., to the capacitor 648). Multiple boost regulators 680A...680D may also be multiplexed to additional sensing circuits to perform parallel sensing operations on multiple memory cells.

[0093] In some embodiments, data lines corresponding to activated memory cells whose threshold voltages are closer to the sense voltage applied to their control gates are expected to experience lower discharge levels and higher resulting voltage levels at sense node 640 than data lines corresponding to activated memory cells whose threshold voltages are further away from the sense voltage applied to their control gates. Thus, a sense node 640 indicating activation of its corresponding memory cell at one boosted voltage level during decompression can indicate deactivation of its corresponding memory cell at a different (e.g., higher) boosted voltage level during decompression. This phenomenon can be used to compensate for sense voltages that are above or below a local minimum between two adjacent threshold voltage distributions. Various embodiments utilize multiple boosted voltage levels coupled to a sense node during a single sensing operation to estimate conditions that can indicate activation of those memory cells whose threshold voltages are below the local minimum and deactivation of those memory cells whose threshold voltages are above the local minimum, e.g., to estimate the location of the local minimum.

[0094] The trip points of the two sense paths 649 and 669 of the sense circuit 600 can generally depend on the threshold voltages of the first sense transistor 650 and the second sense transistor 672, respectively. The sense circuit 600 can be configured to have a trip point (e.g., a sensing threshold level) that is close to a precharge voltage level that can be established on the sense node 640 before sensing a selected memory cell. The trip points can be specific voltage levels on the sense node 640, where, for example, when the voltage level of the sense node 640 is equal to or greater than the first trip point, the first sense path 649 outputs a first logic level indicating a first state of the sense node 640, and, for example, when the voltage level of the sense node 640 is equal to or greater than the second trip point, the second sense path 669 outputs a second logic level indicating a second state of the sense node 640. For example, when the voltage level of the sense node 640 is below the trip point of the first sense transistor 650, the sense circuit 600 can output a third logic level indicating a third state of the sense node 640. For example, when the voltage level of the sense node 640 is below the trip point of the second sense transistor 672, the sense circuit 600 may output a fourth logic level indicating a fourth state of the sense node 640. The sensed state of the sense node 640 may be used to provide an indication of the data state of the sensed memory cell, including providing histogram data to the local media controller 135.

[0095] Figure 7A is a diagram illustrating a voltage applied to a sensing node 640 ( Figure 6) to obtain histogram data at two different voltage boosts. For example, such a single-path sensing circuit would only include the first sense path 649. In this embodiment, a first depressurization of the voltage at the sense node 640 can provide an initial depressurization of the sense node 640, thereby bringing the sense node voltage close to (but above) the threshold voltage (Vt) of the first sense transistor 650. A further second depressurization of the voltage at the sense node 640 can provide a second depressurization close to (but below) the threshold voltage Vt. Sensing of the data state can be performed at each boosted voltage level of the sense node 640. As discussed, the need to depressurize twice to provide histogram data at two depressurization levels can result in significant read delays.

[0096] Figure 7B is a graph illustrating the timing of boosting a sense node to an initial voltage level and then determining two different states of the sense node using two different sensing paths according to an embodiment. Figure 7A In the graph of FIG. 1 , the boost regulator can provide an initial decompression to the sense node 640 to bring the sense node 640 to an initial voltage level. In one embodiment, the initial voltage level is the difference between the threshold voltage of the first sense transistor 650 and the gate-source voltage drop (Vgs) of the first sense transistor 650. In this embodiment, there is no need to perform further decompression by performing sensing of the sense node 640 via the second sense path 669 (e.g., responsive to Vt of sen2) and the first sense path 649 (e.g., responsive to Vt of sen1). For example, significant delay can be eliminated by not performing the second decompression.

[0097] Figure 8A is a graph illustrating a set of histograms 802 obtained from five equally spaced boosted voltages applied to a sense node of a single path sense circuit, according to an embodiment. Figure 8A The histogram 802 shown in FIG corresponds to the Figure 7A Histogram obtained from the sensing performed.

[0098] Figure 8B is a graph illustrating a set of histograms 805 obtained from four different boosted voltages using two different sensing paths of a sensing circuit, wherein the sensing voltage gap is smaller than the threshold voltage gap, according to an embodiment. Figure 8C 8 is a graph illustrating a set of histograms 810 obtained from four different boosted voltages using two different sensing paths of a sensing circuit according to an embodiment, wherein the sensing voltage gap is greater than the threshold voltage gap. In other words, the first sensing transistor 650 and the second sensing transistor 672 ( Figure 6 ) can be fixed, but provide a threshold voltage gap for each boosted voltage level applied to the sense node 640. Therefore, the fifth boost to the sense node 640 can be eliminated.

[0099] In some embodiments, the sensing voltage gap is substantially lower than the threshold voltage gap provided by the second sensing path 669, resulting in a ratio Figure 8A The histogram generated in the histogram is narrower ( Figure 8B In other embodiments, the sensing voltage gap is actually larger than the threshold voltage gap provided by the second sensing path, resulting in a larger than Figure 8A The histogram generated in the histogram is wider ( Figure 8C ). Although the edges of these histograms may not be perfectly aligned, the local media controller 135 can still analyze the set of histograms 805 or 810 to determine the location of the local minimum between adjacent threshold voltage distributions without approximation. In some embodiments, as part of analyzing the histograms, the local media controller 135 can perform extrapolation on either the set of histograms 805 or the set of histograms 810 to fill any histogram gaps or remove overlapping histograms, respectively.

[0100] Figure 9 The diagram shows Figure 8B The histogram group 805 is Figure 8A Therefore, Figure 9 The graph shows the Figure 8A The proposed dual sensing path design of sensing circuit 600 has a wider voltage range (or increased voltage range) of four boosted levels compared to the single path sensing circuit design of five equidistant boosted voltages shown in .

[0101] Figure 10 FIG1 is a flow chart of an example method 1000 for simultaneously sensing two states of a memory cell using a sensing circuit having two sensing paths, according to some embodiments. For example, method 1000 may employ sensing circuit 600 to create and process a histogram (e.g., histogram 802 or 805) in addition to processing logic of local media controller 135. In some embodiments, a boost regulator (e.g., boost regulator 680) is located internally or externally to sensing circuit 600.

[0102] At operation 1010, a node is boosted. For example, one or more boost regulators may be selected to boost the sense node 640. More specifically, the sense node of the sense circuit is capacitively boosted to an initial voltage level, wherein the sense node is coupled to a data line of a memory array of a memory device. The sense circuit 600 may include the sense node 640 and may be located in either or both of the cache register 118 and the data register 121. For example, the memory array may be Figure 1B Memory array 104 of memory device 130 is shown in FIG.

[0103] At operation 1020, a first state of a node is determined. For example, the sensing circuit 600 may determine the first state of the sensing node. More specifically, the sensing circuit 600 determines the first state of the sensing node 640 relative to an initial voltage level using a first sensing path. The first sensing path may be Figure 6 The first sensing path 649 of the sensing circuit 600 is shown in FIG.

[0104] At operation 1030, a second state of the node is determined. For example, the sensing circuit 600 can simultaneously determine the second state of the sensing node. More specifically, the sensing circuit 600 simultaneously determines the second state of the sensing node 640 using a combination of the second sensing path relative to the initial voltage level and the threshold voltage gap provided by the second sensing path 669.

[0105] At operation 1040, a representation of the data is created. For example, processing logic (e.g., local media controller 135) may create a histogram or other representation of the data from the first state and the second state. This histogram may be Figure 8A or Figure 8B One of the individual histograms shown.

[0106] At operation 1050, the data is analyzed. For example, processing logic (e.g., local media controller 135) may optionally analyze a set of histograms including the histogram to determine a local minimum between two adjacent threshold voltage distributions within the memory cells of the memory array. Sense circuit 600 may then use the voltage level associated with the local minimum as a boosted voltage level for reading data from the memory cells, e.g., to distinguish between two logic states of adjacent threshold voltage distributions.

[0107] In some embodiments, selective slow programming convergence (SSPC) can be performed when programming memory cells, for example, where the programming rate is increased until a first program verify level is reached, and then the programming rate is slowed down until a second program verify level is reached. This SSPC method of cell programming can be used to reach a target threshold voltage level within a memory cell at a slower rate to prevent the risk of over-programming the memory cell with voltage. Thus, the disclosed embodiments can be used as a way to more quickly perform program verification of threshold voltage levels during SSPC programming, for example, to verify that a memory cell has indeed reached the first program verify level and the second program verify level during these separate phases of SSPC.

[0108] Figure 11 An example machine of a computer system 1100 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 1100 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1Amemory subsystem 110) or can be used to perform operations of the controller (for example, execute an operating system to perform operations corresponding to Figure 1A of the memory subsystem controller 115) of the host system (e.g., Figure 1A In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0109] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0110] The example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 1110 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1118, which communicate with each other via a bus 1130.

[0111] The processing device 1102 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements another instruction set, or a processor that implements a combination of instruction sets. The processing device 1102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1102 is configured to execute instructions 1128 for performing the operations and steps discussed herein. The computer system 1100 may further include a network interface device 1112 for communicating via a network 1120.

[0112] The data storage system 1118 may include a machine-readable storage medium 1124 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1128 or software embodying any one or more of the methodologies or functions described herein. The data storage system 1118 may also include the local media controller 135 and sensing circuitry 138 or sensing circuitry 600 discussed previously. During execution of the instructions 1128 by the computer system 1100, the instructions 1128 may also reside, completely or at least partially, within the main memory 1104 and / or within the processing device 1102, with the main memory 1104 and the processing device 1102 also constituting machine-readable storage media. The machine-readable storage medium 1124, the data storage system 1118, and / or the main memory 1104 may correspond to Figure 1A Memory subsystem 110.

[0113] In one embodiment, instructions 1126 include implementing instructions corresponding to a controller (e.g., Figure 1A The memory subsystem controller 115 of the present invention may be configured to store instructions for the functions of the memory subsystem controller 115. Although the machine-readable storage medium 1124 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0114] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the essence of their work to others skilled in the art. An algorithm is generally considered herein to be a self-consistent sequence of operations that leads to a desired result. Operations are those that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general purposes, it sometimes proves convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0115] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0116] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0117] The algorithms and displays presented herein are essentially independent of any particular computer or other device. Various general-purpose systems can be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform this method. The structures of various such systems will be set forth in the following description. Furthermore, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein can be implemented using a variety of programming languages.

[0118] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, or the like.

[0119] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader scope and spirit of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be read in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: memory arrays; as well as a sensing circuit coupled to the memory array, wherein the sensing circuit comprises: a sensing node coupled to a data line of the memory array; a first sensing path including a first transistor having a first gate coupled to the sensing node, the first transistor having a first threshold voltage; and A second sensing path includes a second transistor having a second gate coupled to the sensing node, wherein a first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by a threshold voltage gap.

2. The memory device of claim 1, wherein a source of each of the first transistor and the second transistor is coupled to ground. 3 . The memory device of claim 1 , wherein each of the first transistor and the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor. 4 . The memory device of claim 3 , wherein an n-channel of the second transistor comprises a different n-type implant dose than an n-channel of the first transistor, the different n-type implant dose being used to provide the threshold voltage gap.

5. The memory device of claim 1, wherein the threshold voltage gap is between 150 and 220 millivolts. 6 . The memory device of claim 1 , wherein each of the first transistor and the second transistor is a p-channel metal oxide semiconductor (PMOS) transistor. 7 . The memory device of claim 6 , wherein a p-channel of the second transistor comprises a different p-type implant dose than a p-channel of the first transistor, the different p-type implant dose being used to provide the threshold voltage gap.

8. The memory device of claim 1 , further comprising a boost regulator and a capacitor coupled between the boost regulator and the sense node, wherein: The boost regulator is used to apply a voltage boost to charge the capacitor to an initial voltage level; The first sensing path is used to determine a first state of the sensing node of the memory array relative to the initial voltage level; the second sensing path being operable to simultaneously determine a second state of the sensing node relative to a combination of the initial voltage level and the threshold voltage gap; as well as The sensing circuit is configured to create a histogram from the first state and the second state.

9. The memory device of claim 8, wherein the initial voltage level comprises a difference between the first threshold voltage and a gate-source voltage drop of the first transistor.

10. A memory device comprising: memory arrays; as well as a sensing circuit coupled to the memory array, wherein the sensing circuit comprises: a sensing node coupled to a data line of the memory array; a first sense path comprising a first transistor having a first gate coupled to the sense node, the first transistor being defined by an internal threshold voltage; a second sensing path comprising a second transistor having a second gate coupled to the sensing node, the second transistor being defined by the internal threshold voltage; and A voltage source is coupled to the source of the second transistor to shift a trip point of the second transistor by a threshold voltage gap.

11. The memory device of claim 10, wherein a source of the first transistor is coupled to ground, and the voltage source is coupled between the source of the second transistor and the ground. 12 . The memory device of claim 10 , wherein each of the first transistor and the second transistor is an n-channel metal oxide semiconductor (NMOS) transistor.

13. The memory device of claim 10, wherein the voltage source is between 150 and 220 millivolts.

14. The memory device of claim 10, wherein each of the first transistor and the second transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

15. The memory device of claim 10, further comprising a boost regulator and a capacitor coupled between the boost regulator and the sense node, wherein: The boost regulator is used to apply a voltage boost to charge the capacitor to an initial voltage level; The first sensing path is used to determine a first state of the sensing node of the memory array relative to the initial voltage level; the second sensing path being operable to simultaneously determine a second state of the sensing node relative to a combination of the initial voltage level and the threshold voltage gap; as well as The sensing circuit is configured to create a histogram from the first state and the second state.

16. The memory device of claim 15, wherein the initial voltage level comprises a difference between the threshold voltage and a gate-source voltage drop of the first transistor.

17. A method of operating a memory device, comprising: capacitively boosting a sense node of a sense circuit to an initial voltage level, wherein the sense node is coupled to a data line of a memory array of the memory device; determining a first state of the sense node relative to the initial voltage level via a first sense path of the sense circuit; concurrently determining a second state of the sense node relative to a combination of the initial voltage level and the threshold voltage gap via a second sense path of the sense circuit; as well as A histogram is created from the first state and the second state.

18. The method of claim 17, further comprising analyzing a set of histograms including the histogram to determine a local minimum between two adjacent threshold voltage distributions within memory cells of the memory array.

19. The method of claim 17, further comprising: employing a first transistor in the first sensing path; as well as A second transistor is employed in the second sensing path, wherein a first threshold voltage of the first transistor differs from a second threshold voltage of the second transistor by the threshold voltage gap.

20. The method of claim 17, further comprising: employing a first transistor in the first sensing path, the first transistor having a threshold voltage; employing a second transistor in the second sensing path, the second transistor having a threshold voltage; as well as A voltage source is coupled to a source of the second transistor to provide a different trip point for the second transistor compared to the first transistor, the different trip point corresponding to the threshold voltage gap.

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