Memory device including voltage control of a diffusion region associated with a memory block

Abstract

This application relates to memory devices including voltage control of diffusion regions associated with memory blocks. Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including a first control gate for respective first memory cells of the first memory block, a second memory block including a second control gate for respective second memory cells of the second memory block, a first diffusion region coupled to the first control gate, a second diffusion region adjacent to the first diffusion region, the second diffusion region coupled to the second control gate, and circuitry to apply a voltage to the second diffusion region in a write operation to the first memory block.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 63 / 132,728, filed December 31, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments described herein relate to memory devices that include driver circuitry associated with memory blocks of the memory device. Background Technology

[0004] Memory devices are widely used in computers and many other electronic projects. A memory device typically has numerous memory cells for storing information (e.g., data). Many conventional techniques attempt to increase the memory cell density of a memory device by vertically stacking memory cells in a stack for a given area of ​​the memory device. However, constraints in the manufacturing process limit the vertical dimensions of the memory device. Summary of the Invention

[0005] In one aspect, this application provides an apparatus comprising: a first memory block including a first control gate for a respective first memory cell of the first memory block; a second memory block including a second control gate for a respective second memory cell of the second memory block; a first diffusion region coupled to the first control gate; a second diffusion region adjacent to the first diffusion region, the second diffusion region being coupled to the second control gate; and circuitry for applying a voltage to the second diffusion region during a write operation performed on the first memory block.

[0006] In another aspect, this application provides an apparatus comprising: a first memory block including a first control gate for a respective first memory cell; a second memory block including a second control gate for a respective second memory cell; a first transistor sharing the first gate, the first transistor including a first diffusion region respectively coupled to the first control gate; a second transistor sharing a second gate, the second transistor including a second diffusion region respectively coupled to the second control gate, the second diffusion region being adjacent to the first diffusion region; circuitry for coupling the second gate to a first voltage during a time interval in a write operation storing information in the first memory cell, and decoupling the second gate from the first voltage after the time interval; and additional circuitry for coupling the first gate to a second voltage during the write operation.

[0007] In another aspect, this application provides a method comprising: performing a write operation on a memory array, the memory array including a first memory block and a second memory block, and performing the write operation comprising: selecting the first memory block to store information, the first memory block being coupled to a first diffusion region; and applying a voltage to a second diffusion region, the second diffusion region being adjacent to the first diffusion region and coupled to the second memory block.

[0008] In another aspect, this application provides a method comprising: performing a write operation on a memory array, the memory array including a first memory block and a second memory block adjacent to the first memory block, and the write operation comprising: selecting the first memory block to store information, the first memory block being associated with a first diffusion region coupled to a first control gate of a corresponding first memory cell for the first memory block; and applying a voltage to a second diffusion region adjacent to the first diffusion region, the second diffusion region being coupled to a second control gate of a corresponding second memory cell for the second memory block.

[0009] In another aspect, this application provides a method comprising: performing a write operation on a memory array, the memory array including a first memory block and a second memory block, and performing the write operation comprising: coupling a first gate to a first voltage not greater than zero, the first gate being shared by a first transistor, the first transistor being coupled to a corresponding first control gate for a corresponding first memory cell of the first memory block, the first transistor including a corresponding first diffusion region; and coupling a second gate to a second voltage greater than zero, the second gate being shared by a second transistor, the second transistor being coupled to a corresponding second control gate for a corresponding second memory cell of the second memory block, the second transistor including a corresponding second diffusion region adjacent to the first diffusion region; decoupling the second gate from the second voltage; and coupling the first gate to a first additional voltage greater than zero. Attached Figure Description

[0010] Figure 1 A block diagram illustrating a device in the form of a memory device including a memory array, memory blocks and a string driver, according to some embodiments described herein.

[0011] Figure 2 A schematic diagram illustrating a portion of a memory device comprising a memory array having memory blocks, according to some embodiments described herein.

[0012] Figure 3 Demonstrating some embodiments described herein, including memory arrays, memory blocks, block decoders, global drivers, and serial drivers. Figure 2A schematic diagram of a memory device.

[0013] Figure 4 Demonstrating some embodiments according to those described herein, including Figure 3 The connection between the string driver, a sub-block in a memory block, and the global driver. Figure 3 A schematic diagram of a memory device.

[0014] Figure 5 Demonstrates a memory block comprising a string driver according to some embodiments described herein. Figure 3 A side view (e.g., cross-section) of the structure of a portion of a memory device.

[0015] Figure 6 Demonstrates a diffusion region including a string driver according to some embodiments described herein. Figure 5 The structure of a string driver.

[0016] Figure 7 This demonstrates selective application of [something] to a portion of a write operation of a memory device according to some embodiments described herein. Figure 6 Some instance voltages in the diffusion region of the string driver.

[0017] Figure 8 This illustrates waveforms of signals associated with selected and unselected memory blocks, according to some embodiments described herein. Figure 5 and Figure 6 Instance write operations of the memory device.

[0018] Figure 9 Demonstrating some embodiments according to the description herein Figure 5 and Figure 6 Another instance of a write operation for a memory device.

[0019] Figure 10 Demonstrating some embodiments according to the description herein Figure 5 and Figure 6 Another instance of a write operation for a memory device.

[0020] Figure 11 A flowchart illustrating a method for performing a write operation in a memory device according to some embodiments described herein.

[0021] Figure 12 A flowchart illustrating another method for performing a write operation in a memory device according to some embodiments described herein.

[0022] Figure 13A flowchart illustrating another method for performing a write operation in a memory device according to some embodiments described herein.

[0023] Figure 14 The present invention illustrates a device in the form of a system including a memory device, according to some embodiments described herein. Detailed Implementation

[0024] Because the vertical dimensions used to form memory cells are constrained by the manufacturing process, it is difficult to continuously increase the memory cell density to a certain vertical dimension. The techniques described herein relate to memory devices with circuitry and memory operations that allow for a reduction in the area of ​​some of the circuitry within the memory device. This reduction in circuitry area creates more space for forming more memory cells, thereby increasing the memory cell density of the memory device compared to some conventional memory devices. The circuitry in the described techniques includes string drivers associated with memory blocks of the memory device. During memory operations on the memory blocks, different voltages can be applied to specific diffusion regions of the string drivers to counteract the potential electrical effects of adjacent elements at the reduced area. References below... Figures 1 to 14 This paper further discusses the detailed circuitry and memory operations of the techniques described herein, as well as other improvements and benefits.

[0025] Figure 1 This diagram illustrates a device in the form of a memory device 100, comprising a memory array (or multiple memory arrays) 101, memory blocks BL0 to BLKi, and other components of the memory device 100, according to some embodiments described herein. Each of the memory blocks BLK0 to BLKi may contain a memory cell 102, which may be contained within sub-blocks SB0 to SBj of the respective memory block. A sub-block is part of a memory block. In the physical structure of the memory device 100, the memory cells 102 may be arranged vertically (e.g., stacked on top of each other) on a substrate (e.g., a semiconductor substrate) of the memory device 100.

[0026] like Figure 1As shown, memory device 100 may include access lines (which may include local word lines) 150 in respective memory blocks. Memory device 100 may include data lines (which may include bit lines) 170, which may be shared among memory blocks BLK0 to BLKi. Access lines 150 may carry signals (e.g., word line signals) WL0 to WLm. Data lines 170 may carry signals (e.g., bit line signals) BL0 to BLn. Memory device 100 may use access lines 150 to selectively access memory cells 102 in the respective memory blocks BLK0 to BLKi. Memory device 100 may use data lines 170 to selectively exchange information (e.g., data) with memory cells 102 in memory blocks BLK0 to BLKi.

[0027] like Figure 1 As shown, each of the memory blocks BLK0 to BLKi may have its own access line (e.g., word line) 150, which is electrically isolated from the access lines (e.g., word lines) 150 of other memory blocks. Alternatively, two or more memory blocks BLK0 to BLKi may share access lines.

[0028] Subblocks within the same memory block can share access lines (e.g., share word lines) and can be controlled by the same access line. For example, subblocks SB0 to SBj of memory block BLK0 can share access line 150 of memory block BLK0. Subblocks SB0 to SBj of memory block BLKi can share access line 150 of memory block BLKi.

[0029] Memory device 100 may include row access circuitry 108 and column access circuitry 109 capable of decoding address information from address register 107. Based on the decoded address information, memory device 100 may determine which memory cells 102 of which sub-blocks of memory blocks BLK0 to BLKi will be accessed during memory operations.

[0030] The memory device 100 can perform write (e.g., programming) operations to store (e.g., program) information in memory cells 102 of selected memory blocks BLK0 to BLKi. The memory device 100 can perform read operations to read (e.g., sense) information (e.g., previously stored information) from selected memory cells 102 of memory blocks BLK0 to BLKi. The memory device 100 can use data lines 170 associated with signals BL0 to BLn to provide information stored in or read from selected memory blocks BLK0 to BLKi (e.g., sensed information). The memory device 100 can also perform erase operations to erase information from one or more of the memory blocks BLK0 to BLKi.

[0031] The memory device 100 may receive supply voltages, including supply voltages Vcc and Vss. The supply voltage Vss may operate at ground potential (e.g., a value of approximately zero volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC-DC converter circuitry. The memory device 100 may include a voltage generator 115 that can generate different voltages for use during memory operations (e.g., read, write, and erase operations).

[0032] like Figure 1 As shown, the row access circuitry system 108 may include a block decoder 132, a global driver (e.g., a global access line driver) 135, and a serial driver 145. The block decoder 132 is operable to decode (e.g., from address register 107) address information to determine which memory blocks BLK0 to BLKi are accessed in a memory operation (e.g., a read, write, or erase operation).

[0033] During memory operation of the memory device, global driver 135 is operable to provide voltage to serial driver 145. Serial driver 145 is operable to provide voltage to signals WL0 to WLm of the respective memory blocks BLK0 to BLKi. Depending on the operation of the memory device 200, signals WL0 to WLm may have different voltages.

[0034] like Figure 1 As shown, memory device 100 may include a control unit 118 configured to control memory operations of memory device 100 based on control signals on line 104. Examples of control signals include a chip enable signal CE#, a write enable signal WE#, and other signals. The control signals on line 104 may indicate which operation (e.g., read, write, or erase) memory device 100 may perform. Other devices external to memory device 100 (e.g., a memory controller or processor) may control the values ​​of the control signals on line 104. Specific values ​​of combinations of signals on line 104 may generate commands (e.g., read, write, or erase commands) that cause memory device 100 to perform corresponding memory operations (e.g., read, write, or erase operations).

[0035] Memory device 100 may include a sensing and buffering circuitry system 120, which may include components such as a sense amplifier and page buffer circuitry (e.g., a data latch). The sensing and buffering circuitry system 120 may respond to signals BL_SEL0 to BL_SELn from column access circuitry system 109. The sensing and buffering circuitry system 120 may be configured to determine (e.g., by sensing) the value of information read from memory cells 102 of memory blocks BLK0 to BLKi (e.g., in a read operation) and provide the value of the information to line (e.g., a global data line) 175. The sensing and buffering circuitry system 120 may also be configured to use signals on line 175 to determine the value of information to be stored (e.g., programmed) in memory cells 102 of memory blocks BLK0 to BLKi during a write operation, based on the value of signals (e.g., voltage values) on line 175 during a write operation. Memory device 100 may include a failure bit (or failure byte) counter 125 to count the bits that are considered unsuccessful in a particular write operation stored in a memory block. Memory device 100 may include an error correction code (ECC) mechanism (not shown) to correct bits considered erroneous.

[0036] Memory device 100 may include an input / output (I / O) circuitry 117 to exchange information (e.g., data, address, and instruction information) with an external device (e.g., a memory controller or processor) via lines (e.g., I / O lines) 105. Signals I / O0 to I / O are located on line 105. x This can represent information read from or stored in memory cells 102 from memory blocks BLK0 to BLKi. Lines 104 and 105 may contain nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., memory controllers or processors) may communicate with memory device 100 via lines 104 and 105.

[0037] Each of the memory cells 102 is programmable to store information representing the value of at most one bit (e.g., a single bit) or the value of multiple bits, such as two, three, four, or another number of bits. For example, each of the memory cells 102 is programmable to store information representing the binary value "0" or "1" of a single bit. A single bit per cell is sometimes referred to as a single-level cell. In another instance, each of the memory cells 102 is programmable to store information representing the value of multiple bits, such as one of the four possible values ​​of two bits "00", "01", "10", and "11", one of the eight possible values ​​of three bits "000", "001", "010", "011", "100", "101", "110", and "111", or one of other values ​​of another number of multiple bits (e.g., more than three bits per memory cell). Cells with the ability to store multiple bits are sometimes referred to as multi-level cells (or multi-state cells).

[0038] Memory device 100 may include a non-volatile memory device, and memory cell 102 may include a non-volatile memory cell, such that memory cell 102 retains information stored thereon when power supply (e.g., voltage Vcc, Vss, or both) is disconnected from memory device 100. For example, memory device 100 may be a flash memory device, such as NAND flash (e.g., 3D NAND) or NOR flash memory device, or another type of memory device, such as a variable resistance memory device (e.g., phase-change memory device or resistive random access memory (RAM) device).

[0039] Those skilled in the art will recognize that the memory device 100 may include other components, some of which are not shown. Figure 1 To avoid confusion with the exemplary embodiments described herein, at least a portion of the memory device 100 may include a structure and be configured as described below. Figures 2 to 14 The structure and operation of any of the described memory devices are similar or identical.

[0040] Figure 2 This illustration shows a portion of a memory device 200 comprising a memory array 201 having memory blocks BLK0 to BLKi and sub-blocks SB0 to SBj in each of the memory blocks, according to some embodiments described herein. The memory device 200 may correspond to... Figure 1 The memory device 100. For example, the memory array 201 may be formed Figure 1 Part of the memory array 101.

[0041] In the physical structure of memory device 200, memory blocks BLK0 to BLKi can be arranged (e.g., formed) such that one memory block is adjacent to another memory block, such that each memory block is adjacent to another memory block. Adjacent memory blocks are adjacent memory blocks located next to each other. Figure 2 The directions X, Y, and Z can be relative to the physical orientation of the structure of the memory device 200 (e.g., three-dimensional (3D) dimensions). For example, the Z direction can be a direction perpendicular to the substrate of the memory device 200 (e.g., a vertical direction relative to the substrate). The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to the XY plane of the memory device 200).

[0042] Sub-blocks SB0 to SBj within each of memory blocks BLK0 to BLKi are smaller portions of each memory block. Memory blocks BLK0 to BLKi may contain the same number of sub-blocks. For example, each of memory blocks BLK0 to BLKi may contain four sub-blocks (e.g., sub-blocks SB0, SB1, SB2, and SB3).

[0043] like Figure 3 As shown, memory device 200 may include memory cells 210 to 217 arranged in a string of memory cells. For simplicity, only string 230 of memory cells is labeled. Sub-blocks of a memory block (e.g., memory blocks BLK0 to BLKi) of memory device 200 may have the same number of strings of memory cells. As an example, Figure 2 An example is shown in which each memory cell string (e.g., memory cell string 230) contains eight memory cells 210 to 217. However, each memory cell string may contain a different number of memory cells (e.g., up to one hundred or more memory cells in a memory cell string). Figure 2 This example shows an instance where each sub-block contains three memory cell strings. However, each sub-block can contain more than three memory cell strings.

[0044] like Figure 2 As shown, the memory device 200 may include select gates (e.g., drain select gates or transistors) 260, 261, and 262 that can be controlled by corresponding select lines (e.g., drain select lines) 260', 261', and 262' and corresponding signals (e.g., drain select line signals) SGD0, SGD1, and SGD2.

[0045] Memory device 200 may include select gates (e.g., source select gates or transistors) 280, 281, and 282 that can be controlled by corresponding select lines (e.g., source select lines) 280', 281, and 282' and corresponding signals (e.g., source select line signals) SGS0, SGS1, and SGS2. Each memory cell string may be associated with (e.g., coupled to) corresponding select gates 260, 261, and 262 and corresponding select gates 280, 281, and 282.

[0046] Each sub-block (e.g., SB0 or ​​SBj) has its own memory cell string, select gates 260, 261, and 262 and associated select lines 260', 261', and 262', and select gates 280, 281, and 282. Sub-blocks within the same memory block may share select lines (e.g., source select lines) 280', 281', and 282'.

[0047] Figure 2 Each memory cell string is shown, associated with three drain select gates (e.g., select gates 260, 261, and 262) and three source select gates (e.g., select gates 280, 281, and 282). However, the number of drain select gates, the number of source select gates, or both associated with a memory cell string may be different than three.

[0048] like Figure 2 As shown, the memory device 200 may include components carrying signals BL0 to BL1 respectively. N Data cable 2700 to 270 N Data cable 2700 to 270 N Each of these can be configured as a conductive line containing a conductive material (e.g., conductive-doped polysilicon, metal, or other conductive material). The memory cell strings of memory blocks BLK0 to BLKi can share data lines 2700 to 270. N Information (in signal form) read from a memory cell carrying a selected memory cell of the memory device 200 (e.g., a selected memory cell in memory block BLK0 or BLK1) or information to be stored in the memory cell.

[0049] Memory device 200 may include a source (e.g., source line, source plate, or source region) 290 that can carry a signal (e.g., a source line signal) SL. Source 290 may be configured as a conductive line or conductive plate (e.g., a conductive region) of memory device 200. Source 290 may be a common source (e.g., a common source plate or common source region) for memory blocks BLK0 to BLKi. Alternatively, each of memory blocks BLK0 to BLKi may have its own source similar to source 290. Source 290 may be coupled to a ground connection of memory device 200.

[0050] Each of the memory blocks BLK0 to BLKi may have its own control gate group for controlling access to the corresponding memory cells of the memory cell string of the sub-blocks of the corresponding memory block. For example... Figure 2 As shown, memory device 200 may include control gates (e.g., local word lines) 220 to 227 in each of memory blocks BLK0 to BLKi.

[0051] like Figure 2 As shown, the control gates 220 to 227 of one memory block (e.g., memory block BLK0) can be electrically decoupled from the control gates 220 to 227 of another memory block (e.g., memory block BLKi). Therefore, memory blocks BLK0 to BLKi can be accessed individually (e.g., one at a time). For example, the control gates 220 to 227 of memory block BLK0 can be used to access memory block BLK0 at one time, and the control gates 220 to 227 of memory block BLKi can be used to access memory block BLKi at another time.

[0052] The memory device 200 may have the same number of control gates in memory blocks (e.g., memory blocks BLK0 to BLKi). Figure 2 In one example, memory device 200 has eight control gates 220 to 227 in each of memory blocks BLK0 to BLKi. However, the number of control gates in the memory blocks of memory device 200 (e.g., memory blocks BLK0 to BLKi) may be different from eight. For example, each of memory blocks BLK0 to BLKi may contain up to one hundred (or more) control gates.

[0053] Each of the control gates 220 to 227 may be part of a structure (e.g., a layer) of conductive material (e.g., a conductive material layer) located in a hierarchy of the memory device 200. The control gates 220 to 227 may carry corresponding signals (e.g., local word line signals) WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. The memory device 200 may use the signals WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 in the corresponding memory blocks during operation (e.g., read, write, or erase operations) to selectively control access to corresponding memory cells in the corresponding memory blocks.

[0054] For example, during a write operation, memory device 200 may use signals WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 associated with block BLK0 to control access to selected memory cells of memory block BLK0 to store information in those selected memory cells. In another example, during a read / write operation, memory device 200 may use signals WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 associated with block BLK0 to control access to selected memory cells of memory block BLK0 to read (e.g., sense) information (e.g., previously stored information) from the memory cells of memory block BLK0.

[0055] Figure 3 This illustration depicts a memory array 201 comprising memory blocks BLK0, BLK1, BLK2, and BLK3, a block decoder 332, a global driver 335, and string drivers 340, 341, 342, and 343, according to some embodiments described herein. Figure 2 A schematic diagram of the memory device 200. As an example, Figure 3 A memory device 200 is shown having four memory blocks BLK0, BLK1, BLK2, and BLK3 and four associated string drivers 340, 341, 342, and 343. However, the memory device 200 may include numerous memory blocks and associated string drivers 340, 341, 342, and 343.

[0056] Memory blocks BLK0, BLK1, BLK2, and BLK3 are adjacent to each other. For example... Figure 3 As shown, memory block BLK0 is adjacent to memory block BLK1. Memory block BLK1 is adjacent to memory block BLK2. Memory block BLK2 is adjacent to memory block BLK3. In the physical structure of memory device 200, adjacent blocks are positioned close to each other, such that there are no additional blocks (or multiple additional blocks) between adjacent blocks. Adjacent blocks may be referred to as neighboring blocks.

[0057] In the physical structure of the memory device 200, the memory array 201 (which includes memory blocks BLK0, BLK1, BLK2, and BLK3) may be located on a substrate (e.g., a semiconductor substrate) of, for example, substrate 399 (e.g., may be formed on said substrate), as schematically shown. Figure 3 The structure of substrate 399 is shown in the figure. Figure 5 In the physical structure of the memory device 200, the block decoder 332, the global driver 335, and the serial drivers 340, 341, 342, and 343 may be located in the substrate 399 (e.g., formed in or on the substrate 399) and may be located below the memory array 201.

[0058] like Figure 3 As shown, string drivers 340, 341, 342, and 343 are adjacent to each other. String drivers 340 and 341 are adjacent to each other. String drivers 341 and 342 are adjacent to each other. String drivers 342 and 343 are adjacent to each other. String drivers 340, 341, 342, and 343 can be coupled to the corresponding memory blocks BLK0, BLK1, BLK2, and BLK3 via conductive paths (e.g., conductive contacts or conductive lines) 350, 351, 352, and 353.

[0059] Each of the string drivers 340, 341, 342, and 343 may include a transistor T that can share a gate (common gate or shared gate) (e.g., gate G0, G1, G2, or G3) within the respective string driver. Gates G0, G1, G2, and G3 may receive signals (e.g., block select signals) BLK_SEL0, BLK_SEL1, BLK_SEL2, and BLK_SEL3, respectively.

[0060] Each transistor T may include a drain D and a source S. In this specification, the drain D and the source S are used interchangeably. In the structure of each transistor T, the drain D may include a diffused region (e.g., a doped region), and the source S may include another diffused region (e.g., a doped region) separate from the diffused region of the drain.

[0061] like Figure 3 As shown, the sources of the two corresponding transistors T in string drivers 340 and 341 can be shared (e.g., the sources can be electrically coupled to each other to form a shared source). Similarly, the sources of the two corresponding transistors T in string drivers 342 and 343 can be shared (e.g., the sources can be electrically coupled to each other to form a shared source). In the configuration of memory device 200, the shared source may have a single diffusion region.

[0062] like Figure 3As shown, the string drivers 340, 341, 342, and 343 may respectively include switching circuits 360, 361, 362, and 363. The switching circuits 360, 361, 362, and 363 are operable to provide signals BLK_SEL0, BLK_SEL1, BLK_SEL2, and BLK_SEL3 respectively on corresponding gates G0, G1, G2, and G3 with different voltages during memory operations (e.g., read, write, or erase operations) of the memory device 200.

[0063] The switching circuit 360 is operable to couple the gate G0 to different voltages at different times during memory operations (e.g., read, write, or erase operations) of the memory device 200. Therefore, the signal BLK_SEL1 on the gate G0 may have (e.g., may have) different voltages at different times during memory operations of the memory device 200.

[0064] Switching circuit 361 is operable to couple gate G1 to different voltages at different times during memory operations (e.g., read, write, or erase operations) of memory device 200. Therefore, the signal BLK_SEL1 on gate G1 may have (e.g., may have) different voltages at different times during memory operations of memory device 200.

[0065] Switching circuit 362 is operable to couple gate G2 to different voltages at different times during memory operations (e.g., read, write, or erase operations) of memory device 200. Therefore, the signal BLK_SEL0 on gate G2 may have (e.g., may have) different voltages at different times during memory operations of memory device 200.

[0066] Switching circuit 363 is operable to couple gate G3 to different voltages at different times during memory operations (e.g., read, write, or erase operations) of memory device 200. Therefore, the signal BLK_SEL3 on gate G3 may have (e.g., may have) different voltages at different times during memory operations of memory device 200.

[0067] Global driver 335 can be coupled to serial drivers 340, 341, 342, and 343 via conductive lines (e.g., global access lines) 336. Figure 3 As shown, conductor 336 may couple to the respective source D of the respective transistor T of string drivers 340, 341, 342, and 343. Global driver 335 is operable to provide different voltages on conductor 336 during memory operations (e.g., read, write, or erase operations) of memory device 200.

[0068] Switching circuits 360, 361, 362, and 363 can selectively turn on (e.g., activate) transistors T of string drivers 340, 341, 342, and 343 respectively based on address information from block decoder 332. Memory device 200 may include an address register (e.g., Figure 1 The address register 107 is used to provide address information to the block decoder 332. The block decoder 332 is operable to determine, based on the address information, which of the string drivers 340, 341, 342, and 343 can be activated during memory operations of the memory device 200. During memory operations of the memory device 200 (e.g., read, write, or erase operations), the turn-on transistor T of a particular string driver can transfer voltage from the corresponding conductor 336 to the corresponding memory blocks BLK0, BLK1, BLK2, and BLK3 through the corresponding conductive paths 350, 351, 352, and 353.

[0069] Figure 4 Demonstrating some embodiments according to those described herein, including Figure 3 The connection between the serial driver 340, the sub-block SB0 of memory block BLK1, and the global driver 335. Figure 3 A schematic diagram of the memory device 200. Figure 4 In the memory block BLK1, sub-block SB and associated elements (e.g., memory cells 210 to 217 and select gates 260, 261, 262, 281, 282 and 283, signals BL and SL) are... Figure 2 The sub-blocks and associated elements shown are identical. Therefore, their descriptions are not repeated.

[0070] like Figure 4 As shown, conductor 336 may carry corresponding signals (e.g., global drain select line signals) GSGD0, GSGD1, and GSGD2, signals (e.g., global access line signals) GWL0 to GWL7, and signals (e.g., global source line signals) GSGS0, GSGS1, and GSGS2. These signals can be selectively activated (e.g., switched on) by string drivers 340, 341, 342, and 343. Figure 3 ) and selectively provide memory blocks (e.g., memory blocks BLK0, BLK1, BLK2 and BLK3) to memory device 200.

[0071] like Figure 4 As shown, the source and drain of each transistor T can be coupled to a corresponding conductive line in conductive line 336 and a corresponding conductive path in conductive path 351 (e.g., coupled between the corresponding conductive line and the corresponding conductive path). For simplicity, in Figure 4 The source (S) and drain (D) of a single transistor T are marked in the diagram.

[0072] Other memory blocks and string drivers of memory device 200 (e.g., Figure 3 (in China) can have similar Figure 4 The connection between memory block BLK1 and serial driver 341. For example, as Figure 4 As shown, the string driver 342 can be coupled to the global driver 335 and the memory block BLK2 in a connection similar to that of the string driver 341.

[0073] Figure 5 This document illustrates, according to some embodiments described herein, memory blocks BLK0, BLK1, BLK2, and BLK3 associated with string drivers 340, 341, 342, and 343. Figure 3 A side view (e.g., cross-section) of a portion of the structure of the memory device 200. Figure 5 As shown, memory blocks BLK0, BLK1, BLK2, and BLK3 of memory array 201 may be located (e.g., formed on) substrate 399. Substrate 399 may contain a semiconductor material. For example, substrate 399 may contain monocrystalline silicon (also referred to as single-crystal silicon). The monocrystalline semiconductor material of substrate 399 may contain impurities, such that substrate 399 may have a specific conductivity type (e.g., n-type or p-type). Source 290 may be formed on (or in) substrate 399. Source 290 may contain a conductive material (or multiple conductive materials). For example, source 290 may contain conductive-doped polycrystalline silicon, a metal, or a combination of both, or other conductive materials.

[0074] like Figure 5 As shown, the memory device 200 may include different layers 501 to 514 in the Z direction. Memory cells 210 to 217 of memory blocks BLK0, BLK1, BLK2, and BLK3 may be formed (e.g., vertically in the Z direction) on the substrate 399 in corresponding layers (e.g., layers 504 to 511). Memory cells 210 to 217 of corresponding memory cell strings (e.g., memory cell string 230) may be positioned along different portions of the pillars 550 of the corresponding memory cell string. Figure 5 As shown, each post 550 may extend in the Z direction (e.g., vertically). Each post 550 of a corresponding memory cell string may be a portion of a conductive path (e.g., a current path) passing through the corresponding memory cell string between the data line 2700 and the source 290. Figure 5 As shown, data line 2700 can be shared among sub-blocks SB0, SB1, SB2 and SB3 of memory blocks BLK0, BLK1, BLK2 and BLK3.

[0075] like Figure 5As shown, memory blocks BLK0, BLK1, BLK2, and BLK3 are four adjacent memory blocks located close to each other (e.g., four adjacent memory blocks). For example, memory blocks BLK0 and BLK1 are adjacent memory blocks. Memory blocks BLK1 and BLK2 are adjacent memory blocks. Memory blocks BLK2 and BLK3 are adjacent memory blocks. Memory blocks BLK0, BLK1, BLK2, and BLK3 have separate control gates for the respective memory cells of the respective memory blocks.

[0076] like Figure 5 As shown, sub-blocks SB0, SB1, SB2 and SB3 of the corresponding memory block may share the same control gate (e.g., control gates 220 to 227) of the corresponding memory block (e.g., may be controlled by the same control gate). Figure 5 The example shown illustrates an instance where each of memory blocks BLK0, BLK1, BLK2, and BLK3 contains four sub-blocks SB0, SB1, SB2, and SB3. However, the number of sub-blocks may differ from four.

[0077] The control gates 220 to 227 (associated with signals WL0 to WL7) in the same block may be located on different layers (e.g., layers 504 to 511) in the Z direction of the memory device 200 (e.g., they may be stacked on top of each other). The control gates 220 to 227 may comprise a conductive material (or multiple conductive materials). Examples of materials used for the control gates 220 to 227 include conductive-doped polysilicon, metal, or other conductive materials. Figure 5 As shown, the memory device 200 may include dielectric material (e.g., silicon dioxide) 521 located at different levels in the Z direction. The dielectric material 521 in the respective blocks is interleaved with the control gates 220 to 227 in the respective blocks.

[0078] The selection lines (e.g., three drain selection lines) associated with the corresponding signals SGD0, SGD1, and SGD2 of the sub-blocks within the same block (e.g., block BLK0) may comprise corresponding conductive regions (e.g., three conductive regions) formed in different layers (e.g., layers 512, 513, and 514) in the Z-direction. Each of the conductive regions may have a length in the Y-direction (perpendicular to the X-direction). Figure 5 As shown, each sub-block may have its own drain select line (associated with corresponding signals SGD0, SGD1, and SGD2), which is electrically isolated from the drain select lines (associated with corresponding signals SGD0, SGD1, and SGD2) of the other sub-block. The drain select line may contain a conductive material, which may be the same as (or different from) the material of the control gates 220 to 227. Figure 5As shown, the select gates 260, 261 and 262 of the respective sub-blocks may include the corresponding portions of the drain select lines of the respective sub-blocks.

[0079] The selection lines (e.g., three source selection lines) associated with the corresponding signals SGS0, SGS1, and SGS2 of the sub-blocks within the same block (e.g., block BLK0) may contain corresponding conductive regions (e.g., three conductive regions) formed in different layers (e.g., layers 501, 502, and 503) in the Z direction. Each of the conductive regions may have a length in the Y direction (perpendicular to the X direction). Figure 5 As shown, sub-blocks within the same memory block can share source select lines (associated with corresponding signals SGS0, SGS1, and SGS2). The source select lines may contain a conductive material, which may be the same as (or different from) the material of the control gates 220 to 227. Figure 5 As shown, the select gates 280, 281 and 282 of the respective sub-blocks may include the corresponding portions of the source select lines of the respective sub-blocks.

[0080] like Figure 5 As shown, string drivers 340, 341, 342, and 343 may be located in substrate 399 beneath corresponding memory blocks BLK0, BLK1, BLK2, and BLK3. Conductive paths 350, 351, 352, and 353 coupled between the corresponding memory blocks and the corresponding string drivers correspond to... Figure 3 The same conductive paths are shown. For simplicity, Figure 5 Only some of conductive paths 350, 351, 352, and 353 are shown. Each of conductive paths 350, 351, 352, and 353 may contain a conductive material (e.g., a metal (e.g., tungsten)). At least a portion of the conductive material in each conductive path 350, 351, 352, and 353 may be formed in the Z direction (e.g., vertically).

[0081] exist Figure 5 In the diagram, the signal SGD on the corresponding conductive paths 350, 351, 352, and 353 can represent the individual signals SGD0, SGD1, and SGD2 on the corresponding drain select line of the corresponding memory block. Similarly, the signal SGS on the corresponding conductive paths 350, 351, 352, and 353 can represent the individual signals SGS0, SGS1, and SGS2 on the corresponding source select line of the corresponding memory block.

[0082] Figure 6 Demonstrating some embodiments including diffusion regions according to the embodiments described herein Figure 5 The structure of a portion of the string drivers 340, 341, 342, and 343. For example... Figure 6As shown, string drivers 340, 341, 342, and 343 may include corresponding diffusion regions D0, S01, D1, D2, S23, and D3. These diffusion regions may be formed from individual portions of the substrate 399. String drivers 340, 341, 342, and 343 may include corresponding gates G0, G1, G2, and G3 disposed above the corresponding diffusion regions D0, S01, D1, D2, S23, and D3.

[0083] like Figure 6 As shown, each of the string drivers 340, 341, 342, and 343 may occupy a region having a width 602 in the Y direction (e.g., a region in substrate 399). The width 602 is the same for string drivers 340, 341, 342, and 343. The width 602 may correspond to the width (e.g., the spacing in the Y direction in the XY plane) of each memory block in the memory device 200 (e.g., memory blocks BLK0, BLK1, BLK2, and BLK3). Figure 6 As shown, the memory device 200 may have a region (with width A1) that does not contain the diffusion regions of the drivers 341 and 342.

[0084] like Figure 6 As shown, diffusion regions D0, D1, D2, D3, S01, and S23 are individual portions of the material (e.g., semiconductor material) in the substrate 399 that is doped with impurities (e.g., doped with n-type or p-type dopants). Therefore, diffusion regions D0, D1, D2, D3, S01, and S23 can also be referred to as doped regions.

[0085] The conductivity types of diffusion regions D0, D1, D2, D3, S01, and S23 are different from the conductivity type of substrate 399. For example, substrate 399 may contain p-type semiconductor material, and each of diffusion regions D0, D1, D2, D3, S01, and S23 may contain n-type semiconductor material.

[0086] like Figure 6 As shown, diffusion region S01 is adjacent to diffusion regions D0 and D1 and lies between diffusion regions D1 and D2. Diffusion region S23 is adjacent to diffusion regions D2 and D3 and lies between diffusion regions D2 and D3. Diffusion region D1 is adjacent to diffusion region D2.

[0087] Each diffusion region S01 and adjacent diffusion regions D0 or D1 may form an active region of a corresponding transistor T (e.g., an n-channel metal-oxide-semiconductor (NMOS) transistor) in the substrate 399. For example, when an appropriate voltage is applied to the gate G0, the active region containing the diffusion region S01 and the adjacent diffusion region D0 may form a channel (e.g., a transistor channel) to conduct current between the diffusion region S01 and the adjacent diffusion region D0. In another example, when an appropriate voltage is applied to the gate G1, the active region containing the diffusion region S01 and the adjacent diffusion region D1 may form a channel (e.g., a transistor channel) to conduct current between the diffusion region S01 and the adjacent diffusion region D1.

[0088] Similarly, each diffusion region S23 and the adjacent diffusion region D2 or D3 can form an active region (e.g., the active region of the corresponding transistor T) in the substrate 399. For example, when an appropriate voltage is applied to the gate G2, the active region containing the diffusion region S23 and the adjacent diffusion region D2 can form a channel (e.g., a transistor channel) to conduct current between the diffusion region S23 and the adjacent diffusion region D2. In another example, when an appropriate voltage is applied to the gate G3, the active region containing the diffusion region S23 and the adjacent diffusion region D3 can form a channel (e.g., a transistor channel) to conduct current between the diffusion region S23 and the adjacent diffusion region D3.

[0089] The diffusion regions D0, S01, D1, D2, S23, and D3 can be portions of the corresponding drain and source terminals of transistor T in string drivers 340, 341, 342, and 343. For example, the diffusion region D0 can be a portion of the corresponding transistor T in string driver 340. Figure 3 The corresponding drain portion of ). The diffusion region D1 can be the corresponding transistor T of the string driver 341. Figure 3 The corresponding drain portion of ). The diffusion region D2 can be the corresponding transistor T of the string driver 342. Figure 3 The corresponding drain portion of ). The diffusion region D3 can be the corresponding transistor T of the string driver 343. Figure 3 The corresponding drain portion of ). The diffusion region S01 can be the corresponding transistor T of the string drivers 340 and 341. Figure 3 The corresponding shared source S portion of ). The diffusion region S23 can be the corresponding transistor T of the string drivers 342 and 343. Figure 3 The corresponding shared source pole S portion of ).

[0090] Therefore, the transistor T( of the string driver 340) Figure 6(Not marked in the text) may contain a diffusion region D0 and a neighboring diffusion region S01. The transistor T of the string driver 341 may contain a diffusion region D1 and a neighboring diffusion region S01. The transistor T of the string driver 342 may contain a diffusion region D2 and a neighboring diffusion region S23. The transistor T of the string driver 343 may contain a diffusion region D3 and a neighboring diffusion region S23.

[0091] Each of the gates G0, G1, G2, and G3 may contain a conductive material (e.g., a metal) and may extend in length in the X direction. Figure 6 As shown, the gate G0 may be located above the diffusion regions D0 and S01 (e.g., the location of the transistor channel of the corresponding transistor T). The gate G0 may be separated from the diffusion regions D0 and S01 (in the Z direction) by a dielectric material (e.g., gate oxide (e.g., silicon dioxide)).

[0092] The gate G1 may be located above the diffusion regions S01 and D1 (e.g., the location of the transistor channel of the corresponding transistor T). The gate G1 may be separated from the diffusion regions S01 and D1 (in the Z direction) by a dielectric material (e.g., gate oxide (e.g., silicon dioxide)).

[0093] The gate G2 may be located above the diffusion regions D2 and S23 (e.g., the location of the transistor channel of the corresponding transistor T). The gate G2 may be separated from the diffusion regions D2 and S23 (in the Z direction) by a dielectric material (e.g., gate oxide (e.g., silicon dioxide)).

[0094] The gate G3 may be located above the diffusion regions S23 and D3 (e.g., the location of the transistor channel of the corresponding transistor T). The gate G3 may be separated from the diffusion regions S23 and D3 (in the Z direction) by a dielectric material (e.g., gate oxide (e.g., silicon dioxide)).

[0095] like Figure 6 As shown, each of the conductive lines 336 (associated with signals GWL0 to GWL7) can be coupled to (e.g., accessible to) a corresponding diffusion region S01 and a corresponding diffusion region S23. Figure 6 In this context, the control gates (unlabeled) of the corresponding memory blocks BLK0, BLK1, BLK2, or BLK3 are associated with signals WL0 to WL7 of the corresponding memory blocks. Therefore, as... Figure 6As shown, diffusion region D0 is coupled to (e.g., accessible) the corresponding second control gate of memory block BLK0 (associated with signals WL0 to WL7) (electrically in contact with said corresponding second control gate). Diffusion region D1 is coupled to (e.g., accessible) the corresponding second control gate of memory block BLK1 (associated with signals WL0 to WL7) (electrically in contact with said corresponding second control gate). Diffusion region D2 is coupled to (e.g., accessible) the corresponding second control gate of memory block BLK2 (associated with signals WL0 to WL7) (electrically in contact with said corresponding second control gate). Diffusion region D3 is coupled to (e.g., accessible) the corresponding second control gate of memory block BLK3 (associated with signals WL0 to WL7) (electrically in contact with said corresponding second control gate).

[0096] For simplicity, Figure 6 The other diffusion regions of the string drivers 340, 341, 342, and 343 and the other conductive lines of the global driver 335 coupled to other components, such as the corresponding drain selection lines (e.g., with...), are omitted. Figure 4 The selection lines associated with signals SGD0, SGD1, and SGD2 in the signal selection line and the source selection lines (e.g., with the source selection lines associated with the source selection lines) ... are also mentioned. Figure 4 (Selection lines associated with signals SGS0, SGS1, and SGS2 in the signal).

[0097] exist Figure 6 In this process, voltages can be selectively applied to diffusion regions D0, D1, D2, and D3 by selectively turning on the transistors T of the respective string drivers during memory operations (e.g., read, write, or erase operations). For example, diffusion region D1 can be energized by applying voltage to diffusion region S01 and also to gate G1. In another example, diffusion region D2 can be energized by applying voltage to diffusion region S23 and also to gate G2.

[0098] The connection (e.g., electrical contact) between the diffusion region of a particular memory block and the corresponding control gate (associated with one of the signals WL0 to WL7) allows the voltage applied to the diffusion region to be transferred (also applied) to the corresponding control gate of the particular memory block.

[0099] Figure 7 This demonstrates selective application of diffusion regions D1, D2, S01, and S23 (in the portion of a write operation performed on memory block BLK1 according to some embodiments described herein) to the portion of the write operation performed on memory block BLK1. Figure 6 The instance voltage (marked in the middle) Figure 6 The structure of parts of the string drivers 340, 341, 342 and 343. Figure 7The write operation assumes that memory block BLK1 is selected by memory device 200 to store information in the selected sub-block SB0. Figure 2 and Figure 4 The selected memory cell 212 () Figure 2 and Figure 4 The memory blocks in the memory. In this example, memory cells 210, 211, and 213 to 217 are not selected (unselected) for storing information. Therefore, in this example, the control gate 222 (and) Figure 2 , Figure 4 , Figure 5 and Figure 6 The selected control gate (associated with signal WL2) is the control gate associated with the selected memory cell (e.g., memory cell 212 in this example) of the selected memory block (e.g., memory block BLK1 in this example). Other control gates 220, 222, and 223 to 227 (associated with...) Figure 2 , Figure 4 , Figure 5 and Figure 6 The corresponding signals WL0, WL1 and WL3 to WL7 are associated with the control gates that are not selected (e.g., deselected), which are the control gates associated with the unselected memory cells (e.g., memory cells 210, 211 and 213 to 217 in this example).

[0100] The following description describes a portion (not the complete write operation) of the write operation to illustrate an example of applying a portion of the voltage to the corresponding diffusion regions D1, D2, S01, and S23 of the respective string drivers 340, 341, 342, and 343. Reference Figures 8 to 13 Describe other write operations in detail.

[0101] like Figure 7 As shown in Figure 7, a voltage Vpgm (e.g., programming voltage or write voltage) can be applied to the diffusion region S01 (in Figure 6 (Note: The text appears to be incomplete and contains errors. A more accurate translation would require the full context.) The voltage Vpgm can have a relatively high value (e.g., 14V to 24V) to allow information to be stored in the selected memory cell of memory block BLK1 (the selected memory block). The voltage Vpgm_sw can be applied to gate G1 to turn on (e.g., activate) transistor T of string driver 341. The voltage Vpgm_sw can have a value greater than voltage Vpgm (e.g., 28V). This is to allow voltage Vpgm from diffusion region S01 to be passed to diffusion region D1 (associated with signal WL2) associated with the selected control gate (associated with signal WL2) of the selected memory block (in this example, memory block BLK1). Figure 6(Note: The text appears to be incomplete and contains errors. A possible interpretation is:) A voltage Vpass may be applied to other diffusion regions of the string driver 341 associated with the unselected (e.g., deselected) control gates of memory block BLK1 (e.g., control gates associated with signals WL0, WL1, and WL3 to WL7). The voltage Vpass may have a value less than the voltage Vpgm (e.g., 10V). This is to prevent information from being stored in unselected memory cells of memory block BLK1 and to allow unselected memory cells in the same memory cell string to operate as selected memory cells of memory block BLK1 as pass gates (e.g., turn-on transistors).

[0102] like Figure 7 As shown, voltage Vx can also be applied to diffusion region D2 (in Figure 6 (marked in the middle), the diffusion region D2 is the diffusion region associated with the unselected memory block BLK2. Voltage Vx may have a value relatively smaller than the values ​​of voltage Vpass and voltage Vpgm (e.g., 2V to 4V). In this specification (e.g., Figure 7 The voltage values ​​described in the diagrams (and other diagrams) are example values. Other voltage values ​​may be used.

[0103] Applying a voltage Vx to the diffusion region associated with an unselected memory block (e.g., memory block BLK2 in this example) allows memory device 200 to have improvements and benefits compared to some conventional memory devices, as discussed below.

[0104] like Figure 6 and Figure 7 As shown, diffusion region D2 is adjacent to diffusion region D1. During a write operation, if voltage Vx is not applied to diffusion region D2 (e.g., if diffusion region D2 remains at 0V), the voltage difference between diffusion regions D1 and D2 can be relatively high. This high voltage difference (between diffusion regions D1 and D2) can approach the value of voltage Vpgm. This high voltage difference can cause interference between adjacent control gates (associated with signal WL) coupled to the respective diffusion regions D1 and D2. This can degrade the performance of memory device 200. Figure 7 The applied voltage Vx shown reduces the relative voltage difference. This reduces interference, thereby improving the operation of the memory device 200.

[0105] In addition, such as Figure 7 The applied voltage Vx shown can also provide other improvements and benefits. For example, because voltage Vx can be applied to diffusion region D2 to reduce the relatively high voltage difference, diffusion regions D1 and D2 can be placed closer to each other (e.g., formed). For example, in Figure 6In this configuration, diffusion regions D1 and D2 can be placed closer to each other, allowing the area with width A1 to be reduced (e.g., shrunk). This area reduction creates additional space (e.g., more space in the XY direction) for other components of the memory device 200. For example, the resulting additional space can be used to form more memory cells (in the XY direction). This increases the memory cell density of the memory device 200.

[0106] Figure 8 The diagram illustrates waveforms of signals associated with selected memory blocks (e.g., memory block BLK1) and unselected memory blocks (e.g., memory block BLK2) according to some embodiments described herein. Figure 5 and Figure 6 Instance write operations of memory device 200. For example... Figure 8 As shown, a write operation that stores information in a selected memory cell of memory block BLK1 may include different phases (e.g., different operations) between time T0 and T12. These phases include charging (e.g., pre-charging) phases 810, 813, 816, and 819, writing phases 811, 814, 817, and 820, and verification (write verification) phases 812, 815, 818, and 821. (Example shown) Figure 8 The charging, writing, and verification phases in the process can be as follows: Figure 8 As shown, they proceed sequentially.

[0107] Figure 8 An example is shown of four charge phases, four write phases, and four verification phases performed by the memory device 200 during a write operation. However, the memory device 200 may perform a different number of charge, write, and verification phases. Additionally, as described below, some of the charge phases may be skipped (e.g., not performed).

[0108] exist Figure 8 In the middle, time T0 to T12 indicates the time interval between T0 and T12. Figure 8 Different times (points in time) during associated write operations. Time T0 occurs before time T1, time T1 occurs before time T2, and so on. The memory device 200 may begin a write operation at time T0 and end a write operation at time T12.

[0109] In Figure 8 In the associated instance write operation, it is assumed that memory block BLK1 is the selected memory block in which information is stored in the selected memory cells of memory block BLK1. Memory block BLK2 and other memory blocks (e.g., memory blocks BLK1 and BLK3) are unselected memory blocks.

[0110] Figure 8The signals BLK_SEL1, WL0, WL1, WL3 to WL7 and WL2 associated with memory block BLK1, and the signals BLK_SEL2 and WL0 to WL7 associated with memory block BLK2 are shown in the diagram. Figure 5 and Figure 6 The signals are the same.

[0111] exist Figure 8 In, with Figure 8 The voltages (e.g., voltage levels) associated with the signals in the signal array Vpgm_sw, Vpass_sw, Vpass, Vseed, Vpgm, Vsw1, and V1 are also applied to the signal. Figure 6 The voltages of the corresponding diffusion regions (e.g., diffusion regions S01, S23, D1 and D2) and gates G1 and G2. Figure 8 The voltage in the memory blocks BLK1 and BLK2 is also related to signals WL0 to WL7. Figure 5 The voltage on the corresponding control gate associated with ). Figure 8 In the associated write operation, global drive 335 ( Figure 3 and Figure 4 It is operable to apply different voltages to conductor 336. (Associated with...) Figure 8 The voltages associated with signals WL0 to WL7 in memory blocks BLK1 and BLK2 are based on those of serial drivers 341 and 342. Figure 3 , Figure 4 and Figure 5 Conductive lines 336 (transmitted to the corresponding diffusion regions D1 and D2) Figure 3 and Figure 4 The voltage on ).

[0112] like Figure 8 As shown, the memory device 200 can begin a write operation during a charging phase 810 (e.g., between time T0 and T1). During the charging phase 810, the signal BLK_SEL2 may have a voltage Vsw1 to turn on the serial driver 342 ( Figure 6 A transistor T is used to apply a voltage V1 to the diffusion region D2 associated with signals WL0 to WL7 of memory block BLK2. Voltage Vsw1 may have a value of 5V (or approximately 5V). Voltage V1 may have a value in the range of 2V to 4V. As mentioned above, the voltage values ​​described in this specification are example values. Other voltage values ​​may be used.

[0113] exist Figure 8In this process, the memory device 200 may perform a write phase 811 after the charging phase 810 (e.g., between time T1 and T2). The write phase 811 may be performed to store information in a selected memory cell of the memory block BLK1 (the selected memory block). For example, the write phase 811 may be performed to move the state of the selected memory cell (e.g., threshold voltage) toward a corresponding target state (e.g., target threshold voltage). During the write phase 811, the signal BLK_SEL1 may have voltages Vpass_sw and Vpgm_sw to activate the serial driver 341 (…). Figure 6 The transistor T is associated with memory block BLK1. Signals WL0 to WL7 may have corresponding voltages Vseed, Vpass, and Vpgm, which are the voltages applied to diffusion region D1 during write phase 811. Voltage Vseed may be less than the supply voltage of memory device 200 (e.g., Vcc). For example, Vseed may have a value of 2V (or approximately 2V). Voltage Vpass may have a value of 10V (or approximately 10V). Voltage Vpass_sw may have a value of 28V (or approximately 28V).

[0114] Therefore, as described above and as... Figure 8 As shown, signals WL0 to WL7 associated with the unselected memory block BLK2 may have a voltage V1, while signals associated with the selected memory block BLK1 remain at 0V (e.g., may be coupled to ground). This indicates that voltage V1 may be applied to diffusion region D2 (associated with the unselected memory block BLK2) before applying a voltage (e.g., Vseed, Vpass, or Vpass_sw) to diffusion region D1 associated with the selected memory block BLK1.

[0115] The memory device 200 may perform a verification phase 812 to determine whether the selected memory cell has reached the corresponding target state. If the memory device 200 determines, based on the result from the verification phase 812, that the selected memory cell has reached the corresponding target state, then... Figure 8 Write operations in the instance can end after verification phase 812.

[0116] If memory device 200 determines that fewer than all selected memory cells have reached the corresponding target state, then memory device 200 may repeat the charging phase, writing phase, and verification phase (e.g., after time T3). Figure 8 The repeated stages may include charging stages 813, 816, and 819, writing stages 814, 817, and 820, and verification stages 815, 818, and 821. For example... Figure 8As shown, memory device 200 can apply the same voltages Vsw1 and V1 to the corresponding signals BLK_SEL2 and WL0 to WL7. However, during each repeated write phase, the voltage Vpgm on signal WL2 associated with the selected memory block BLK1 can be increased (e.g., sequentially). For example, Figure 8 The voltage Vpgm is shown to have a step-up pattern during the repeated write phases between times T3 and T12. The voltage Vpgm can be provided by a pulse (e.g., a programming pulse) 888. Figure 8 As shown, pulse 888 can have different voltage values ​​(e.g., different amplitudes) during each repeated write phase. Figure 8 The associated instance write operation may end after time T12, at which time the selected memory cell is considered to have reached the corresponding target state.

[0117] Some charging phases in a write operation of the memory device 200 can be skipped (e.g., not performed) based on conditions (e.g., predetermined criteria) configured in the memory device 200 (e.g., set in the memory device 200). For example, the memory device 200 may keep track of (e.g., store) the number of pulses (e.g., pulse 888) used in the write phase. In this example, if the number of pulses 888 is not greater than a limit (e.g., a predetermined number of pulses), then the charging phase (e.g., one of charging phases 813, 816, and 819) can be skipped (e.g., not performed). In this example, if the number of pulses 888 is greater than the limit, then the charging phase is not skipped (e.g., performed). The limit can be selected based on the characteristics of the memory device 200 and can be a programmable (e.g., fine-tunable) value. The limit can be stored in the memory device 200. For example, the control unit of the memory device 200 (e.g., Figure 1 The control unit 118 may include registers to store limit values. If the charging phase is skipped, the memory device 200 may continue in the next write phase after the previous verification phase.

[0118] In alternative write operations, the conditions for skipping the charging phase can be based on the value of voltage Vpgm and a limit value. For example, the control unit of memory device 200 (such as...) Figure 1The control unit 118 may include registers to store voltage values ​​(e.g., predetermined values) for a limit. The stored limit value may be selected based on characteristics of the memory device 200 and may be a programmable (e.g., fine-tunable) value. In this example, if the voltage Vpgm used in a particular write phase is not greater than a limit (e.g., a predetermined value for voltage Vpgm), then a charging phase (e.g., one of charging phases 813, 816, and 819) may be skipped. In this example, if the voltage Vpgm is greater than a limit, then the charging phase is not skipped (e.g., is performed). If the charging phase is skipped, then the memory device 200 may continue in the next write phase after the previous verification phase.

[0119] The operation is as described above. Figure 8 The described write operation (e.g., applying voltage V1 to diffusion region D2 associated with memory block BLK2 (the unselected memory block) allows memory device 200 to have the above-referenced features. Figure 7 The improvements and benefits discussed.

[0120] Figure 9 Demonstrating some embodiments according to the description herein Figure 5 and Figure 6 Another instance of a write operation on a memory device. Memory device 200 can be configured to perform write operations with... Figure 8 Associated write operations or with Figure 9 Any of the associated write operations. For simplicity, not repeated. Figure 8 and Figure 9 Similar or identical elements between them. Figure 9 In, similar to Figure 8 For example, suppose memory block BLK1 is the selected memory block in which information is stored in the selected memory cells of memory block BLK1. Memory block BLK2 and other memory blocks (e.g., memory blocks BLK1 and BLK3) are unselected memory blocks.

[0121] like Figure 9 As shown, a write operation that stores information in a selected memory cell of memory block BLK1 may include different phases (e.g., different operations) between time T20 and T30. The phases include several instance write phases 910, 912, 914 and 916, and verification phases 911, 913, 915 and 917.

[0122] exist Figure 9 In this example, the signal BLK_SEL2 may have a voltage Vsw2 to turn on the serial driver 342 ( Figure 6 Transistor T is used to apply voltage V2 to the diffusion region D2 associated with signals WL0 to WL7 of memory block BLK2. Figure 9 As shown, after applying voltage Vseed to the diffusion region D1 associated with signal WL2 in memory block BLK1 during the write phase (e.g., write phases 910, 912, 914 and 916), signal BLK_SEL2 can be activated during the write phase (e.g., voltage Vsw2 may be present).

[0123] Will Figure 9 The voltage V2 applied to the diffusion region (e.g., diffusion region D2 in this example) associated with an unselected memory block (e.g., memory block BLK2) in the structure of the string drivers 340, 341, 342, and 343 of the memory device 200 can be referred to above. Figure 7 The improvements and benefits discussed.

[0124] The memory device 200 may perform a verification phase (e.g., verification phases 911, 913, 915, and 917) after each write phase. The memory device 200 may repeat the write and verification phases as needed. Figure 9 As shown, pulse 999 can have different voltage values ​​(e.g., different amplitudes) during each repeated write phase. Figure 9 The associated instance write operation may end after time T30, at which time the selected memory cell reaches the corresponding target state.

[0125] The memory device 200 may skip applying voltage V2 to the diffusion region D2 based on some conditions configured in the memory device 200. These conditions may be used for... Figure 8 The conditions are the same. For example, if the number of pulses 999 is not greater than the pulse count limit or if the voltage Vpgm is not greater than the voltage limit, then the memory device 200 may skip applying voltage V2. Write operations are performed in the memory device 200 (similar to...). Figure 9 (Related instances) can be compared to Figure 8 The associated write operations further improve the performance of the memory device 200 (e.g., reduce programming time).

[0126] The operation is as described above. Figure 9 The described write operation (e.g., applying voltage V2 to diffusion region D2 associated with memory block BLK2 (unselected memory block) allows memory device 200 to have the above-referenced features. Figure 7 The improvements and benefits discussed.

[0127] Figure 10 Demonstrating some embodiments according to the description herein Figure 5 and Figure 6 Another instance of a write operation on a memory device. (Compared to...) Figure 10The associated instance write operation can be Figure 9 A variant of the instance write operation. The memory device 200 can be configured to perform write operations with... Figure 8 , Figure 9 or Figure 10 Any of the associated write operations. For simplicity, not repeated. Figure 9 and Figure 10 Similar or identical elements between them.

[0128] like Figure 10 As shown, a write operation that stores information in a selected memory cell of memory block BLK1 may include different phases (e.g., different operations) between time T20 and T30. These phases include several instance write phases 910', 912', 914', and 916', and verification phases 911', 913', 915', and 917', which may be similar to... Figure 9 The text describes several write phases (910, 912, 914, and 916) and verification phases (911, 913, 915, and 917). It also mentions... (The sentence is incomplete and requires further context to translate accurately.) Figure 9 and Figure 10 The difference between associated write operations is contained in Figure 10 The voltages applied between time T20B and T21 to the diffusion regions D1 and D2 associated with signals WL0 to WL7 of memory blocks BLK1 and BLK2.

[0129] like Figure 10 As shown, signal BLK_SEL2 can apply voltage Vsw3 between times T20B and T21 to turn on serial driver 342. Figure 6 Transistor T is used to apply voltage V3 to the diffusion region D2 associated with signals WL0 to WL7 of memory block BLK2. Between times T20B and T21, signal BLK_SEL1 may be supplied with voltage Vpass_sw to turn on serial driver 341. Figure 6 A transistor T is used to apply voltage V3' to the diffusion region D1 associated with signals WL0 to WL7 of memory block BLK1. The value of voltage V3' may be equal to (or approximately equal to) the value of voltage V3. Voltages V3 and V3' may be equal to (or approximately equal to) the supply voltage (e.g., Vcc) of memory device 200. A write operation is performed in memory device 200 (similar to...). Figure 10 (Associated examples) can avoid or reduce potential current leakage between the control gates associated with signals WL0 to WL7 that are coupled to the diffusion regions D1 and D2 of memory block BLK2.

[0130] The operation is as described above. Figure 10The described write operation (e.g., applying voltage V3 to diffusion region D2 associated with memory block BLK2 (the unselected memory block) allows memory device 200 to have the above-mentioned references. Figure 7 The improvements and benefits discussed.

[0131] Figure 11 This is a flowchart illustrating a method 1100 for performing a write operation in a memory device according to some embodiments described herein. Method 1100 may be included in the memory device (e.g., a control unit of the memory device, such as...). Figure 1 The algorithm portion of the control unit 118). Method 1100 can be performed by software, firmware, hardware (e.g., logic circuitry system), or any combination of software, firmware, and hardware. The software, firmware, and hardware may be configured (e.g., may be contained in a memory device).

[0132] Method 1100 may include performing a write operation to store information in a selected memory cell of a selected memory cell block within a memory cell block of a memory array of a memory device. The memory device used in method 1100 may include memory devices (e.g., memory devices 100, 200, and 1420). Figure 14 )).like Figure 11 As shown, method 1100 may include activities (e.g., operations) 1105, 1110, 1115, 1120, 1125, 1130, 1135, 1140, and 1145.

[0133] Method 1100 may initiate a memory operation at activity 1105, which may include selecting a memory block to store information (e.g., data) in a write operation. The selected memory block in method 1100 may be memory device 200. Figures 2 to 10 ) memory block BLK1.

[0134] Activity 1110 may include operating on a neighboring memory block, which is an unselected memory block adjacent to the selected memory block. The neighboring memory block in method 1100 may be memory device 200 (…). Figures 2 to 10 The memory block BLK2 is an adjacent memory block. The operation in activity 1110 may include applying a voltage to a diffusion region (e.g., diffusion region D2) associated with the adjacent memory block. The voltage applied in activity 1110 may include voltages V1, V2, or V3 (respectively...). Figure 8 , Figure 9 and Figure 10 ).

[0135] Activity 1115 may include a write phase (e.g., a programming phase) to store information in the selected memory block. The write phase may include... Figure 8 , Figure 9 or Figure 10 The write phase in activity 1115 may include applying a programming voltage (e.g., voltage Vpgm) to the selected control gate of the selected memory block. The programming voltage may be provided by a pulse (e.g., a programming pulse). The pulse in activity 1115 may include pulses 888, 999, or 1010 (respectively). Figure 8 , Figure 9 and Figure 10 The information stored in the memory cell may correspond to the state of the memory cell. Activity 1115 may cause the selected memory cell to have a corresponding state. The state in the memory cell may correspond to the threshold voltage of the memory cell. Each memory cell in the memory device used in method 1100 may store at most one bit per cell or multiple bits per cell. Therefore, the state of the memory cell in the memory device of method 1100 may represent the value of a single bit of information (e.g., a binary value) or the value of multiple bits.

[0136] Activity 1120 of method 1100 may include counting the number of pulses used in activity 1115. The number of pulses used in activity 1115 may correspond to the above reference. Figure 8 , Figure 9 and Figure 10 The number of pulses 888, 999, or 1010 described.

[0137] Activity 1125 may include a verification phase (e.g., a programming verification phase) for performing a write operation. The verification phase may include determining whether the selected memory cell has reached its corresponding target state. The target state is the state corresponding to a value of information stored in the selected memory cell. The verification operation may include comparing the state of the selected memory cell (e.g., a threshold voltage) with its corresponding target state (e.g., a target threshold voltage).

[0138] Activity 1130 may include determining whether all selected memory cells have reached their target state. The "No" flag at activity 1130 indicates that less than all (not all) of the selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1100 may continue with activity 1140. The "Yes" flag at activity 1135 indicates that all selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1100 may continue with activity 1135.

[0139] Activity 1140 may include a value that increases the programming voltage. For example, activity 1140 may increase the voltage (e.g., amplitude) of the pulse (e.g., pulse 888, 999, or 1010) used in activity 1115.

[0140] Activity 1145 may include determining whether the number of pulses (e.g., pulses 888, 999, or 1010) used in activity 1115 is greater than (exceeds) a limit (e.g., a counting limit). For example, activity 1145 may compare the number of pulses counted in activity 1120 with a limit. The limit described herein may be a preset limit (e.g., a predetermined value), which may be an adjustable value and may be stored (e.g., programmable) in a memory device. For example, a control unit of the memory device (such as...) Figure 1 The control unit 118 may include a register to store the value of the limit (e.g., a predetermined count value).

[0141] The "Yes" flag at activity 1145 indicates that the number of pulses (in activity 1115) is greater than a limit (exceeds the limit). In this case, method 1100 may perform a repeating sequence (e.g., repeating a loop) in response to the result from activity 1130 to repeat some or all of activities 1110, 1115, 1120, 1125, 1130, 1140, and 1145 at least once more. The "No" flag at activity 1145 indicates that the number of pulses (in activity 1115) is not greater than a limit (does not exceed the limit). In this case, method 1100 may skip activity 1110 and perform activities 1115, 1120, 1125, and 1130, and then repeat some or all of activities 1110, 1115, 1120, 1125, 1130, 1140, and 1145 at least once more in response to the result from activity 1130.

[0142] If all selected memory cells are considered to have reached their respective target states, then activity 1135 may include an end (complete) write operation.

[0143] Method 1100 can provide a similar reference to the one above. Figures 2 to 10 The improvements and benefits of the described memory device 200.

[0144] Figure 12 This is a flowchart illustrating a method 1200 for performing a write operation in a memory device according to some embodiments described herein. Method 1200 may be included in the memory device (e.g., a control unit of the memory device, such as...). Figure 1 The algorithm portion of the control unit 118). Method 1200 can be performed by software, firmware, hardware (e.g., logic circuitry), or any combination of software, firmware, and hardware. The software, firmware, and hardware may be configured in (e.g., contained in) a memory device.

[0145] Method 1200 may include performing a write operation to store information in a selected memory cell of a selected memory cell block within a memory cell block of a memory array of a memory device. The memory device used in method 1200 may include memory devices (e.g., memory devices 100, 200, and 1420). Figure 14 )).like Figure 12 As shown, method 1200 may include activities (e.g., operations) 1205, 1210, 1215, 1220, 1225, 1230, 1235, 1240, and 1245.

[0146] Method 1200 may initiate a memory operation at activity 1205, which may include selecting a memory block to store information (e.g., data) in a write operation. The selected memory block in method 1200 may be memory device 200. Figures 2 to 10 ) memory block BLK1.

[0147] Activity 1210 may include determining the programming voltage (e.g., the write phase in activity 1120) for a phase. Figure 8 , Figure 9 and Figure 10 Whether the voltage (Vpgm) in the circuit is greater than (exceeds) a limit (e.g., a voltage limit). For example, activity 1210 can compare the value of the programmed voltage with the limit. The limit described herein may be a preset limit (e.g., a predetermined value), which may be an adjustable value and may be stored (e.g., programmable) in a memory device. For example, the control unit of the memory device (such as...) Figure 1 The control unit 118 may include a register to store the value of a limit (e.g., a predetermined voltage value).

[0148] The "No" mark at activity 1210 indicates that the programming voltage value is not greater than the limit (not exceeding the limit). In this case, method 1200 can skip activity 1215 and proceed to activity 1220. The "Yes" mark at activity 1210 indicates that the programming voltage value is greater than the limit (exceeding the limit). In this case, method 1200 can continue with activity 1215.

[0149] Activity 1215 may include operating on a neighboring memory block, which is an unselected memory block adjacent to the selected memory block. The neighboring memory block in method 1200 may be memory device 200 (…). Figures 2 to 10 The operation in activity 1215 may include applying a voltage to a diffusion region (e.g., diffusion region D2) associated with the adjacent memory block BLK2. The voltage applied in activity 1215 may include voltages V1, V2, or V3 (respectively). Figure 8 , Figure 9 and Figure 10 ).

[0150] Activity 1220 may include a write phase (e.g., a programming phase) to store information in the selected memory block. The write phase may include... Figure 8 , Figure 9 or Figure 10 The write phase in activity 1220 may include applying a programming voltage (e.g., voltage Vpgm) to the selected control gate of the selected memory block. The programming voltage may be provided by a pulse (e.g., a programming pulse). The pulse in activity 1220 may include pulses 888, 999, or 1010 (respectively). Figure 8 , Figure 9 and Figure 10 Activity 1220 can cause the selected memory cell to have a corresponding state. Therefore, the state of the memory cell of the memory device in method 1200 can represent the value of a single bit (e.g., a binary value) or the value of multiple bits of information.

[0151] Activity 1225 of method 1200 may include storing (e.g., updating) the value of the programming voltage in activity 1220. The value may be the latest value of the programming voltage in activity 1220.

[0152] Activity 1230 may include a verification phase for performing a write operation (e.g., a programming verification phase). The verification phase may include determining whether the selected memory cell has reached its corresponding target state. The verification operation may include comparing the state of the selected memory cell (e.g., a threshold voltage) with its corresponding target state (e.g., a target threshold voltage).

[0153] Activity 1235 may include determining whether all selected memory cells have reached their target state. A "No" flag at activity 1235 indicates that less than all (not all) of the selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1200 may continue with activity 1245. A "Yes" flag at activity 1235 indicates that all selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1200 may continue with activity 1240.

[0154] Activity 1245 may contain a value that increases the programming voltage. For example, activity 1245 may increase the voltage (e.g., amplitude) of the pulses (e.g., pulses 888, 999, or 1010) used in activity 1220.

[0155] After performing activity 1245, method 1200 may perform a repeating sequence (e.g., repeating loop) in response to the result from activity 1135 to repeat some or all of activities 1210, 1215, 1220, 1225, 1230, 1235 and 1240 at least once more.

[0156] If all selected memory cells are considered to have reached their respective target states, then activity 1240 may include an end (complete) write operation.

[0157] Method 1200 may include the references above. Figures 2 to 10 Other activities and operations of the described memory device 200.

[0158] Method 1200 can provide a similar reference to the one above. Figures 2 to 10 The improvements and benefits of the described memory device 200.

[0159] Figure 13 This is a flowchart illustrating a method 1300 for performing a write operation in a memory device according to some embodiments described herein. Method 1300 may be included in the memory device (e.g., a control unit of the memory device, such as...). Figure 1 The algorithm portion of the control unit 118). Method 1300 can be performed by software, firmware, hardware (e.g., logic circuitry), or any combination of software, firmware, and hardware. The software, firmware, and hardware may be configured (e.g., may be contained in a memory device).

[0160] Method 1300 may include performing a write operation to store information in a selected memory cell of a selected memory cell block within a memory cell block of a memory array of a memory device. The memory device used in method 1300 may include memory devices (e.g., memory devices 100, 200, and 1420). Figure 14 )).like Figure 13 As shown, method 1300 may include activities (e.g., operations) 1305, 1310, 1315, 1320, 1325, 1330, 1335, 1340, 1345, 1350 and 1355.

[0161] Method 1300 may initiate a memory operation at activity 1305, which may include selecting a memory block to store information (e.g., data) in a write operation. The selected memory block in method 1300 may be memory device 200. Figures 2 to 10 ) memory block BLK1.

[0162] Activity 1310 may include a write phase (e.g., a programming phase) to store information in the selected memory block. The write phase in activity 1310 may include applying a programming voltage (e.g., voltage Vpgm) to a selected control gate of the selected memory block. The programming voltage may be provided by a pulse (e.g., a programming pulse). Each memory cell in the memory device for method 1300 may store up to one bit per cell or multiple bits per cell. Therefore, the state of a memory cell in the memory device of method 1300 may represent the value of a single bit (e.g., a binary value) or the value of multiple bits of information.

[0163] Activity 1315 may include a verification phase for performing a write operation (e.g., a programming verification phase). The verification phase may include determining whether the selected memory cell has reached its corresponding target state. The target state is the state corresponding to a value of information stored in the selected memory cell. The verification operation may include comparing the state of the selected memory cell (e.g., a threshold voltage) with its corresponding target state (e.g., a target threshold voltage).

[0164] Activity 1320 of method 1300 may include storing (e.g., updating) a failure count. The failure count may contain bits having a corresponding value (e.g., threshold voltage) that is different from the target state (e.g., target threshold voltage).

[0165] Activity 1325 may include determining whether all selected memory cells have reached their target state. A "No" flag at activity 1325 indicates that fewer than all (not all) of the selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1300 may continue with activity 1335. A "Yes" flag at activity 1325 indicates that all selected memory cells have reached (or are considered to have reached) their target state. In this case, method 1300 may continue with activity 1330.

[0166] Activity 1330 may include a write operation completed in a qualified state.

[0167] Activity 1335 may include determining whether the last programming pulse has been used in activity 1315. A "No" flag at activity 1335 indicates that the last programming pulse has not been used. In this case, method 1300 may continue with activity 1140. A "Yes" flag at activity 1335 indicates that the last programming pulse has been used. In this case, method 1300 may continue with activity 1345.

[0168] Activity 1345 may include determining whether the failure count (stored in activity 1320) is less than (and does not exceed) a limit (e.g., a failure count limit). For example, activity 1345 may compare the value of the failure count in activity 1320 with the limit. The limit described herein may be a preset limit (e.g., a predetermined value), which may be an adjustable value and may be stored (e.g., programmable) in a memory device. For example, a control unit of the memory device (such as...) Figure 1 The control unit 118 may include registers to store the value of a limit (e.g., a predetermined count value). The value of the limit may be selected based on the memory device's ability to correct error bits (e.g., failure bits). For example, the memory device may correct information with up to M error bits, and then the failure count may be set to M (M bits).

[0169] The "Yes" flag at activity 1345 indicates (in activity 1320) that the failure count is less than a limit (e.g., less than M). In this case, method 1300 can proceed to activity 1350 to complete the write operation in a qualified state. After activity 1350, method 1300 can perform error correction (not shown) to correct bits that have values ​​different from the target value (e.g., failure bits).

[0170] The "No" flag at activity 1345 indicates that the failure count is not less than a limit (e.g., not less than M). In this case, method 1300 can proceed to activity 1355 to complete the write operation in a failed state.

[0171] Activity 1340 may include a value that increases the programming voltage. For example, activity 1340 may increase the voltage (e.g., amplitude) of the pulse used to provide the programming voltage.

[0172] After performing activity 1340, method 1300 may perform a repeating sequence (e.g., repeating loop) in response to the result from activity 1325 to repeat some of activities 1310, 1315, 1320, 1325, 1325, 1330, 1335, 1345, 1350 and 1355 at least once more.

[0173] Method 1300 may include the above references. Figures 2 to 10 Other activities and operations of the described memory device 200.

[0174] Figure 14 This document illustrates a device in the form of a system (e.g., an electronic system) 1400 according to some embodiments described herein. Part or all of system 1400 may include, or be included in, a system-on-a-chip, a system-on-package, a solid-state drive (SSD), a mobile phone, a tablet computer, a computer, an electronic module in an automobile, or other types of electronic systems. Figure 14As shown, system 1400 may include processor 1410, memory device 1420, memory controller 1430, graphics controller 1440, I / O controller 1450, display 1452, keyboard 1454, pointing device 1456, at least one antenna 1458, connector 1415, and bus 1460 (e.g., conductive lines formed on a circuit board (not shown) of system 1400).

[0175] In some arrangements, system 1400 need not include a display. Therefore, display 1452 can be omitted from system 1400. In some arrangements, system 1400 need not include any antenna. Therefore, antenna 1458 can be omitted from system 1400.

[0176] Each of the processor 1410, memory device 1420, memory controller 1430, graphics controller 1440, and I / O controller 1450 may contain a die portion and may be an IC package portion.

[0177] Processor 1410 may include a general-purpose processor or an application-specific integrated circuit (ASIC). Processor 1410 may include a central processing unit (CPU).

[0178] The memory device 1420 may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device (e.g., a NAND flash memory device), a phase-change memory, a combination of these memory devices, or other types of memory.

[0179] In this example, memory device 1420 may include the above-mentioned reference. Figures 1 to 13 The memory device 100 or 200 described herein. Therefore, memory device 1420 may include the information referenced above. Figures 1 to 13 The described memory device (e.g., memory device 100 or 200) has a structure and memory operations (e.g., write operations). Figure 14 In this context, processor 1410 or memory controller 1430 may communicate with memory device 1420 to enable memory device 1420 to perform the above-mentioned reference. Figures 1 to 13 The memory operations described herein. For example, processor 1410 or memory controller 1430 may send instructions (e.g., commands in the form of signals) to memory device 1420 to cause memory device 1420 to perform write, read, or erase operations. A write operation may include the above references. Figures 1 to 13 Any of the write operations described.

[0180] Display 1452 may include a liquid crystal display (LCD), a touch screen (e.g., a capacitive or resistive touch screen), or another type of display. Pointing device 1456 may include a mouse, a stylus, or another type of pointing device.

[0181] The I / O controller 1450 may include a communication module for wired or wireless communication (e.g., communication via one or more antennas 1458). Such wireless communication may include communication based on WiFi communication technology, LTE-A communication technology, or other communication technologies.

[0182] The I / O controller 1450 may also include modules for enabling the system 1400 to communicate with other devices or systems in accordance with one or more of the following standards or specifications (e.g., I / O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect High Speed ​​(PCIe), Ethernet, and other specifications.

[0183] Connector 1415 may be arranged (e.g., may include terminals, such as pins) to allow system 1400 to couple to an external device (or system). This allows system 1400 to communicate (e.g., exchange information) with such device (or system) via connector 1415. Connector 1415 may be coupled to I / O controller 1450 via connection 1416 (e.g., bus).

[0184] At least a portion of connector 1415, connection 1416 and bus 1460 may include elements (e.g., conductive terminals, conductive wires or other conductive elements) that conform to at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet and other specifications.

[0185] Figure 14 The components (e.g., devices and controllers) of system 1400 are arranged separately from each other as examples. In some arrangements, two or more components of system 1400 may be located in the same IC package, the same subsystem, or the same device. For example, memory device 1420 and memory controller 1430 may be included in the same SSD or the same memory subsystem of system 1400.

[0186] The description of the apparatus (e.g., memory devices 100, 200, and 1420) and methods (e.g., methods of operating apparatus 100, 200, and 1420) is intended to provide a general understanding of the structure of the various embodiments and is not intended to provide a complete description of all elements and features of an apparatus that may utilize the structure described herein. As used herein, "apparatus" refers to a device (e.g., any one of memory devices 100, 200, and 1420) or a system (e.g., a computer, cellular phone, or other electronic system) that includes a device such as any one of memory devices 100, 200, and 1420.

[0187] The above references Figures 1 to 14 Any of the components described may be implemented in several ways, including via software simulation. Therefore, a portion of any device (e.g., memory devices 100, 200, and 1420) or any of the memory devices described above may be characterized herein as a “module” (or a plurality of “modules”). Such a module may include hardware circuitry, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof, as required and / or appropriate for a particular implementation of the various embodiments. For example, such a module may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitor-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of various potential embodiments.

[0188] Memory devices 100, 200, and 1420 may be included in devices (e.g., electronic circuit systems), such as high-speed computers, communication and signal processing circuit systems, single-processor or multi-processor modules, single or multiple embedded processors, multi-core processors, message switches, and dedicated modules, including multi-layer, multi-chip modules. Such devices may be further included as sub-components within various other devices (e.g., electronic systems) (e.g., televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, set-top boxes, etc.).

[0189] The above references Figures 1 to 14The described embodiments include an apparatus and a method of forming said apparatus. One of the apparatuses includes: a first memory block including a first control gate for a respective first memory cell of the first memory block; a second memory block including a second control gate for a respective second memory cell of the second memory block; a first diffusion region coupled to the first control gate; a second diffusion region adjacent to the first diffusion region, the second diffusion region being coupled to the second control gate; and circuitry for applying a voltage to the second diffusion region during a write operation performed on the first memory block. Other embodiments including additional apparatus and methods are described.

[0190] In the detailed description and claims, the terms "on" or "one on" another, used in relation to two or more elements (e.g., materials), imply at least some contact between the elements (e.g., between materials). The term "above" implies that the elements (e.g., materials) are very close together, but may have one or more additional intervening elements (e.g., materials) that make contact possible but not necessary. Neither "on" nor "above" implies any directionality as used herein unless stated otherwise.

[0191] In the detailed description and claims, the terms “first,” “second,” and “third,” etc., are used only as illustrative marks and are not intended to impose numerical requirements on their objects.

[0192] In the detailed description and claims, the list of items joined by the term "at least one of" can mean any combination of the listed items. For example, if items A and B are listed, then the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, then the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0193] In the detailed description and claims, a list of items joined by the term "one of" can mean only one of the listed items. For example, if items A and B are listed, then the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another instance, if items A, B, and C are listed, then the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0194] The foregoing description and figures illustrate some embodiments of the subject matter of this invention to enable those skilled in the art to practice these embodiments. Other embodiments may have structural, logical, electrical, technological, and other variations. The examples represent only possible variations. Parts and features of some embodiments may be included in or replace those parts and features of other embodiments. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description.

Claims

1. An apparatus comprising: A first memory block, which includes first word lines for corresponding first memory cells; The second memory block includes second word lines for corresponding second memory cells; A first transistor, which shares a first gate, and the first transistor includes first diffusion regions respectively coupled to the first word line; A second transistor, which shares a second gate, includes a second diffusion region coupled to the second word line, the second diffusion region being adjacent to the first diffusion region; A circuit for coupling the second gate to a first voltage during a time interval in a write operation that stores information in the first memory cell, and decoupling the second gate from the first voltage after the time interval. as well as Additional circuitry for coupling the first gate to a second voltage during the write operation, wherein the circuitry is configured to couple the second gate to the first voltage prior to coupling the first gate to the second voltage.

2. The device according to claim 1, further comprising: The third diffusion region is adjacent to the first diffusion region; as well as The fourth diffusion region is adjacent to the second diffusion region.

3. The device according to claim 2, further comprising: The first conductive line is coupled to the corresponding diffusion region of the third diffusion region and the corresponding diffusion region of the fourth diffusion region.

4. The device according to claim 1, wherein the first diffusion region and the second diffusion region are made of the same material.

5. The device of claim 1, wherein the first memory block is adjacent to the second memory block.

6. The device according to claim 1, further comprising: The third memory block contains third word lines for the corresponding third memory cells; A third transistor, sharing a third gate, the third transistor including third diffusion regions respectively coupled to the third word line; and The third transistor shares the corresponding diffusion region with the first transistor.

7. The device according to claim 6, further comprising: A fourth memory block, which includes a fourth word line for a corresponding fourth memory cell; A fourth transistor, sharing a fourth gate, the fourth transistor including a fourth diffusion region respectively coupled to the fourth word line; and The fourth transistor shares the corresponding diffusion region with the second transistor.

8. A method comprising: A write operation is performed on a memory array, the memory array comprising a first memory block and a second memory block, and the write operation comprises: The first memory block is selected to store information, and the first memory block is coupled to the first diffusion region; and A voltage is applied to a second diffusion region, which is adjacent to the first diffusion region and coupled to the second memory block. The write operation includes: A first additional voltage is applied to a third diffusion region adjacent to the second diffusion region; When applying the voltage to the second diffusion region, avoid applying a second additional voltage to the fourth diffusion region, which is adjacent to the third diffusion region; and The third diffusion region is located between the second diffusion region and the fourth diffusion region.

9. The method of claim 8, wherein performing the write operation comprises: During the write phase of the write operation, an additional voltage is applied to the first diffusion region; Stop applying the voltage to the second diffusion region; Verify whether the selected memory cell in the first memory block has reached the corresponding target state; as well as After verifying whether the selected memory cell in the first memory block has reached the corresponding target state, the step of applying the voltage to the second diffusion region is repeated.

10. The method of claim 8, wherein the voltage applied to the second diffusion region has a range from two volts to four volts.

11. A method comprising: A write operation is performed on a memory array, the memory array comprising a first memory block and a second memory block, and the write operation comprises: The first memory block is selected to store information, and the first memory block is coupled to the first diffusion region; and A voltage is applied to a second diffusion region, which is adjacent to the first diffusion region and coupled to the second memory block. The write operation includes: After the voltage is applied to the second diffusion region, additional voltages are applied to at least one of the first diffusion regions.

12. The method of claim 11, further comprising: When the additional voltage is applied to at least one of the first diffusion regions, the application of the voltage to the second diffusion region is stopped.

13. The method of claim 11, wherein the additional voltage applied to at least one of the first diffusion regions is greater than the voltage applied to the second diffusion region.

14. A method comprising: A write operation is performed on a memory array, the memory array comprising a first memory block and a second memory block, and the write operation comprises: The first memory block is selected to store information, and the first memory block is coupled to the first diffusion region; and A voltage is applied to a second diffusion region, which is adjacent to the first diffusion region and coupled to the second memory block. The write operation includes: Before applying the voltage to the second diffusion region, an additional voltage is applied to at least one of the first diffusion regions.

15. The method of claim 14, wherein the additional voltage applied to the at least one of the first diffusion regions is less than the voltage applied to the second diffusion region.

16. A method comprising: A write operation is performed on a memory array, the memory array comprising a first memory block and a second memory block adjacent to the first memory block, and the write operation comprises: The first memory block is selected to store information, and the first memory block is associated with a first diffusion region coupled to a corresponding first word line of a corresponding first memory cell for the first memory block; as well as A voltage is applied to a second diffusion region adjacent to the first diffusion region, and the second diffusion region is coupled to a corresponding second word line of a corresponding second memory cell for the second memory block. The write operation includes: Before or after the voltage is applied to the second diffusion region, an additional voltage is applied to at least one of the first diffusion regions.

17. The method of claim 16, wherein one of the additional voltages comprises a programming voltage.

18. The method of claim 16, wherein performing the write operation comprises: Stop applying the voltage to the second diffusion region; Verify whether the selected memory cell in the first memory block has reached the corresponding target state; and After verifying whether the selected memory cell in the first memory block has reached the corresponding target state, the step of applying the voltage to the second diffusion region is repeated.

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