Etching method for forming a semiconductor device structure and semiconductor device structure

Abstract

The application discloses an etching method for forming a semiconductor device structure and the semiconductor device structure, and relates to the technical field of semiconductor device structures. The etching method comprises the following steps: providing a substrate, wherein the substrate is provided with a to-be-etched layer, the to-be-etched layer is provided with a patterned pattern layer, and the thickness ratio of the to-be-etched layer to the pattern layer is greater than 5; a first gas is introduced into the surface of the pattern layer, wherein the first gas comprises H2 and CHyFz (0<=y<=3, 0<z<=4), and the flow ratio of CHyFz to H2 is 3:1-1:3; the first gas reacts with the top of the pattern layer to form a hardening layer; after the formation of the hardening layer, the pattern layer and the hardening layer are used as masks, a second gas is introduced, the to-be-etched layer is etched, and the top surface of the substrate is exposed until a groove is formed in the to-be-etched layer. The application protects the pattern layer by the hardening layer, improves the selectivity ratio of the to-be-etched layer to the pattern layer, ensures that the mask can effectively mask during deep etching, and meets the etching requirements.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an etching method for forming a semiconductor device structure and a semiconductor device structure. Background Art

[0002] Under the continuous promotion of Moore's Law, the technology node of semiconductors has rapidly advanced to nodes below 10 nm. Generally, in the manufacture of integrated circuit semiconductor devices, a predetermined material structure needs to be formed on a substrate. The formation of the predetermined material structure includes depositing an etch layer on the substrate and providing a patterned graphic layer on the etch layer as a mask. The plasma etching process is one of the important technical links restricting its development. Among them, using photoresist (PR) as a mask to etch materials such as polysilicon, silicon dioxide, and silicon nitride (SiN) below to form complementary metal oxide semiconductor (CMOS), via, or trench structures is one of the important steps.

[0003] When the thickness of the etch layer is very thick and the upper mask is relatively thin, the etching process requires a very high selectivity to the mask. Some mask materials, especially photoresist, have too low selectivity during etching and cannot effectively mask during etching, failing to meet the etching requirements. Summary of the Invention

[0004] In view of the situation where the material to be etched is thick and the upper mask is relatively thin, the present invention provides a method for improving the etching selectivity to the mask to accurately transfer the pattern.

[0005] To achieve the above object, the present invention provides an etching method for forming a semiconductor device structure, which includes: providing a substrate, on which an etch layer is provided, and a patterned graphic layer is provided on the etch layer, and the thickness ratio of the etch layer to the graphic layer is greater than 5; introducing a first gas onto the surface of the graphic layer, the first gas including: H2 and CHyFz, 0 ≤ y ≤ 3, 0 < z ≤ 4; the flow ratio of CHyFz to H2 is 3:1 to 1:3; the first gas reacts with the top of the graphic layer to form a hardening layer; after forming the hardening layer, using the graphic layer and the hardening layer as a mask, introducing a second gas to etch the etch layer until the top surface of the substrate is exposed, and forming a groove in the etch layer.

[0006] Optionally, CHyFz is selected from at least one of tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), or CH3F.

[0007] Optionally, CHyFz is selected from CF4, wherein the gas flow ratio of CF4 to H2 is 2:1 to 1:2.

[0008] Optionally, the first gas further includes at least one of C1 to C5 hydrocarbon small molecule gases.

[0009] Optionally, the hydrocarbon small molecule gas is selected from at least one of CH4, C2H6, or C2H4.

[0010] Optionally, the first gas further includes an inert gas.

[0011] Optionally, the flow rate of the inert gas is 100 sccm to 500 sccm.

[0012] Optionally, the second gas includes: a fluorine-containing gas and O2.

[0013] Optionally, the fluorine-containing gas includes at least one of the following: nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8), or octafluoroisobutene (C4F8), or fluorine (F2) and C4F6.

[0014] Optionally, the second gas further includes an inert gas.

[0015] Optionally, the inert gas includes argon or helium.

[0016] Optionally, the patterned layer is a photoresist layer.

[0017] Optionally, the material of the layer to be etched includes silicon dioxide, silicon nitride, or polycrystalline silicon.

[0018] Optionally, the process conditions for forming the hardened layer include: a pressure of 40mT to 60mT, a radio frequency of 60MHz, 900W to 1200W, and / or 2MHz, 200W to 2500W.

[0019] The present invention also provides a semiconductor device structure formed by the above method, comprising: a substrate having an etchable layer thereon, the etchable layer having a patterned pattern layer thereon; a hardening layer located on the top surface of the pattern layer; and a groove located within the etchable layer and between adjacent pattern layers, exposing the top surface of the substrate.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention introduces a first gas into the surface of the patterned pattern layer to form a hardened layer on top of the pattern layer. Using the pattern layer and the hardened layer as a mask, when etching is performed by introducing a second gas, the hardened layer increases the selectivity of the layer to be etched to the pattern layer. This ensures that when the thickness ratio of the layer to be etched to the thickness of the pattern layer is greater than 5, the mask can effectively cover the surface and meet the etching requirements. Attached Figure Description

[0022] Figure 1 This is a flowchart of the etching method for forming a semiconductor device structure according to the present invention.

[0023] Figure 2 This is a schematic diagram of the etched structure.

[0024] Figure 3 This is a schematic diagram of the hardening layer formed on the PR surface.

[0025] Figure 4 Different etching modes achieved with different CF4 / H2 gas ratios.

[0026] Figure 5 The result diagram shows the effect of further adjusting the PR processing technology. Detailed Implementation

[0027] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "top," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] like Figure 1 As shown, the etching method for forming semiconductor device structures provided by the present invention includes the following steps:

[0030] Step S1: Provide a substrate, on which an etchable layer is provided, and on which a patterned graphic layer is provided, wherein the thickness ratio of the etchable layer to the graphic layer is greater than 5.

[0031] Step S2: Introduce a first gas onto the surface of the pattern layer. The first gas includes H2 and CHyFz, where 0 ≤ y ≤ 3 and 0 < z ≤ 4; the flow rate ratio of CHyFz to H2 is 3:1 to 1:3. The first gas reacts with the top of the pattern layer to form a hardened layer.

[0032] Step S3: After forming the hardened layer, use the pattern layer and the hardened layer as masks, introduce a second gas, and etch the to-be-etched layer until the top surface of the substrate is exposed, forming a groove in the to-be-etched layer.

[0033] After introducing a gas combination including H2 and CHyFz in the present invention, hydrogen, carbon, and fluorine are prone to generate hydrocarbon fluoride polymers (polymers). The polymers are deposited on the surface of the pattern layer to form a hardened layer. Using the pattern layer and the hardened layer as masks, and then introducing a second gas for etching, the hardened layer is utilized to slow down or block the etching of the pattern layer by the plasma, thus improving the etch selectivity of the to-be-etched layer to the upper mask. When the thickness ratio of the to-be-etched layer to the pattern layer is greater than 5, the upper mask will not be completely etched, and a predetermined material structure can be obtained after the etching is completed.

[0034] CHyFz can be at least one of tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), or CH3F. The flow rate ratio of CHyFz to H₂ is 3:1 to 1:3. If the ratio of CHyFz to H₂ is too large, the hardened layer is too thin or difficult to form, and the protection effect on the pattern layer is very small or non-existent; if the ratio is too small, that is, the H content increases, it is a very big challenge for the upper electrode material because the more H there is, the damage to the electrode is a process from quantitative change to qualitative change. When CHyFz selects CF4, in one embodiment, the gas flow ratio of CF4 to H₂ is 2:1 to 1:2.

[0035] In some embodiments, the pattern layer is a photoresist layer. Photoresist is one of the key materials for microfabrication in microelectronics technology. The coated photoresist can form a photoresist pattern through exposure and use the photoresist pattern as an etching mask to etch the material into a predetermined material structure. The etching resistance of the photoresist is poor, and the etch selectivity between the photoresist layer and the to-be-etched layer can be effectively improved by the method of the present invention. In some embodiments, the first gas further includes at least one of C1 - C5 hydrocarbon small molecule gases. In some embodiments, the hydrocarbon small molecule gas selects CH4, C2H6, or C2H4. The hydrocarbon small molecule gas can be used as a deposition gas to provide hydrocarbon free radicals to help form polymer deposition, thereby increasing the polymer content on the PR surface and improving the etch selectivity of the to-be-etched layer to the PR.

[0036] The first gas also includes inert gases, such as argon (Ar) or helium (He). Inert gases serve two main purposes: firstly, they act as diluents, adjusting the concentration of the main gas. Adding an appropriate amount of inert gas can enhance plasma bombardment; too little gas results in weak plasma bombardment. Inert gases also help to ensure uniform distribution of polymer deposition. Adding too much inert gas will excessively dilute the concentration of the main gas, leading to less polymer formation. Argon generates Ar ions, which are directional and can promote faster polymer deposition in small-sized structures.

[0037] In some embodiments, the second gas includes a fluorine-containing gas and O2. When etching materials such as SiO2, the fluorine-containing gas can provide an fluorine source for etching, while O2 can accelerate the etching rate. After a hardened layer is formed on top of the patterned layer, the introduced second gas can quickly etch the layer to be etched. The hardened layer protects the patterned layer, preventing deviations in the device structure due to pattern loss. In some embodiments, the fluorine-containing gas includes at least one of nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8), or octafluoroisobutylene (C4F8), or fluorine (F2).

[0038] In some embodiments, the second gas further includes an inert gas, such as argon (Ar) or helium (He).

[0039] Alternatively, other suitable gases can be used for etching the layer to be etched. For example, some gas combinations that can form a small amount of deposits can continuously replenish the loss of the upper mask and continuously etch the lower layer to be etched during the etching process.

[0040] The etching method of the present invention can be plasma etching and applied in a plasma etching process cavity. Inductively coupled plasma (ICP) can be selected, but it is not limited to capacitively coupled plasma (CCP).

[0041] When forming device structures such as Complementary Metal Oxide Semiconductor (CMOS), the material under the mask can be polysilicon, silicon dioxide, or silicon nitride (SiN).

[0042] like Figure 2As shown in (A), a semiconductor device structure includes an etch stop layer 10, an oxide layer 20, and a photoresist layer 30 disposed sequentially. A substrate and a dielectric layer may be disposed below the etch stop layer 10.

[0043] The etch stop layer 10 can be a single layer or multiple layers, and can be made of silicon oxide, silicon carbide (SiC), silicon nitride, silicon carbonitride (SiCN), silicon carbide (SiOC), silicon carbide nitride (SiOCN), or other suitable materials. The oxide layer 20 serves as a dielectric layer, and its structure can be a single layer or multiple layers, such as a single layer of silicon oxide, a double layer of silicon oxide / silicon nitride, or a multilayer of silicon oxide / silicon nitride / silicon oxide. In this embodiment, silicon dioxide is selected as the material for the oxide layer 20. The oxide layer 20 serves as the layer to be etched. Photoresist is coated on the layer to be etched, and a photoresist pattern is formed by exposure, serving as the patterned pattern layer. The thickness ratio of the oxide layer 20 to the photoresist layer 30 is greater than 5.

[0044] Because the thickness ratio of silicon dioxide to photoresist is too large, when using photoresist layer 30 as a mask to etch silicon dioxide, the photoresist has poor etching resistance. Ordinary processes such as CHF3 / O2 / CF4 or C4F8 / O2 / Ar gas combinations cannot meet the silicon dioxide / photoresist selectivity ratio requirements, and cannot effectively mask the silicon dioxide during deep etching, thus failing to meet the etching requirements.

[0045] By introducing a first gas, a combination of CF4 / H2 / Ar, onto the surface of the photoresist layer 30, the process window is as follows:

[0046] 1. Pressure: 40mT~60mT;

[0047] 2. Radio Frequency (RF) frequencies: 60MHz, 900W~1200W; 2MHz, 200W~2500W;

[0048] 3. The ratio of CF4 / H2: 2:1 > x > 1:2;

[0049] 4. Ar flow rate: 100 sccm~500 sccm.

[0050] like Figure 3 As shown, by using the gas combination of CF4 / H2 / Ar, it is easy to obtain the deposited hydrocarbon fluorine polymer on the freshly made photoresist layer 30, thereby forming a hardened layer 40 (Harden PR) on the PR.

[0051] After the first gas is introduced, H2 provides H radicals to react with the PR surface, and can also form CH structures with CF4 to further form longer carbon chains; CF4 provides a C source to help form polymer deposition. The reaction mechanism is as follows:

[0052] The reaction of H2 and PR: (CHO)x + H* → CH4↑ + OH*

[0053] CH4 further undergoes a chain growth reaction:

[0054] (1) CH4→CH3*+H*

[0055] (2) 2CH3*→C2H6

[0056] (3) C2H6 + CH3* → C2H5* + CH4

[0057] (4) C2H5*→C2H4+H*

[0058] (5) C2H6 + H* → C2H5* + H2

[0059] (6) 2C2H5*→C2H6+C2H4

[0060] Chain growth reactions can also include other reactions that form longer chains.

[0061] The deposited polymer hardens the surface structure of the photoresist during etching, protecting the photoresist and thus improving the silicon dioxide / photoresist selectivity. After the hardened layer is formed, using the photoresist layer and the hardened layer as a mask, a second gas, C4F6 / O2 / Ar, is introduced to etch the layer to be etched until the top surface of the etch stop layer is exposed, forming a groove.

[0062] During polymer deposition, the resulting plasma also has an etching effect on the layer to be etched. CF4 provides a carbon source to help form polymer deposition and an iron source to etch the underlying silicon dioxide. The reaction between CF4 and silicon dioxide is: CFx + SiO2 → SiF4 + CO2 + CO. Ar acts as a dilution gas to adjust the concentration of the main gas and provides Ar. + Etching is performed. However, by controlling the flow ratio of CF4 to H2 to (3:1) to (1:3), the polymer can be continuously deposited, thereby forming a hardened layer 40.

[0063] After etching with a second gas, the result is as follows: Figure 2 As shown in (B), deep grooves can be obtained in oxide layer 20.

[0064] By adjusting the CF4 / H2 gas ratio, the process can be controlled to... Figure 2 The semiconductor device structure shown in (A) first undergoes PR processing, with the following process conditions:

[0065] 60mT, 900 / 200(H / L), 300CF4 / xH2 / 400Ar; H / L refers to high frequency and low frequency, respectively.

[0066] Research has found that not all ratios of CF4 / H2 can form the hardened layer. Figure 4 Different CF4 / H2 gas ratios are provided to achieve different etching modes. The etching rate can be adjusted using H2. When the CF4 / H2 gas ratio changes from 6:1 to 1:2 (i.e., from 300CF4 / xH2 from 300CF4 / 50H2 to 300CF4 / 600H2), the PR process changes from etching mode to deposition mode and then back to etching mode. At a gas ratio of 6:1, the groove depth is... When the ratio is 3:1, the groove depth is Therefore, when the CF4 / H2 gas ratio is from 6:1 to 3:1, it is the etching mode. The gas has a higher fluorine content and a lower H2 content, which is beneficial for etching. Simultaneously, the thickness of the upper mask is slightly greater in a 3:1 ratio than in a 6:1 ratio. When the CF4 / H2 gas ratio is from 3:1 to 1:1 (the groove depth is [missing information] at a 1:1 ratio), [missing information]... The process switches to deposition mode, where the H2 content increases, reducing the etching rate and promoting polymer formation. A thicker upper mask is also achieved, resulting in a thicker hardened layer. However, the gas still has some etching effect on the underlying layer to be etched. When the CF4 / H2 gas ratio is less than 1:1 (e.g., a ratio of 1:2 results in a groove depth of...), the etching process is more efficient. The process switches to etching mode, where the H2 content is higher. H2 also acts as an etching gas to etch the device structure. When the gas ratio is 1:2, the upper mask is thicker, meaning that while the layer to be etched has good etching performance, a thicker hardened layer can still be obtained. Figure 4 The results show that when the CF4 / H2 gas ratio is controlled at 2:1 to 1:2, the hardened layer formed by PR treatment is thicker, and CF4 and H2 also have good etching performance on the layer to be etched.

[0067] When the CF4 / H2 gas ratio is close to 3:1 or close to 1:3, the gas has an etching effect, but polymers can still be formed on the surface of the device structure. That is, the reaction process is that the polymer deposition of the mask above and the plasma etching of the layer to be etched below are carried out simultaneously.

[0068] After the photoresist (PR) process, a sufficiently thick hardened layer is formed on top of the PR layer. However, the etching of the underlying silicon dioxide layer is incomplete due to the required etching depth (silicon dioxide / photoresist thickness greater than 5). Further silicon dioxide etching is then performed under the following process conditions:

[0069] 35mT,500 / 1200(H / L),9C4F6 / 7O2 / 600Ar;

[0070] During silicon dioxide etching, a C4F6 / O2 / Ar gas combination is introduced as a second gas, which can quickly etch the layer to be etched and obtain a clean groove.

[0071] The above-mentioned PR processing technology was further adjusted, and the process conditions adopted were as follows:

[0072] 60mT,1200 / 2500(H / L),200CF4 / 400H2 / 300Ar.

[0073] Figure 5 The diagram shows the results of further adjustments to the above-mentioned PR processing technology. Figure 5 In the process, the initial PR thickness (h1) is 3.7 μm. After treatment, the total thickness (h2) of the PR surface is 3.9 μm, which includes approximately 2.6 μm of the underlying PR (h3) and approximately 1 μm of the hardened layer formed on the surface (h4).

[0074] By processing the PR, not only is the original thickness of the PR increased, but the PR is also protected during the subsequent etching process, reducing PR loss.

[0075] In summary, this invention, by introducing a first gas into the surface of the patterned graphic layer to form a hardened layer, and using the graphic layer and the hardened layer as a mask, after introducing a second gas for etching, can protect the graphic layer through the hardened layer when the thickness of the layer to be etched is very thick and the upper graphic layer is relatively thin, thereby improving the selectivity of the layer to be etched to the graphic layer, ensuring that the mask can effectively shield the surface during etching, and meeting the etching requirements.

[0076] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An etching method for forming a semiconductor device structure, characterized in that, Comprising: Providing a substrate, on which an etch layer to be etched is provided, and on which a patterned graphic layer is provided, and the thickness ratio of the etch layer to be etched to the thickness of the graphic layer is greater than 5; The graphic layer is a photoresist layer; The material of the etch layer to be etched includes: silicon dioxide, silicon nitride or polysilicon; Introducing a first gas onto the surface of the graphic layer, the first gas includes: H2 and CHyFz, 0≤y≤3, 0<z≤4; the flow ratio of CHyFz to H2 is 3:1 to 1:3; the first gas reacts with the top of the graphic layer to form a hardening layer; After forming the hardening layer, using the graphic layer and the hardening layer as a mask, introducing a second gas to etch the etch layer to be etched until the top surface of the substrate is exposed, and forming a groove in the etch layer to be etched.

2. The etching method for forming a semiconductor device structure according to claim 1, characterized in that, CHyFz is selected from at least one of: tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2) or CH3F.

3. The etching method for forming a semiconductor device structure according to claim 2, characterized in that, CHyFz is selected as CF4, wherein the gas flow ratio of CF4 to H2 is 2:1 to 1:

2.

4. The etching method for forming a semiconductor device structure according to claim 1, characterized in that, The first gas further includes: at least one of hydrocarbon small molecule gases of C1-C5.

5. The etching method for forming a semiconductor device structure according to claim 4, characterized in that, The hydrocarbon small molecule gas is selected from at least one of: CH4, C2H6 or C2H4.

6. The etching method for forming a semiconductor device structure according to claim 1, characterized in that, The first gas further includes: an inert gas.

7. The etching method for forming a semiconductor device structure according to claim 6, characterized in that, The flow rate of the inert gas is 100 sccm to 500 sccm.

8. The etching method for forming a semiconductor device structure according to claim 1, characterized in that, The second gas includes: a fluorine-containing gas and O2.

9. The etching method for forming a semiconductor device structure according to claim 8, characterized in that, The fluorine-containing gas includes: at least one of nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), octafluoropropane (C3F8), octafluorocyclobutane (C4F8) or octafluoroisobutene (C4F8) or fluorine gas (F2) or C4F6.

10. The etching method for forming a semiconductor device structure according to claim 8, characterized in that, The second gas further includes: an inert gas.

11. The etching method for forming a semiconductor device structure according to claim 6 or 10, characterized in that, The inert gas includes argon or helium.

12. The etching method for forming a semiconductor device structure according to claim 1, characterized in that, The process conditions for forming the hardening layer include: the pressure is 40 mT to 60 mT; the radio frequency is 60 MHz, the radio frequency power is 900 W to 1200 W, or, the radio frequency is 2 MHz, the radio frequency power is 200 W to 2500 W.

13. A semiconductor device structure formed by the method according to any one of claims 1 to 12, characterized in that, Comprising: A substrate, on which an etch layer to be etched is provided, and on which a patterned graphic layer is provided; A hardening layer, located on the top surface of the graphic layer; A groove, located in the etch layer to be etched and between adjacent graphic layers, exposing the top surface of the substrate.

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