Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched; forming a first mask material layer on the layer to be etched; forming a photoresist layer on the first mask material layer, the photoresist layer having a first opening and a second opening adjacent to each other; performing multiple times of rotating implantation on the first mask material layer to form a first mask layer having a first doped region and a second doped region adjacent to each other; and etching the first mask layer until a surface of the layer to be etched is exposed to form a first barrier structure and a second barrier structure adjacent to each other. Thus, the difficulty of the process for forming the semiconductor structure is reduced, and the cost of forming the semiconductor structure is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] In the process of manufacturing semiconductor products, photolithography is typically used to transfer patterns from a photomask to the surface of a silicon wafer, forming a semiconductor product that meets design requirements. In the photolithography process, firstly, through an exposure step, light passes through the transparent or reflective areas of the photomask and illuminates the layer to be etched, coated with photoresist, causing a photochemical reaction with the photoresist. Next, through a development step, the solubility of the developer by the photosensitive and unphotosensitive photoresist forms a photolithographic pattern, achieving the transfer of the photomask pattern. Then, through an etching step, the photolithographic pattern formed on the photoresist layer is etched onto the layer to be etched, further transferring the photomask pattern to the etched layer.

[0003] However, as the integration of semiconductor structures increases, existing photolithography processes are more complex in order to form smaller patterns, resulting in high difficulty and cost in the manufacturing process of forming semiconductor structures. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can reduce the difficulty of forming the semiconductor structure and reduce the cost of forming the semiconductor structure while forming patterns with smaller spacing on the layer to be etched.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched; forming a first mask material layer on the layer to be etched; forming a photoresist layer on the surface of the first mask material layer, the photoresist layer having adjacent first openings and second openings, the bottom of the first openings exposing a portion of the surface of the first mask material layer, and the bottom of the second openings also exposing a portion of the surface of the first mask material layer; performing multiple spin implantations on the first mask material layer to form a first mask layer, the first mask layer having adjacent first doped regions and second doped regions, and the ion implantation angle of each spin implantation being greater than 0 degrees; etching the first mask layer until the surface of the layer to be etched is exposed, forming adjacent first barrier structures and second barrier structures.

[0006] Optionally, each rotational implantation includes: rotating the layer to be etched around a central axis by a first angle, the central axis being a normal passing through the center of the surface of the layer to be etched; and after rotating the layer to be etched, performing ion implantation on the first mask material layer using the photoresist layer as a mask.

[0007] Optionally, the first angle is greater than 0 degrees and is less than or equal to 0 degrees. degree or One of the degrees, where d is the thickness of the photoresist layer, W1 is the width of the first opening, W2 is the width of the second opening, and the first angle is rotated at a speed of 45 degrees every 10 to 60 seconds.

[0008] Optionally, in the ion implantation process, the ion implantation angle... degree or The degrees are given by α, H, W, W1, and W2, where α is the ion implantation angle of the spin implantation, H is the thickness of the first mask material layer, W is the preset width, W1 is the width of the first opening, and W2 is the width of the second opening.

[0009] Optionally, in the ion implantation process, the ion implantation time ranges from 30 seconds to 300 seconds.

[0010] Optionally, the method further includes removing the photoresist layer after forming the first mask layer and before etching the first mask layer.

[0011] Optionally, it also includes: using the first barrier structure and the second barrier structure as masks to etch the layer to be etched.

[0012] Optionally, the layer to be etched includes a substrate and a second mask material layer located on the substrate, wherein the second mask material layer is made of a different material than the first barrier structure and the second barrier structure.

[0013] Optionally, the method for etching the layer to be etched includes: using the first barrier structure and the second barrier structure as masks, etching the second mask material layer until a third barrier structure and a fourth barrier structure are formed on the substrate.

[0014] Optionally, in the process of etching the second mask material layer, the etching ratio of the material of the second mask material layer to the material of the first barrier structure ranges from 10:1 to 200:1.

[0015] Optionally, the sidewall of the first barrier structure has a first angle with the normal perpendicular to the substrate surface, the sidewall of the second barrier structure has a second angle with the normal perpendicular to the substrate surface, the sidewall of the third barrier structure has a third angle with the normal perpendicular to the substrate surface, and the sidewall of the fourth barrier structure has a fourth angle with the normal perpendicular to the substrate surface. Furthermore, the third angle and the fourth angle are both smaller than the first angle, and the third angle and the fourth angle are also smaller than the second angle.

[0016] Optionally, the material of the second mask material layer includes silicon oxide or titanium nitride.

[0017] Optionally, the layer to be etched further includes a third mask material layer located between the substrate and the second mask material layer. The material of the third mask material layer is different from the material of the second mask material layer, and the material of the third mask material layer is also different from the material of the substrate.

[0018] Optionally, the method for etching the layer to be etched further includes: using the third barrier structure and the fourth barrier structure as masks, etching the third mask material layer until the substrate surface is exposed, forming adjacent fifth barrier structures and sixth barrier structures.

[0019] Optionally, the method for etching the layer to be etched further includes: using the fifth and sixth barrier structures as masks to etch the substrate.

[0020] Optionally, the material of the third mask material layer includes silicon.

[0021] Optionally, the material of the first mask material layer includes silicon.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] In the semiconductor structure formation method provided by the technical solution of the present invention, since the first mask material layer is subjected to multiple rotational implantation, and in each rotational implantation, ions are tilted (ion implantation angle is greater than 0 degrees), a first doped region and a second doped region with a larger width are formed compared to the width of the first opening and the second opening. Therefore, the spacing between the first doped region and the second doped region can be smaller than the spacing between the first opening and the second opening. Similarly, the spacing between the first barrier structure and the second barrier structure can be smaller than the spacing between the first opening and the second opening. Thus, the spacing between the patterns (first barrier structure and second barrier structure) transferred to the etchable layer is reduced, thereby reducing the number of photoresist layers that need to be formed in the photolithography process. This allows for the formation of smaller-spacing patterns on the etchable layer while reducing the difficulty of forming the semiconductor structure and the cost of forming the semiconductor structure. Attached Figure Description

[0024] Figures 1 to 3 This is a top view schematic diagram of the steps in a semiconductor structure formation method;

[0025] Figures 4 to 9 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, existing photolithography processes are quite complex, resulting in high difficulty and cost in manufacturing semiconductor structures. The following will provide a detailed explanation with reference to the accompanying drawings.

[0027] It should be noted that the term "surface" in this specification is used to describe the relative spatial relationship and is not limited to whether there is direct contact.

[0028] Figures 1 to 3 This is a top view schematic diagram of the steps in a semiconductor structure formation method.

[0029] Please refer to Figure 1 A substrate (not shown) is provided; a mask material layer 100 is formed on the substrate; a first photoresist layer 110 is formed on the mask material layer 100, the first photoresist layer 110 having a first opening 111; using the first photoresist layer 110 as a mask, ion implantation is performed on the mask material layer 100 to form a first doped region (not shown); after forming the first doped region, the first photoresist layer 110 is removed.

[0030] Please refer to Figure 2 After removing the first photoresist layer 110, a second photoresist layer 120 is formed on the mask material layer 100, and the second photoresist layer 120 has a first opening 121; using the second photoresist layer 120 as a mask, ion implantation is performed on the mask material layer 100 to form a second doped region (not shown); after forming the second doped region, the second photoresist layer 120 is removed.

[0031] Please refer to Figure 3 After removing the second photoresist layer 120, the mask material layer 100 is etched back until the substrate surface is exposed to form a first barrier structure 101 and a second barrier structure 102. The spacing A between the first barrier structure 101 and the second barrier structure 102 is less than the size limit of the photolithography process.

[0032] Next, the substrate is etched using the first barrier structure 101 and the second barrier structure 102 as masks.

[0033] In the above method, since two photoresist layers are formed—that is, the first photoresist layer 110 and the second photoresist layer 120 are formed through two photolithography processes—the size of the pattern transferred to the mask material layer 100 can be smaller than the size limit of the photolithography process. Specifically, the distance A between the first blocking structure 101 and the second blocking structure 102 can be smaller than the size limit of the photolithography process. Similarly, as the complexity of the pattern to be transferred to the etched layer increases, more photolithography processes are needed to form more photoresist layers to achieve pattern transfer.

[0034] However, on the one hand, the manufacturing cost of semiconductor structures is high because multiple photoresist layers need to be formed to achieve pattern transfer. On the other hand, when multiple photoresist layers need to be formed, the overlay precision between each photoresist layer also needs to be controlled, thus increasing the difficulty of the semiconductor structure manufacturing process. In summary, this results in the high difficulty and cost of forming semiconductor structures.

[0035] To address the aforementioned problems, this invention provides a method for forming a semiconductor structure. This method involves repeatedly rotating and implanting a first mask material layer to form adjacent first and second doped regions. Then, the first mask layer is etched until the surface of the layer to be etched is exposed, forming adjacent first and second barrier structures. This reduces the difficulty and cost of forming the semiconductor structure.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 9 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 4 Provide a layer 200 to be etched; form a first mask material layer 300 on the layer 200 to be etched.

[0039] The first mask material layer 300 provides initial material for the subsequent formation of the first barrier structure and the second barrier structure.

[0040] In this embodiment, the layer to be etched 200 includes: a substrate 210 and a second mask material layer 220 located on the substrate 210.

[0041] In this embodiment, the substrate 210 is made of a low-k dielectric layer (K ​​less than or equal to 3.9).

[0042] In other embodiments, the substrate material includes silicon oxide.

[0043] The second mask material layer 220 provides material for the subsequent formation of the third and fourth barrier structures.

[0044] The second mask material layer 220 is made of a different material than the first and second barrier structures. Therefore, during the etching process that forms the first and second barrier structures, the second mask material layer 220 has a better etching barrier capability, which helps to reduce the damage caused to the second mask material layer by the etching process.

[0045] In this embodiment, the material of the second mask material layer 220 includes silicon oxide or titanium oxide.

[0046] In this embodiment, the layer to be etched 200 further includes a third mask material layer 230.

[0047] The third mask material layer 230 is located between the substrate 210 and the second mask material layer 220. The material of the third mask material layer 230 is different from that of the second mask material layer 220, and the material of the third mask material layer 230 is also different from that of the substrate 210.

[0048] On the one hand, the third mask material layer 230 provides material for the subsequent formation of the fifth and sixth barrier structures on the substrate 210. On the other hand, the third mask material layer 230 located on the substrate 210 can protect the substrate 210 during the subsequent etching process for forming the third and fourth barrier structures, reduce the damage to the surface of the substrate 210 caused by the etching process for forming the third and fourth barrier structures, and improve the performance of the semiconductor structure.

[0049] Furthermore, since the material of the third mask material layer 230 is different from that of the second mask material layer 220, different etching rates can be applied to the second mask material layer 220 and the third mask material layer 230 during the subsequent etching processes that form the third and fourth barrier structures. Therefore, the third mask material layer 230 has better barrier capability against the etching processes that form the third and fourth barrier structures. Consequently, on the one hand, the third mask material layer 230 can better protect the substrate 210. On the other hand, it also reduces the wear and tear on the third mask material layer 230 itself during the etching processes that form the third and fourth barrier structures. Therefore, it is beneficial to form the fifth and sixth barrier structures with better morphology, so as to better transfer the pattern to the substrate 210.

[0050] Specifically, in this embodiment, the material of the third mask material layer 230 includes silicon, such as amorphous silicon.

[0051] In another embodiment, the layer to be etched does not include a third mask material layer. The substrate material is different from the material of the second mask material layer. Similarly, because the substrate material is different from the second mask material layer, the etching processes for forming the third and fourth barrier structures can have different etching rates on the substrate and the second mask material layer. This allows the substrate to have better barrier capabilities against the etching processes forming the third and fourth barrier structures, reducing damage to the substrate surface and improving the performance of the semiconductor structure. Furthermore, compared to this embodiment, since the third mask material layer, fifth barrier structure, and sixth barrier structure are not formed, the semiconductor structure formation efficiency is improved, and the manufacturing cost of the semiconductor structure is reduced, achieving a better balance between semiconductor structure performance, cost, and formation efficiency.

[0052] In another embodiment, the layer to be etched does not include a second mask material layer. Furthermore, the material of the first mask material layer is different from the material of the substrate, thereby further improving the formation efficiency of the semiconductor structure and reducing the cost of manufacturing the semiconductor structure.

[0053] In this embodiment, the process of forming the first mask material layer 300 includes a deposition process, which includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0054] In other embodiments, the process for forming the first mask material layer also includes spin coating or epitaxial growth.

[0055] Specifically, in this embodiment, the material of the first mask material layer 300 includes silicon, such as amorphous silicon.

[0056] Please refer to Figure 5 A photoresist layer 400 is formed on the surface of the first mask material layer 300. The photoresist layer 400 has an adjacent first opening 410 and a second opening 420. The bottom of the first opening 410 exposes a portion of the surface of the first mask material layer 300, and the bottom of the second opening 420 also exposes a portion of the surface of the first mask material layer 300.

[0057] In this embodiment, the method for forming the photoresist layer 400 includes: forming a photoresist material layer (not shown) on the surface of the first mask material layer 300; and exposing and developing the photoresist material layer to form the photoresist layer 400.

[0058] In this embodiment, the first opening 410 has a width W1 and the second opening 420 has a width W2 in a direction perpendicular to the sidewall of the first opening 410. A spacing G1 exists between adjacent first openings 410 and second openings 420.

[0059] Next, please refer to Figure 6 The first mask material layer 300 is subjected to multiple rotational implantation to form a first mask layer 310. The first mask layer 310 has adjacent first doped regions 311 and second doped regions 312, and the ion implantation angle of each rotational implantation is greater than 0 degrees.

[0060] Because the first mask material layer 300 is subjected to multiple rotational implantations, and the ion implantation angle of each rotational implantation is greater than 0 degrees, therefore, compared to the width dimension of the first opening 410 (e.g., Figure 5 The width W1 shown) and the width dimension of the second opening 420 (as shown) Figure 5 The width W2 shown in the figure forms a first doped region 311 and a second doped region 312 with a larger width dimension. Therefore, the spacing between the first doped region 311 and the second doped region 312 can be smaller than the spacing G1 between the first opening 410 and the second opening 420 (as shown in the figure). Figure 5 (As shown).

[0061] The first doped region 311 provides material for the subsequent formation of the first barrier structure, and the second doped region 312 provides material for the subsequent formation of the second barrier structure.

[0062] Specifically, each rotational implantation includes: rotating the layer to be etched 200 around a central axis by a first angle, the central axis being the normal passing through the center of the surface of the layer to be etched 200; after rotating the layer to be etched 200, using the photoresist layer 400 as a mask, performing ion implantation on the first mask material layer 300, and the ion implantation angle (e.g., ...) Figure 6 The angle α shown is greater than 0 degrees.

[0063] In this embodiment, the first angle is greater than 0 degrees and is less than or equal to 0 degrees. The degree, where d is the thickness of the photoresist layer 400, W1 is the width of the first opening 410, and the first angle is rotated at a speed of 45 degrees every 10 to 60 seconds.

[0064] In other embodiments, the first angle is greater than 0 degrees and is less than or equal to 0 degrees. The degree, where W2 is the width of the second opening 420.

[0065] Therefore, by controlling the size of the first angle and the rotation speed, the range of implanted ions can be controlled, so that the deviation between the spacing between the subsequently formed first and second barrier structures and the spacing required by the design is smaller, thereby improving the pattern accuracy transferred to the substrate 210.

[0066] In this embodiment, in the ion implantation process, the ion implantation angle is... Degree. Where α is the ion implantation angle of the spin implantation, H is the thickness of the first mask material layer 300, and W is the preset width, that is, the design width of the pattern subsequently transferred to the etched layer through the first barrier structure.

[0067] In other embodiments, ion implantation angle Spend.

[0068] Therefore, by precisely controlling the ion implantation angle, the range of implanted ions can be controlled, resulting in a smaller deviation between the spacing between the subsequently formed first and second barrier structures and the spacing required by the design, thus improving the patterning accuracy transferred to the substrate 210. The range of implanted ions specifically includes the depth and width of the implanted ion diffusion, as well as the shape of the formed region.

[0069] In this embodiment, the ion implantation time ranges from 30 seconds to 300 seconds during the ion implantation process. Therefore, by controlling the ion implantation time, the range of implanted ions is controlled, resulting in a smaller deviation between the spacing between the subsequently formed first and second barrier structures and the design-required spacing, thus improving the patterning accuracy transferred to the substrate 210.

[0070] Please refer to Figure 7 The first mask layer 310 is etched until the surface of the layer to be etched 200 is exposed, forming an adjacent first barrier structure 321 and a second barrier structure 322.

[0071] Since the spacing between the first doped region 311 and the second doped region 312 can be smaller than the spacing G1 between the first opening 410 and the second opening 420 (e.g. Figure 5 As shown, the spacing between the first blocking structure 321 and the second blocking structure 322 can be smaller than the spacing G1 between the first opening 410 and the second opening 420. This reduces the spacing between the patterns (first blocking structure 321 and second blocking structure 322) transferred to the etchable layer, thereby reducing the number of photoresist layers that need to be formed in the photolithography process. This allows for the formation of smaller-spacing patterns on the etchable layer 200 while reducing the difficulty of forming the semiconductor structure, reducing the cost of forming the semiconductor structure, and improving the efficiency of forming the semiconductor structure.

[0072] Furthermore, by reducing the number of photoresist layers, overlay deviations that occur during the formation of multiple photoresist layers are better avoided, the process window for semiconductor structure formation is increased, and the process difficulty is also reduced.

[0073] In this embodiment, the process of etching the first mask layer 310 to form the first barrier structure 311 and the second barrier structure 312 includes a back etching process.

[0074] The etching process includes dry etching or wet etching.

[0075] In this embodiment, the sidewall of the first blocking structure 321 has a first included angle A1 with the normal perpendicular to the surface of the substrate 210, and the sidewall of the second blocking structure 322 has a second included angle A2 with the normal perpendicular to the surface of the substrate 210.

[0076] Specifically, since the first doped region 311 and the second doped region 312 are formed by multiple spin implantations, the boundary between the materials of the first doped region 311 and the first mask layer 310 is prone to tilting. Similarly, the boundary between the materials of the second doped region 312 and the first mask layer 310 is also prone to tilting. Therefore, the formed first barrier structure 321 is prone to tilting, and similarly, the formed second barrier structure 321 is prone to tilting. That is, the sidewall of the first barrier structure 321 has a first included angle A1 with the normal perpendicular to the surface of the substrate 210, and the sidewall of the second barrier structure 322 has a second included angle A2 with the normal perpendicular to the surface of the substrate 210.

[0077] In this embodiment, the photoresist layer 400 is removed after the first mask layer 310 is formed and before the first mask layer 310 is etched. The process for removing the photoresist layer 400 includes an ashing process, etc.

[0078] Next, the layer 200 to be etched is etched using the first blocking structure 321 and the second blocking structure 322 as masks.

[0079] Specifically, please refer to Figure 8 Using the first barrier structure 321 and the second barrier structure 322 as masks, the second mask material layer 220 is etched until the third barrier structure 221 and the fourth barrier structure 222 are formed on the substrate 210.

[0080] In this embodiment, the method of etching the second mask material layer 220 includes: using the first barrier structure 321 and the second barrier structure 322 as masks, etching the second mask material layer 220 until the third mask material layer 230 is exposed, forming an initial third barrier structure (not shown) and an initial fourth barrier structure (not shown); then, continuing to etch the initial third barrier structure and the fourth barrier structure to increase the perpendicularity of the sidewalls of the initial third barrier structure and the initial fourth barrier structure until the third barrier structure 221 and the fourth barrier structure 222 are formed.

[0081] Specifically, the sidewall of the third blocking structure 221 has a third included angle (not shown) with the normal perpendicular to the surface of the substrate 210, and the sidewall of the fourth blocking structure 222 has a fourth included angle (not shown) with the normal perpendicular to the surface of the substrate 210. Furthermore, the third and fourth included angles are smaller than the first included angle A1, and the third and fourth included angles are also smaller than the second included angle A2.

[0082] By forming the third barrier structure 221 and the fourth barrier structure 222, a semiconductor structure with a better morphology can be formed during the pattern transfer process of the semiconductor structure, thereby improving the stability and pattern accuracy of the pattern transferred to the substrate 210, and thus improving the performance and reliability of the semiconductor structure.

[0083] In this embodiment, during the etching process of the second mask material layer 220, the etching selectivity ratio between the material of the second mask material layer 220 and the material of the first barrier structure 321 ranges from 10:1 to 200:1. Therefore, by using a larger etching selectivity ratio, it is possible to prevent the first barrier structure 321 and the second barrier structure 322 from being completely worn away during the formation of the third barrier structure 221 and the fourth barrier structure 222.

[0084] In this embodiment, during the etching process of the second mask material layer 220, the etching selectivity ratio of the materials of the second mask material layer 220 and the third mask material layer 230 ranges from 10:1 to 200:1. Therefore, with a larger etching selectivity ratio, the third mask material layer 230 can better protect the substrate 210, reducing damage to the substrate 210 caused by the etching process of the second mask material layer 220, thereby improving the performance and reliability of the semiconductor structure.

[0085] Next, please refer to Figure 9 Using the third barrier structure 221 and the fourth barrier structure 222 as masks, the third mask material layer 230 is etched until the surface of the substrate 210 is exposed, forming adjacent fifth barrier structure 231 and sixth barrier structure 232.

[0086] In this embodiment, by forming the third mask material layer 230 and etching the third mask material layer 230 to form adjacent fifth barrier structures 231 and sixth barrier structures 232, the stability of the pattern transferred to the substrate 210 is further increased.

[0087] In this embodiment, the etching process of the third mask material layer 230 includes a dry etching process or a wet etching process.

[0088] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fifth barrier structure 231 and the sixth barrier structure 232, etching the substrate 210 using the fifth barrier structure 231 and the sixth barrier structure 232 as masks.

[0089] In another embodiment, the layer to be etched does not include a third mask material layer. Therefore, the method for etching the layer to be etched includes etching the substrate using a third barrier structure and a fourth barrier structure as masks.

[0090] In another embodiment, the layer to be etched does not include a second mask material layer. Therefore, the method for etching the layer to be etched includes: using a first barrier structure and a second barrier structure as masks to etch the substrate.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide the layer to be etched; A first mask material layer is formed on the layer to be etched; A photoresist layer is formed on the surface of the first mask material layer. The photoresist layer has an adjacent first opening and a second opening. The bottom of the first opening exposes a portion of the surface of the first mask material layer, and the bottom of the second opening also exposes a portion of the surface of the first mask material layer. The first mask material layer is subjected to multiple rotation implantations to form a first mask layer. The first mask layer has adjacent first doped regions and second doped regions. The first doped region is located in the first mask material layer exposed at the bottom of the first opening, and the second doped region is located in the first mask material layer exposed at the bottom of the second doped region. The width of the first doped region is greater than the width of the first opening, and the width of the second doped region is greater than the width of the second opening. The ion implantation angle of each rotation implantation is greater than 0 degrees. The first mask layer is etched until the surface of the layer to be etched is exposed, forming an adjacent first barrier structure and a second barrier structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Each rotational implantation includes: rotating the layer to be etched around a central axis by a first angle, the central axis being a normal passing through the center of the surface of the layer to be etched; and after rotating the layer to be etched, using the photoresist layer as a mask, performing ion implantation on the first mask material layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first angle is greater than 0 degrees, and less than 0 degrees. or equal to One of degrees or degrees, where d is the thickness of the photoresist layer, W1 is the width of the first opening, W2 is the width of the second opening, and the first angle is rotated at a speed of 45 degrees every 10 to 60 seconds.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the ion implantation process, or Where α is the ion implantation angle of the spin implantation, H is the thickness of the first mask material layer, W is the preset width, W1 is the width of the first opening, and W2 is the width of the second opening.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the ion implantation process, the ion implantation time ranges from 30 seconds to 300 seconds.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the first mask layer is formed and before the first mask layer is etched, the photoresist layer is removed.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Using the first and second barrier structures as masks, the layer to be etched is etched.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The layer to be etched includes a substrate and a second mask material layer located on the substrate, the second mask material layer being made of a different material than the first barrier structure and the second barrier structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for etching the layer to be etched includes: using the first barrier structure and the second barrier structure as masks, etching the second mask material layer until a third barrier structure and a fourth barrier structure are formed on the substrate.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the process of etching the second mask material layer, the etching ratio of the material of the second mask material layer to the material of the first barrier structure ranges from 10:1 to 200:

1.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first barrier structure has a first angle between its sidewall and the normal perpendicular to the substrate surface; the second barrier structure has a second angle between its sidewall and the normal perpendicular to the substrate surface; the third barrier structure has a third angle between its sidewall and the normal perpendicular to the substrate surface; and the fourth barrier structure has a fourth angle between its sidewall and the normal perpendicular to the substrate surface. Furthermore, the third and fourth angles are smaller than the first angle, and the third and fourth angles are also smaller than the second angle.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the second mask material layer includes silicon oxide or titanium nitride.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The layer to be etched further includes a third mask material layer located between the substrate and the second mask material layer. The material of the third mask material layer is different from the material of the second mask material layer, and the material of the third mask material layer is also different from the material of the substrate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for etching the layer to be etched further includes: using the third barrier structure and the fourth barrier structure as masks, etching the third mask material layer until the substrate surface is exposed, forming adjacent fifth barrier structures and sixth barrier structures.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for etching the layer to be etched further includes: using the fifth barrier structure and the sixth barrier structure as masks to etch the substrate.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The material of the third mask material layer includes silicon.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first mask material layer includes silicon.

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