Chip bonding alignment structure and bonded chip structure and manufacturing method thereof

Abstract

The present application discloses a chip bonding alignment structure and a bonded chip structure and a manufacturing method thereof. The chip bonding alignment structure comprises a semiconductor chip, a metal layer, an etch stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer and a silicon carbon nitride layer. The metal layer is on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etch stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer through the etch stop layer. The dielectric barrier layer covers the etch stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbon nitride layer covers the silicon oxide layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method for fabricating the same, and more particularly to a bonding alignment structure for a semiconductor chip bonding technique and a bonded chip structure fabricated by using the bonding alignment structure and a method for fabricating the same. BACKGROUND

[0002] Chip bonding technique refers to the process of bonding two semiconductor chips (e.g. wafers) together after cleaning, and then performing high-temperature annealing to form chemical bonds at the interface between the two semiconductor chips. Chip bonding technique has become an important means for preparing composite materials and implementing micro-machining, and is widely used in semiconductor fabrication processes, including substrate engineering, integrated circuit manufacturing, micro-electro-mechanical systems (MEMS), and packaging.

[0003] In a typical chip bonding technique, an inter-bonding layer (IBL) including a dielectric buffer layer and a bonding material layer (usually a silicon carbon nitride layer) is formed on the bonding surface of each of the two semiconductor chips. Then, heat and pressure are applied to the bonding material layer surface atoms of the two semiconductor chips to form covalent bonds. When the bonding energy reaches a certain strength, the two semiconductor chips can be integrated without the use of adhesive media. In order to accurately align the two semiconductor chips, an alignment mark is formed on the metal layer closest to the bonding surface of one of the semiconductor chips. Image recognition is then used to identify the alignment mark and accurately bond the two semiconductor chips face to face.

[0004] However, the alignment mark is covered by the dielectric buffer layer and the bonding material layer, which may result in poor clarity of the alignment mark, making it difficult to identify, and thus reducing the alignment accuracy of the two semiconductor chips. In addition, the alignment mark is usually a copper metal pattern, which is easily affected by other thermal fabrication processes (such as thermal annealing fabrication processes) before chip bonding, resulting in Cu hillock defects. The Cu hillock defects can penetrate the dielectric buffer layer and / or the bonding material layer, causing copper ions to diffuse into the dielectric buffer layer and / or the bonding material layer or other subsequent material layers, which may affect the performance and reliability of the bonded semiconductor chips.

[0005] Therefore, there is a need to provide an advanced chip bonding alignment structure and bonded chip structure and a method for fabricating the same to solve the problems faced by the prior art. SUMMARY

[0006] An embodiment of the present disclosure discloses a chip bonding alignment structure, which includes a semiconductor chip, a metal layer, an etch stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbon nitride layer. The metal layer is on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etch stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer through the etch stop layer. The dielectric barrier layer covers the etch stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbon nitride layer covers the silicon oxide layer.

[0007] Another embodiment of the present disclosure discloses a method for manufacturing a chip bonding alignment structure, which includes the following steps. First, a metal layer is formed on a bonding surface of a semiconductor chip, and has a metal alignment pattern. Then, an etch stop layer is formed to cover the bonding surface and the metal layer. A high pressure anneal (HPA) process is performed to form at least one metal bump extending upward from the metal layer through the etch stop layer. Next, a dielectric barrier layer is formed to cover the etch stop layer and the metal bump. A silicon oxide layer is formed to cover the dielectric barrier layer. A silicon carbon nitride layer is formed to cover the silicon oxide layer.

[0008] Still another embodiment of the present disclosure discloses a bonded chip structure, which includes a first semiconductor chip, a second semiconductor chip, and a via plug. The first semiconductor chip has a first bonding surface and includes a metal layer, at least one metal bump, an etch stop layer, a silicon oxide layer, and a silicon carbon nitride layer. The metal layer is on the first bonding surface and has a metal alignment pattern. The etch stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer through the etch stop layer. The dielectric barrier layer covers the etch stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbon nitride layer covers the silicon oxide layer. The second semiconductor chip has a second metal wire layer and a second bonding surface facing the first bonding surface. The via plug electrically connects the first metal wire layer in the first semiconductor chip and the second metal wire layer in the second semiconductor chip.

[0009] Yet another embodiment of the present disclosure provides a method for fabricating a bonded chip structure. The method includes the following steps. First, a metal layer is formed on a first bonding surface of a first semiconductor chip, and the metal layer has a metal alignment pattern. Then, an etch stop layer is formed on the first bonding surface and the metal layer. Next, a high pressure anneal process is performed to form at least one metal hillock extending upward from the metal layer through the etch stop layer. Thereafter, a dielectric barrier layer is formed on the etch stop layer and the metal hillock. A silicon oxide layer is formed on the dielectric barrier layer. A silicon carbonitride layer is formed on the silicon oxide layer. Subsequently, a second bonding surface of a second semiconductor chip is bonded to the first bonding surface. Finally, a via plug is formed to electrically connect a first metal wiring layer in the first semiconductor chip and a second metal wiring layer in the second semiconductor chip.

[0010] According to the above embodiments, the present disclosure provides a chip bonding alignment structure, a bonded chip structure, and methods for fabricating the same. The chip bonding alignment structure is formed by first forming a metal layer having a metal alignment pattern on a bonding surface of one of two semiconductor chips to be bonded. The high pressure anneal step for repairing metal wiring layers of semiconductor chip elements is delayed, and an etch stop layer is formed on the metal layer before the high pressure anneal is performed. The high pressure anneal is performed to generate metal hillocks (e.g., Cu hillocks) in the metal layer and break through the etch stop layer. Thereafter, a dielectric barrier layer is formed on the etch stop layer to cover the metal hillocks. A bonding intermediate layer including a silicon oxide layer and a silicon carbonitride layer is sequentially formed on the dielectric barrier layer to form the chip bonding alignment structure. Subsequently, the chip bonding alignment structure is used for alignment, and the bonding surfaces of the two semiconductor chips are bonded to each other to form the bonded chip structure.

[0011] The metal hillocks can increase the definition of the metal alignment pattern in the metal layer, which is beneficial for accurate alignment of chip bonding. In addition, the metal hillocks are covered by the dielectric barrier layer, which prevents metal ions in the metal hillocks from diffusing into the bonding intermediate layer formed subsequently, avoids the bonding intermediate layer from being broken, and maintains the flatness of the bonding intermediate layer. Therefore, the alignment accuracy of the chip bonding fabrication process can be improved, and the fabrication yield and quality of the bonded chip structure can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] For a better understanding of the above and other aspects of the present disclosure, examples are hereinafter described in detail with reference to the drawings, in which:

[0013] Figures 1A-1F For an embodiment of the present disclosure, a series of fabrication process structure cross-sectional schematic diagrams for fabricating a semiconductor bonded chip structure 10 are shown.

[0014] SYMBOL DESCRIPTION

[0015] 10: bonded chip structure

[0016] 11: first semiconductor chip

[0017] 11a: first bonding surface

[0018] 12: second semiconductor chip

[0019] 12a: second bonding surface

[0020] 100: chip bonding alignment structure

[0021] 101: device substrate

[0022] 101a: front side surface of device substrate

[0023] 102: interlayer dielectric layer

[0024] 102a: top surface of interlayer dielectric layer

[0025] 103: metal wire layer

[0026] 104: etch stop layer

[0027] 105: high pressure anneal fabrication process

[0028] 106a: metal bump

[0029] 106b: metal bump

[0030] 107: dielectric barrier layer

[0031] 108: silicon oxide layer

[0032] 108a: upper surface of silicon oxide layer

[0033] 109: silicon carbonitride layer

[0034] 110: metal layer

[0035] 110p: metal alignment pattern

[0036] 121: device substrate

[0037] 121a: front side surface of device substrate

[0038] 122: interlayer dielectric layer

[0039] 122a: top surface of interlayer dielectric layer

[0040] 123: metal wire layer

[0041] 124: etch stop layer

[0042] 128: silicon oxide layer

[0043] 129: silicon carbonitride layer DETAILED DESCRIPTION

[0044] The present application provides a chip bonding alignment structure and a bonded chip structure and a manufacturing method thereof. The alignment precision of the chip bonding manufacturing process is improved, and the manufacturing process yield and quality of the bonded chip structure are improved. In order to make the above-mentioned embodiments and other purposes, features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail with reference to the accompanying drawings.

[0045] However, it should be noted that these specific embodiments and methods are not intended to limit the present application. The present application can also be implemented using other features, elements, methods and parameters. The preferred embodiments are presented only to illustrate the technical features of the present application, and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and changes without departing from the spirit of the present application based on the description in the following specification. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0046] Please refer to Figures 1A-1F , Figures 1A-1F Fig. 1 is a schematic diagram of a series of manufacturing process structure cross sections for manufacturing a bonded chip structure 10 according to an embodiment of the present application. The manufacturing method of the bonded chip structure 10 includes the following steps: first, a first semiconductor chip 11 is provided, and a metal layer 110 is formed on a first bonding surface 11a of the first semiconductor chip 11, so that it has a metal alignment pattern 110p (as shown in Figure 1A ).

[0047] The step of forming the first semiconductor chip 11 includes performing a back-end-of-line (BEOL) process (not shown) on the front side surface 101a of the element substrate 101, forming an interlayer dielectric (ILD) layer 102 and a multilayer metal wire layer 103 on the front side surface 101a.

[0048] In some embodiments of the present disclosure, the device substrate 101 can be made of a semiconductor material, such as silicon (Si), germanium (Ge), or a compound semiconductor material, such as gallium arsenide (GaAs). In other embodiments, the device substrate 101 can be a silicon-on-insulator (SOI) substrate. In some embodiments, the device substrate 101 is preferably a silicon substrate, such as a silicon wafer. The metal line layer 103 includes at least one semiconductor device (not shown), such as a transistor, a capacitor, a resistor, other active / passive devices, microelectronic / micromechanical structures (not shown), or any combination thereof.

[0049] In some embodiments of the present disclosure, the metal layer 110 can be the uppermost metal layer of the plurality of metal line layers 103 embedded in the ILD layer 102. The top surface 102a of the ILD layer 102 can be considered as the first bonding surface 11a of the first semiconductor chip 11. In some embodiments, the metal layer 110 (metal line layer 103) is a patterned copper layer formed using a copper fabrication process, and the metal alignment pattern 110p can be a copper alignment pattern located at the edge region of the device substrate 101.

[0050] An etch stop layer 104 is then formed to cover the first bonding surface (the top surface 102a of the ILD layer 102) and the metal layer 110, as shown in FIG. 1C. Figure 1B In some embodiments of the present disclosure, the etch stop layer 104 can be made of a dielectric material, such as silicon carbon nitride, silicon nitride, or a combination thereof.

[0051] A high pressure anneal fabrication process 105 is then performed to increase the surface roughness of the metal layer 110 and form at least one metal hillock (e.g., metal hillocks 106a and 106b) extending upward from the metal layer 110 through the etch stop layer 104, as shown in FIG. 1D. Figure 1C In some embodiments, the metal layer 110 is a copper layer, and the metal hillocks 106a and 106b formed can be copper hillocks. The metal hillock 106a can extend upward from the metal alignment pattern 110p through the etch stop layer 104, and the metal hillock 106b can extend upward from other portions of the metal layer 110 through the etch stop layer 104.

[0052] It is noted that Figure 1CThe depicted metal bumps 106a and 106b are merely illustrative; in other embodiments, the number, shape, size, and location of formation of the metal bumps are not limited. For example, in some embodiments, no metal bumps 106a can be formed on the metal alignment pattern 110p after the high pressure anneal fabrication process 105. In other embodiments, more metal bumps (not depicted) can be formed extending upward from any other location of the metal layer 110 through the etch stop layer 104.

[0053] Subsequently, a plurality of deposition fabrication processes, such as a Focused Ion Beam (FIB) deposition fabrication process, are performed to sequentially form a dielectric barrier layer 107 covering the etch stop layer 104 and the metal bumps 106; form a silicon oxide layer 108 covering the dielectric barrier layer 107; and form a silicon carbon nitride layer 109 covering the silicon oxide layer 108, to complete the fabrication of the chip bonding alignment structure 100 as depicted. Figure 1D The depicted chip bonding alignment structure 100 is fabricated. The material constituting the dielectric barrier layer 107 can be selected from a group consisting of silicon carbon nitride, silicon carbide, silicon nitride, silicon oxide carbide, and any combination thereof.

[0054] In the present embodiment, before forming the silicon carbon nitride layer 109, a planarization step (not depicted) is performed on the silicon oxide layer 108, such as a Chemical-Mechanical Planarization (CMP) technique, to remove a portion of the silicon oxide layer 108 to provide a substantially planar upper surface 108a, and then the silicon carbon nitride layer 109 is formed on the upper surface 108a of the silicon oxide layer 108 by a deposition fabrication process.

[0055] The chip bonding alignment structure 100 can include: a semiconductor chip 11, a metal layer 110, an etch stop layer 104, at least one metal bump 106, a dielectric barrier layer 107, a silicon oxide layer 108, and a silicon carbon nitride layer 109. The metal layer 110 is located on a first bonding surface 11a of the first semiconductor chip 11 and has a metal alignment pattern 110p. The etch stop layer 104 covers the bonding surface and the metal layer 107. The metal bump 106 extends upward from the metal alignment pattern 110p or other locations of the metal layer 110 through the etch stop layer 104. The dielectric barrier layer 107 covers the etch stop layer 104 and the metal bump 106. The silicon oxide layer 108 covers the dielectric barrier layer 107. The silicon carbon nitride layer 109 covers the silicon oxide layer 108.

[0056] Subsequently, a second semiconductor chip 12 is provided, and the first semiconductor chip 11 and the second semiconductor chip 12 are bonded face-to-face (as depicted in FIG. 1C). Figure 1EIn the present embodiment, the formation of the second semiconductor chip 12 includes the following steps: first, forming the interlayer dielectric layer 122 and at least one metal wiring layer 123 on the front side surface 121a of the device substrate 121 for forming at least one semiconductor device on the front side surface 121a of the device substrate 121. Then, sequentially forming the etch stop layer 124, the silicon oxide layer 128 and the silicon carbonitride layer 129 over the interlayer dielectric layer 122 using a plurality of deposition fabrication processes. In the present embodiment, the top surface 122a of the interlayer dielectric layer 122 can be considered as the bonding surface 12a of the second semiconductor chip 12.

[0057] The bonding step of the first semiconductor chip 11 and the second semiconductor chip 12 includes: flipping the second semiconductor chip 12 so that the silicon carbonitride layer 129 located above the bonding surface 12a of the second semiconductor chip 12 is in face-to-face contact with the silicon carbonitride layer 109 located above the first bonding surface 11a of the first semiconductor chip 11. Then, covalently bonding the surface atoms of the silicon carbonitride layers 109 and 129 by heat and pressure to tightly bond the first semiconductor chip 11 and the second semiconductor chip 122.

[0058] Then, forming the via plug 13 to connect the metal wiring layer 103 in the first semiconductor chip 11 and the metal wiring layer 123 in the second semiconductor chip 12. In the present embodiment, the step of forming the via plug 13 includes performing an etching fabrication process using the etch stop layer 104 as a stop layer to remove a portion of the device substrate 121, the interlayer dielectric layer 122, the etch stop layer 124, the silicon oxide layer 128, the silicon carbonitride layer 129, the silicon carbonitride layer 109, the silicon oxide layer 108, the dielectric barrier layer 107 and the etch stop layer 104 to form an opening to expose a portion of the metal wiring layer 103. The opening is then filled with a conductive material. Subsequently, a semiconductor bonded chip structure 10 as shown in FIG. 1 is formed by a series of back-end fabrication processes, such as a metal damascene process (not shown). Figure 1F

[0059] ​According to the above-mentioned embodiments, the present specification provides a chip bonding alignment structure 100 and a bonded chip structure 10 and a manufacturing method thereof. A metal layer 110 with a metal alignment pattern 110p is formed on a bonding surface (a first bonding surface 11a) of one of two semiconductor chips (a first semiconductor chip 11 and a second semiconductor chip 12) (the first semiconductor chip 11) to be bonded. A high-pressure annealing step 105 used for repairing a metal wire layer (a metal wire layer 103) of a semiconductor chip element (the first semiconductor chip 11) is delayed, and an etching stop layer 104 is formed on the metal layer 110, and then the high-pressure annealing step 105 is performed. Metal hillock defects (for example, Cu hillock) are generated in the metal layer 110 and break through the etching stop layer 104. After the high-pressure annealing step 105, a dielectric barrier layer 107 is formed on the etching stop layer 104 to cover the metal hillock 106, and a bonding intermediate layer including a silicon oxide layer 108 and a silicon carbonitride layer 109 is sequentially formed on the dielectric barrier layer 107 to form the chip bonding alignment structure. Subsequently, the two semiconductor chips (the first semiconductor chip 11 and the second semiconductor chip 12) are bonded by using the chip bonding alignment structure 100 for alignment to form the bonded chip structure 10.

[0060] Since the etching stop layer 104 is formed on the metal layer 110 before the high-pressure annealing step 105, the definition of the metal alignment pattern 110p in the metal layer 110 is improved, which is beneficial to the accurate alignment of the chip bonding. In addition, the metal hillock 106 is covered by the dielectric barrier layer 107, which prevents the diffusion of metal ions in the metal hillock 106 to the bonding intermediate layer (including the silicon oxide layer 108 and the silicon carbonitride layer 109), and affects the performance and reliability of the bonded chip structure 10 or other elements formed subsequently. Therefore, the alignment accuracy of the chip bonding manufacturing process is improved, and the manufacturing process yield and quality of the bonded chip structure 10 are improved.

[0061] Although the present application is disclosed in connection with the above preferred embodiments, it will be understood that it is not intended to limit the application and that changes and modifications can be suggested to one skilled in the art, and it is intended that the present application encompass such changes and modifications as fall within the scope of the appended claims.

Claims

1. A die bonding alignment structure, characterized by, comprising: a semiconductor chip having a bonding surface; a metal layer on the bonding surface having a metal alignment pattern; an etch stop layer covering the bonding surface and the metal layer; at least one metal bump extending upwardly from the metal layer through the etch stop layer; a dielectric barrier layer covering the etch stop layer and the at least one metal bump; a silicon oxide layer covering the dielectric barrier layer; and a silicon carbon nitride layer covering the silicon oxide layer.

2. The chip bonding alignment structure of claim 1, wherein the metal alignment pattern is a copper alignment pattern and the metal bump is a copper bump.

3. The chip bonding alignment structure of claim 1, wherein the dielectric barrier layer comprises a dielectric material selected from the group consisting of silicon carbon nitride, silicon carbonide, silicon nitride, silicon carbonide with oxygen, and combinations thereof.

4. The chip bonding alignment structure of claim 1, wherein the etch stop layer comprises a dielectric material selected from the group consisting of silicon carbon nitride, silicon nitride, and combinations thereof.

5. A method of fabricating a chip bonding alignment structure, comprising: forming a metal layer on a bonding surface of a semiconductor chip having a metal alignment pattern; forming an etch stop layer covering the bonding surface and the metal layer; performing a high pressure anneal fabrication process to form at least one metal bump extending upwardly from the metal layer through the etch stop layer; forming a dielectric barrier layer covering the etch stop layer and the at least one metal bump; forming a silicon oxide layer covering the dielectric barrier layer; and forming a silicon carbon nitride layer covering the silicon oxide layer.

6. The method of fabricating a chip bonding alignment structure of claim 5, wherein the step of forming the metal layer comprises a copper fabrication process.

7. A bonded chip structure, comprising: a first semiconductor chip having a first bonding surface, comprising: a metal layer on the first bonding surface having a metal alignment pattern; an etch stop layer covering the bonding surface and the metal layer; at least one metal bump extending upwardly from the metal layer through the etch stop layer; a dielectric barrier layer covering the etch stop layer and the at least one metal bump; a silicon oxide layer covering the dielectric barrier layer; and a silicon carbon nitride layer covering the silicon oxide layer; a second semiconductor chip having a second bonding surface facing the first bonding surface; and a via plug electrically connecting a first metal wiring layer in the first semiconductor chip and a second metal wiring layer in the second semiconductor chip.

8. The bonded chip structure of claim 7, wherein the metal alignment pattern is a copper alignment pattern and the metal bump is a copper bump.

9. The bonded chip structure of claim 7, wherein the metal layer is part of the first metal wiring layer.

10. A method of fabricating a bonded chip structure, comprising: forming a metal layer on a first bonding surface of a first semiconductor chip having a metal alignment pattern; forming an etch stop layer covering the first bonding surface and the metal layer; performing a high pressure anneal fabrication process to form at least one metal bump extending upwardly from the metal layer through the etch stop layer; ​ ​ ​ ​ forming a dielectric barrier layer over the etch stop layer and the at least one metal bump; forming a silicon oxide layer over the dielectric barrier layer; forming a silicon carbonitride layer over the silicon oxide layer; bonding a second bonding surface of a second semiconductor chip face-to-face with the first bonding surface; and forming a via plug electrically connecting the first metal wiring layer in the first semiconductor chip and the second metal wiring layer in the second semiconductor chip.

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