Semiconductor structure and its formation method
By constructing discrete fin stacked structures on a substrate and using the gate structure as a mask for etching to form vertically stacked complementary field-effect transistors, the problem of how to improve the performance of semiconductor devices was solved, and the formation of vertically stacked complementary field-effect transistors was realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2020-12-28
- Publication Date
- 2026-05-26
AI Technical Summary
How to form vertically stacked complementary field-effect transistors to improve the performance of semiconductor devices.
A substrate is provided with a discrete fin stacked structure, and a vertically stacked complementary field-effect transistor is formed by etching a mask through a gate structure, including the construction of multiple dielectric and doped layers, and finally the removal of the sacrificial layer to form a vertically stacked complementary field-effect transistor structure.
The formation of vertically stacked complementary field-effect transistors was achieved, improving the performance of the semiconductor structure.
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Figure CN114695261B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] During the fabrication of semiconductor devices, various manufacturing processes are performed, such as film deposition, etch mask creation, patterning, photoresist development, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a semiconductor substrate. Historically, transistors have been microfabrication formed in a plane with wiring / metals formed on it, and thus the transistor is characterized as a two-dimensional (2D) circuit or 2D fabrication. Scaling has greatly increased the number of transistors per unit area in 2D circuits, but as scaling enters the single-digit nanometer semiconductor device fabrication node, scaling is facing greater challenges. Semiconductor device manufacturers have expressed a demand for three-dimensional (3D) semiconductor devices, in which devices, transistors, and standard cells are stacked on top of each other as a means of further scaling.
[0003] 3D complementary field-effect transistor (CFET) devices can include three-dimensionally stacked cells (or standard cells or logic standard cells) where complementary n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) and p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) are positioned on top of each other. This vertical stacking (a stack perpendicular to the working surface of the semiconductor substrate) allows for improved area scaling and wiring congestion for logic standard cells by “folding” the logic cells onto themselves as a three-dimensional design.
[0004] However, forming vertically stacked complementary field-effect transistors will present unique challenges. Summary of the Invention
[0005] The problem addressed by this invention is to provide a method for forming a semiconductor structure for forming vertically stacked complementary field-effect transistors to improve the performance of the formed semiconductor device.
[0006] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
[0007] A substrate is provided, wherein the substrate has a discrete fin stack structure; the fin stack structure includes a first sacrificial material layer, a first fin layer located on the first sacrificial material layer, a second sacrificial material layer located on the first fin layer, and a second fin layer located on the second sacrificial material layer;
[0008] A gate structure spanning the fin stack structure is formed on the substrate;
[0009] The fin stack structure is etched using the gate structure as a mask until the top surface of the first fin layer is exposed, forming a second fin and a second sacrificial layer.
[0010] The first fin layer and the first sacrificial material layer are etched using the second fin, the second sacrificial layer and the gate structure as a mask to form the first fin and the first sacrificial layer;
[0011] A first source / drain doped layer is formed on the substrate on both sides of the first fin and the first sacrificial layer, and the first source / drain doped layer covers the sidewalls of the first fin and the first sacrificial layer.
[0012] A first dielectric layer is formed on the first source / drain doped layer, and the first dielectric layer covers the sidewall of the second sacrificial layer;
[0013] A second source / drain doped layer is formed on the first dielectric layer, and the second source / drain doped layer covers the sidewall of the second fin.
[0014] A second dielectric layer is formed on the second source / drain doped layer, and the second dielectric layer covers the sidewall of the gate structure;
[0015] Remove the first sacrificial layer, the second sacrificial layer, and the gate structure.
[0016] Optionally, the substrate includes a semiconductor substrate, and the step of forming the fin stack structure includes:
[0017] A fin stacked material layer is formed on a semiconductor substrate;
[0018] The fin stack material layer and a portion of the semiconductor substrate are etched to form the fin stack structure and the protrusion structure located below the fin stack structure;
[0019] After forming the fin stack structure and the protrusion structure located below the fin stack structure, a bottom dielectric layer is formed on the semiconductor substrates on both sides of the fin stack structure, and the top surface of the bottom dielectric layer is flush with the top surface of the protrusion structure.
[0020] After the bottom dielectric layer is formed, a gate structure spanning the fin stack structure is formed on the substrate.
[0021] Optionally, after forming the second sacrificial material layer, the method further includes:
[0022] A first barrier layer is formed at the bottom of the second sacrificial layer and a second barrier layer is formed at the top of the second sacrificial material layer.
[0023] Optionally, ion implantation processes are performed on the top and bottom of the second sacrificial material layer, respectively, so that the first barrier layer is formed at the bottom of the second sacrificial layer and the second barrier layer is formed at the top of the second sacrificial layer.
[0024] Optionally, the ions implanted in the ion implantation process are boron ions.
[0025] Optionally, after the first source / drain doped layer is formed, the top surface of the first source / drain doped layer is flush with the top surface of the first barrier layer.
[0026] Optionally, after the first dielectric layer is formed, the top surface of the first dielectric layer is higher than the top surface of the second barrier layer.
[0027] Optionally, the materials of the first sacrificial layer and the second sacrificial layer are silicon doped with phosphorus in situ.
[0028] Optionally, before etching the fin stack structure using the gate structure as a mask, the method further includes:
[0029] A sidewall is formed covering the second sacrificial layer, the second fin, and the sidewall of the gate structure;
[0030] After the sidewalls are formed, the fin stack structure is etched using the sidewalls and the gate structure as a mask until the top surface of the first fin layer is exposed, forming the second fin and the second sacrificial layer.
[0031] Optionally, the top of the gate structure also has a gate etching hard mask layer; after the sidewall is formed, the sidewall covers the sidewall of the gate etching hard mask layer.
[0032] Optionally, after forming the second source / drain doped layer, the method further includes: removing the gate etching hard mask layer;
[0033] After removing the gate etch hard mask layer, the second dielectric layer is formed on the second source / drain doped layer.
[0034] Optionally, the chemical solution used to remove the first sacrificial layer, the second sacrificial layer, and the gate structure is a phosphoric acid solution, and the temperature of the phosphoric acid is 100°C to 250°C.
[0035] This invention also provides a semiconductor structure, the semiconductor structure comprising:
[0036] Base;
[0037] A first fin located above the base, wherein the first fin and the base have a first cavity;
[0038] The first source / drain doped layer is located on the substrate on both sides of the first fin;
[0039] A second fin located above the first fin, with a second cavity between the second fin and the first fin;
[0040] The first dielectric layer located on the first source / drain doped layer;
[0041] A second source / drain doped layer located on the first dielectric layer and on both sides of the second fin;
[0042] The second dielectric layer is located on the second source / drain doped layer.
[0043] Optionally, the substrate includes:
[0044] Semiconductor substrate;
[0045] Multiple discrete protrusion structures are located on the semiconductor substrate, and the protrusion structures are also located below the first fin and the first source / drain doped layer;
[0046] A bottom dielectric layer is located on the semiconductor substrate, and the top surface of the bottom dielectric layer is flush with the top surface of the protrusion structure.
[0047] Optionally, the semiconductor structure further includes:
[0048] A first barrier layer located on the first fin;
[0049] The second barrier layer is located at the bottom of the second fin.
[0050] Optionally, the top surface of the first barrier layer is flush with the top surface of the first source / drain doped layer.
[0051] Optionally, the top surface of the first dielectric layer is higher than the top surface of the second barrier layer.
[0052] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0053] The above-described solution provides a substrate having discrete fin stacked structures. The fin stacked structures include a first sacrificial material layer, a first fin layer on the first sacrificial material layer, a second sacrificial material layer on the first fin layer, and a second fin layer on the second sacrificial material layer. A gate structure is formed on the substrate spanning the fin stacked structures. The fin stacked structures are etched using the gate structure as a mask until the top surface of the first fin layer is exposed, forming a second fin and a second sacrificial layer. The first fin layer and the first sacrificial layer are etched using the second fin, the second sacrificial layer, and the gate structure as a mask. A first sacrificial layer is formed by a sacrificial material layer, forming a first fin and a first sacrificial layer; a first source / drain doped layer is formed on the substrate on both sides of the first fin and the first sacrificial layer, the first source / drain doped layer covering the sidewalls of the first fin and the first sacrificial layer; a first dielectric layer is formed on the first source / drain doped layer, the first dielectric layer covering the sidewalls of the second sacrificial layer; a second source / drain doped layer is formed on the first dielectric layer, the second source / drain doped layer covering the sidewalls of the second fin; a second dielectric layer is formed on the second source / drain doped layer, the second dielectric layer covering the sidewalls of the gate structure; the first sacrificial layer, the second sacrificial layer, and the gate structure are then removed. This approach can form a vertically stacked complementary field-effect transistor structure and can improve the performance of the formed semiconductor structure. Attached Figure Description
[0054] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.
[0055] Figures 2 to 11 This is a schematic diagram of a structure formed by an intermediate step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0056] As the background technology shows, forming vertically stacked complementary field-effect transistors presents unique challenges.
[0057] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure. The method includes: providing a substrate having discrete fin stacked structures; the fin stacked structures including a first sacrificial material layer, a first fin layer on the first sacrificial material layer, a second sacrificial material layer on the first fin layer, and a second fin layer on the second sacrificial material layer; forming a gate structure spanning the fin stacked structures on the substrate; etching the fin stacked structures using the gate structure as a mask until the top surface of the first fin layer is exposed, forming a second fin and a second sacrificial layer; and using the second fin, the second sacrificial layer, and the gate structure as a mask. The first fin layer and the first sacrificial material layer are etched to form the first fin and the first sacrificial layer. A first source / drain doped layer is formed on the substrate on both sides of the first fin and the first sacrificial layer, covering the sidewalls of the first fin and the first sacrificial layer. A first dielectric layer is formed on the first source / drain doped layer, covering the sidewalls of the second sacrificial layer. A second source / drain doped layer is formed on the first dielectric layer, covering the sidewalls of the second fin. A second dielectric layer is formed on the second source / drain doped layer, covering the sidewalls of the gate structure. The first sacrificial layer, the second sacrificial layer, and the gate structure are then removed. This method can form a vertically stacked complementary field-effect transistor structure and can improve the performance of the formed semiconductor structure.
[0058] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention is shown. See also... Figure 1 A method for forming a semiconductor structure may specifically include the following steps:
[0059] Step S101: Provide a substrate having a discrete fin stack structure; the fin stack structure includes a first sacrificial material layer, a first fin layer on the first sacrificial material layer, a second sacrificial material layer on the first fin layer, and a second fin layer on the second sacrificial material layer;
[0060] Step S102: Form a gate structure that spans the fin stack structure on the substrate;
[0061] Step S103: Etch the fin stack structure using the gate structure as a mask until the top surface of the first fin layer is exposed, forming the second fin and the second sacrificial layer;
[0062] Step S104: Using the second fin, the second sacrificial layer, and the gate structure as a mask, etch the first fin layer and the first sacrificial material layer to form the first fin and the first sacrificial layer;
[0063] Step S105: A first source / drain doped layer is formed on the substrate on both sides of the first fin and the first sacrificial layer, the first source / drain doped layer covering the sidewalls of the first fin and the first sacrificial layer;
[0064] Step S106: A first dielectric layer is formed on the first source / drain doped layer, the first dielectric layer covering the sidewall of the second sacrificial layer;
[0065] Step S107: A second source / drain doped layer is formed on the first dielectric layer, the second source / drain doped layer covering the sidewall of the second fin;
[0066] Step S108: Form a second dielectric layer on the second source / drain doped layer, the second dielectric layer covering the sidewall of the gate structure; remove the first sacrificial layer, the second sacrificial layer and the gate structure.
[0067] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0068] See Figure 2 A substrate is provided, the substrate including a semiconductor substrate 100 having a plurality of discrete protrusion structures 101 and fin stack structures (not shown) located on the protrusion structures.
[0069] The semiconductor substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
[0070] In this embodiment, the semiconductor substrate 100 is a silicon semiconductor substrate. In other embodiments, the semiconductor substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The semiconductor substrate may also be other types of semiconductor substrates such as silicon-on-insulator (SiS) or germanium-on-insulator (CHIS). The material of the semiconductor substrate may be suitable for process requirements or easy to integrate.
[0071] In this embodiment, the fin stacked structure includes a first sacrificial material layer 111, a first fin layer 112 located on the first sacrificial material layer, a second sacrificial material layer 113 located on the first fin layer 112, and a second fin layer 114 located on the second sacrificial material layer 113.
[0072] The first sacrificial material layer 111 is used to subsequently form a first sacrificial layer located between the protrusion structure 101 and the first fin. The first sacrificial layer needs to be removed later, therefore the first sacrificial material layer 111 is an easily removable material, and the process of removing the first sacrificial layer causes minimal damage to other film layers. In this embodiment, the material of the first sacrificial material layer 111 is in-situ phosphorus-doped silicon.
[0073] The first fin layer 112 is used for subsequent etching to form the first fin. The first fin 112 is a fin of a first type of transistor. In this embodiment, the first type of transistor is a p-MOSFET, and the material of the first fin layer is silicon (Si). In other embodiments, the first type of transistor can also be an n-MOSFET, and the material of the first fin layer can also be silicon germanide (SiGe).
[0074] The second sacrificial material layer 113 is used for subsequent etching to form a second sacrificial layer located between the first fin and the second fin. The second sacrificial layer needs to be removed subsequently; therefore, the second sacrificial material layer 113 is an easily removable material, and the process of removing the second sacrificial layer causes minimal damage to other film layers. In this embodiment, the material of the second sacrificial material layer 113 is in-situ phosphorus-doped silicon.
[0075] The second fin layer 114 is used for subsequent etching to form the second fin. The second fin is a fin of a second type of transistor, which differs from the first type of transistor. In this embodiment, the second type of transistor is an n-MOSFET, and the material of the second fin layer is SiGe. In other embodiments, the second type of transistor can also be a p-MOSFET, and the material of the second fin layer can also be Si.
[0076] The method of forming the protrusion structure 101 and the fin stack structure includes: providing a semiconductor substrate 100; forming a fin stack material layer (not shown) on the semiconductor substrate 100; etching the fin stack material layer and a portion of the thickness of the semiconductor substrate 100 to form the fin stack structure and the protrusion structure 101 located below the fin stack structure.
[0077] In this embodiment, the step of etching the fin stacked material layer and a portion of the semiconductor substrate 100 includes: forming a patterned mask layer on the fin stacked material layer; and etching the fin stacked material layer and a portion of the semiconductor substrate 100 using the patterned mask layer as a mask to form the fin stacked structure and a protrusion structure 101 located below the fin stacked structure.
[0078] In this embodiment, after forming the second sacrificial material layer 113, the method further includes forming a first barrier material layer 1131 located at the bottom of the second sacrificial material layer 113 and a second barrier material layer 1132 located at the top of the second sacrificial material layer 113.
[0079] The first barrier material layer 1131 is used for subsequent etching of the first barrier layer. The first barrier layer is used to prevent phosphorus ions in the second sacrificial material layer 113 from leaking into the first fin layer.
[0080] The second barrier material layer 1132 is used for subsequent etching of the second barrier layer. The second barrier layer is used to prevent phosphorus ions in the second sacrificial material layer 113 from leaking into the second fin layer.
[0081] The steps of forming the first barrier material layer 1131 and the second barrier material layer 1132 include: performing ion implantation processes on the top and bottom of the second sacrificial material layer 113 respectively, so that the first barrier material layer 1131 is formed at the bottom of the second sacrificial material layer 113, and the second barrier material layer 1132 is formed at the top of the second sacrificial material layer 113.
[0082] In this embodiment, the ions implanted by the ion implantation process are boron ions.
[0083] See Figure 3 A bottom dielectric layer 120 is formed on the semiconductor substrates 100 on both sides of the fin stacked structure.
[0084] The bottom dielectric layer 120 serves to isolate adjacent protruding structures.
[0085] In this embodiment, the material of the bottom dielectric layer 120 is silicon oxide.
[0086] The process for forming the bottom dielectric layer 120 can be atomic layer deposition, chemical vapor deposition, or physical vapor deposition, etc.
[0087] See Figure 4 A gate structure 130 is formed across the fin stack structure.
[0088] In this embodiment, the gate structure 130 is a dummy gate structure, which occupies space for the subsequent formation of a common metal gate structure. The common metal gate structure is a metal gate structure shared by the first type of transistor and the second type of transistor.
[0089] In this embodiment, the pseudo-gate structure is a single-layer structure, comprising only a pseudo-gate electrode layer. In other embodiments, the pseudo-gate structure may also be a multi-layer structure, and accordingly, the pseudo-gate structure may include a gate oxide layer and a pseudo-gate electrode layer located on the gate oxide layer.
[0090] In this embodiment, the material of the dummy gate electrode layer is amorphous silicon (A-Si).
[0091] Specifically, the step of forming the gate structure 130 includes: forming a gate structure material layer on the bottom dielectric layer 120 and the fin stack structure; etching the gate structure material layer to form a gate structure spanning the fin stack structure.
[0092] The step of forming a gate structure material layer on the bottom dielectric layer 120 and the fin stack structure includes: forming a gate structure material layer on the bottom dielectric layer 120 and the sidewalls and top surface of the fin stack structure.
[0093] The step of etching the gate structure material layer includes: forming a patterned etching hard mask layer 135 on the gate structure material layer; using the patterned etching hard mask layer 135 as a mask, etching the gate structure material layer to form the gate structure 130.
[0094] Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure along the cutting line AB. (See also...) Figure 5 The fin stack structure is etched using the gate structure 130 as a mask until the top surface of the first fin layer 112 is exposed, forming the second fin 140 and the second sacrificial layer 145.
[0095] In this embodiment, the process of etching the fin stacked structure using the gate structure 130 as a mask is a dry etching process. In other embodiments, the process of etching the fin stacked structure using the gate structure 130 as a mask can also be a wet etching process.
[0096] In this embodiment, after the gate structure 130 is formed, the etch hard mask layer 135 located on top of the gate structure is retained. Accordingly, the fin stack structure is etched using the gate structure 130 and the etch hard mask layer 135 as masks until the top surface of the first fin layer 112 is exposed, forming the second fin 140 and the second sacrificial layer 145.
[0097] In this embodiment, when a second barrier material layer 1132 is formed on top of the second sacrificial material layer 113, the second barrier material layer 1132 is also etched during the process of etching the fin stacked structure using the gate structure 130 as a mask, so that the second barrier material layer 1132 forms a second barrier layer 1132'.
[0098] See Figure 6 Using the second fin 140, the second sacrificial layer 145 and the gate structure 130 as a mask, the first sacrificial material layer 113 and the first fin layer 112 are etched to form the first fin 150 and the first sacrificial layer 155.
[0099] In this embodiment, the etching process for the first sacrificial material layer 113 and the first fin layer 112 is a dry etching process. In other embodiments, the etching process for the first sacrificial material layer 113 and the first fin layer 112 can also be a wet etching process.
[0100] In this embodiment, when an etching hard mask layer 135 is still retained on top of the gate structure 130, the mask for etching the first sacrificial material layer 113 and the first fin layer 112 also includes the etching hard mask layer 135 located on top of the gate structure 130.
[0101] In this embodiment, when the first barrier material layer 1131 is formed at the bottom of the second sacrificial material layer 113, the first barrier material layer 1131 is also etched during the etching of the first sacrificial material layer 113 and the first fin layer 112, so that the first barrier material layer 1131 forms the first barrier layer 1131'.
[0102] In this embodiment, before etching the first fin layer 113 and the first sacrificial material layer 112 using the second fin 150, the second sacrificial layer 145, and the gate structure 130 as masks, the method further includes forming a sidewall 160 covering the sidewalls of the gate structure 130, the second fin 140, and the second sacrificial layer 145. When the top of the gate structure 130 still retains the etched hard mask layer 135, the sidewall 160 also covers the sidewall or part of the sidewall of the etched hard mask layer 135.
[0103] The sidewall 160 is used to protect the second fin 140, the second sacrificial layer 145, the gate structure 130, and the etching hard mask layer 135 during the subsequent etching of the first sacrificial material layer 113 and the first fin layer 112, so as to reduce the etching loss of the second fin 140, the second sacrificial layer 145, the gate structure 130, and the etching hard mask layer 135, and improve the morphological quality of the formed semiconductor structure.
[0104] In this embodiment, the sidewall 160 is made of silicon nitride. In other embodiments, the sidewall may also be made of silicon oxide, silicon oxynitride, silicon carbide, or carbon.
[0105] The step of forming the sidewall 160 includes: forming a sidewall layer on the sidewall and top of the etched hard mask layer 135, the gate structure 130, the second fin 140, the sidewall of the second sacrificial layer 145, and the first fin layer 112; and removing the sidewall layer on the top of the etched hard mask layer 135 and the first fin layer 112 using a maskless etching process to form the sidewall 160.
[0106] The process for forming the sidewall layer is atomic layer vapor deposition, chemical vapor deposition, or physical vapor deposition, etc.
[0107] See Figure 7 A first source / drain doped layer 170 is formed on the semiconductor substrate 100 on both sides of the first fin 150 and the first sacrificial layer 155, and the first source / drain doped layer 170 covers the sidewalls of the first fin 150 and the first sacrificial layer 155.
[0108] In this embodiment, the step of forming the first source / drain doped layer 170 includes: using the etched hard mask 135 and the sidewall 160 as masks, forming a first epitaxial layer on the substrate 100 on both sides of the first fin 150; and performing a first doping on the first epitaxial layer to form the first source / drain doped layer 170.
[0109] The process for forming the first epitaxial layer includes a first epitaxial growth process.
[0110] In this embodiment, the process of performing the first doping on the first epitaxial layer includes an in-situ doping process. In other embodiments, the process of performing the first doping on the first epitaxial layer further includes ion implantation.
[0111] In this embodiment, the first fin 150 is a p-MOSFET fin, the material of the first epitaxial layer is silicon-germanium, and the doping source for the first doping is boron atoms. In other embodiments, the first doping process is ion implantation, and the doping source is boron ions or BF ions. 2+ ion.
[0112] In this embodiment, after forming the first source / drain doped layer 170, the step of removing the sidewalls 160 is also included.
[0113] The process for removing the sidewall 160 can be a dry etching process or a wet etching process.
[0114] It should be noted that during the removal of the sidewall 160, a portion of the etched hard mask layer 135 is also etched away, leaving only a portion of the etched hard mask layer 135 remaining on the gate structure 130.
[0115] See Figure 8 A first dielectric layer 180 is formed on the first source / drain doped layer 170, and the first dielectric layer 180 covers the sidewall of the second sacrificial layer 115.
[0116] The first dielectric layer 180 serves as an isolation between the second source / drain doped layer subsequently formed thereon and the first source / drain doped layer 170.
[0117] In this embodiment, the material of the first dielectric layer 180 is silicon oxide.
[0118] The step of forming the first dielectric layer 180 includes: forming a first dielectric material layer on the first source / drain doped layer 170 on both sides of the etched hard mask layer 135, the gate structure 130, the second fin 140, the second barrier layer 1132', and the second sacrificial layer 145, wherein the top surface of the first dielectric material layer is flush with the top surface of the etched hard mask layer 135; and etching the first dielectric material layer back so that the top surface of the first dielectric material layer is slightly higher than the top surface of the second barrier layer, thereby forming the first dielectric layer 180.
[0119] It should be noted that the top surface of the first dielectric layer 180 is higher than the top surface of the second barrier layer 1132', which can prevent the second source / drain doped layer subsequently formed thereon from contacting the second barrier layer, thereby avoiding damage to the first fin 150.
[0120] See Figure 9 A second source / drain doped layer 190 is formed on the first dielectric layer 180, and the second source / drain doped layer 190 covers the sidewall of the second fin 140.
[0121] In this embodiment, the step of forming the second source / drain doped layer 190 includes: using the etched hard mask 135, the gate structure 130 and the second fin 150 as masks, forming a second epitaxial layer on the first dielectric layer 180 on both sides of the second fin 140; and performing a second doping on the second epitaxial layer to form the second source / drain doped layer 190.
[0122] The process for forming the second epitaxial layer includes a second epitaxial growth process.
[0123] In this embodiment, the process of performing a second doping on the second epitaxial layer includes an in-situ doping process. In other embodiments, the process of performing a second doping on the second epitaxial layer further includes ion implantation.
[0124] In this embodiment, the formed second fin 140 is a fin of an n-MOSFET, and the material of the second epitaxial layer is silicon phosphide. The dopant source for the first doping is boron ions, arsenic ions, phosphorus atoms, or arsenic atoms.
[0125] See Figure 10 A second dielectric layer 195 is formed on the second source / drain doped layer 190, and the second dielectric layer 195 covers the sidewall of the gate structure 130.
[0126] The second dielectric layer 195 serves as an isolation element between the film layer subsequently formed thereon and the second source / drain doped layer 190.
[0127] In this embodiment, the material of the second dielectric layer 195 is silicon oxide.
[0128] The step of forming the second dielectric layer 195 includes: forming a second dielectric material layer on the second drain doped layer 190 on both sides of the etched hard mask layer 135 and the gate structure 130, wherein the top surface of the second dielectric material layer is flush with the top surface of the etched hard mask layer 135; and etching back the second dielectric material layer so that the top surface of the second dielectric material layer is flush with the top surface of the gate structure 130 to form the second dielectric layer 195.
[0129] In this embodiment, during the process of etching the second dielectric material layer, the etched hard mask layer 135 is etched away together.
[0130] See Figure 11 Remove the first sacrificial layer 155, the second sacrificial layer 145, and the gate structure 130.
[0131] In this embodiment, a wet etching process is used to etch away the first sacrificial layer 155, the second sacrificial layer 145, and the gate structure 130.
[0132] In this embodiment, the chemical solution used in the wet etching process is a phosphoric acid solution (H3PO4). Specifically, the temperature of the phosphoric acid solution is between 100°C and 250°C.
[0133] Accordingly, a semiconductor structure is also provided in this embodiment of the invention.
[0134] Please continue reading Figure 11 The semiconductor structure includes:
[0135] A substrate (not shown); a first fin 150 located above the substrate, having a first cavity (not shown) between the first fin 150 and the substrate; a first source / drain doped layer 170 located on the substrate on both sides of the first fin 150; a second fin 140 located above the first fin 150, having a second cavity (not shown) between the second fin 140 and the first fin 150; a first dielectric layer 180 located on the first source / drain doped layer 170; a second source / drain doped layer 190 located on the first dielectric layer 180, the second source / drain doped layer 190 covering the sidewalls of the second fin 140; and a second dielectric layer 195 located on the second source / drain doped layer.
[0136] In this embodiment, the substrate includes: a semiconductor substrate 100; a plurality of discrete protrusion structures 101 located on the semiconductor substrate 100, the protrusion structures 101 being located below the first fin 150 and the first source / drain doped layer 170; and a bottom dielectric layer 120 located on the semiconductor substrate 100, the top surface of the bottom dielectric layer 120 being flush with the top surface of the protrusion structures 101.
[0137] In this embodiment, the semiconductor structure further includes a first barrier layer 1131' located on the first fin 150 and a second barrier layer 1132' located at the bottom of the second fin 140.
[0138] In this embodiment, the top surface of the first barrier layer 1131' is flush with the top surface of the first source / drain doped layer 170.
[0139] In this embodiment, the top surface of the first dielectric layer 180 is higher than the top surface of the second barrier layer 1132'.
[0140] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate has a discrete fin stack structure; the fin stack structure includes a first sacrificial material layer, a first fin layer located on the first sacrificial material layer, a second sacrificial material layer located on the first fin layer, and a second fin layer located on the second sacrificial material layer; A gate structure spanning the fin stack structure is formed on the substrate; The fin stack structure is etched using the gate structure as a mask until the top surface of the first fin layer is exposed, forming a second fin and a second sacrificial layer. The first fin layer and the first sacrificial material layer are etched using the second fin, the second sacrificial layer and the gate structure as a mask to form the first fin and the first sacrificial layer; A first source / drain doped layer is formed on the substrate on both sides of the first fin and the first sacrificial layer, and the first source / drain doped layer covers the sidewalls of the first fin and the first sacrificial layer. A first dielectric layer is formed on the first source / drain doped layer, and the first dielectric layer covers the sidewall of the second sacrificial layer; A second source / drain doped layer is formed on the first dielectric layer, and the second source / drain doped layer covers the sidewall of the second fin. A second dielectric layer is formed on the second source / drain doped layer, and the second dielectric layer covers the sidewall of the gate structure; Remove the first sacrificial layer, the second sacrificial layer, and the gate structure.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate includes a semiconductor substrate having discrete protrusion structures, and the fin stack structure is located on the protrusion structures; The steps of forming the protrusion structure and the fin stack structure include: Provide semiconductor substrates; A fin stacked material layer is formed on a semiconductor substrate; The fin stack material layer and a portion of the semiconductor substrate are etched to form the fin stack structure and the protrusion structure located below the fin stack structure.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, After forming the fin stacked structure and the protrusion structure located below the fin stacked structure, the method further includes: A bottom dielectric layer is formed on the semiconductor substrates on both sides of the fin stacked structure, and the top surface of the bottom dielectric layer is flush with the top surface of the protrusion structure. After the bottom dielectric layer is formed, a gate structure spanning the fin stack structure is formed on the substrate.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the second sacrificial material layer, the process also includes: A first barrier material layer is formed at the bottom of the second sacrificial material layer and a second barrier material layer is formed at the top of the second sacrificial material layer; During the process of etching the fin stacked structure using the gate structure as a mask, the second barrier material layer is also etched, so that the second barrier material layer forms the second barrier layer. During the etching of the first fin layer and the first sacrificial material layer using the second fin, the second sacrificial layer and the gate structure as a mask, the first barrier material layer is also etched, so that the first barrier material layer forms the first barrier layer.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, Ion implantation processes are performed on the top and bottom of the second sacrificial material layer, respectively, so that the first barrier material layer is formed at the bottom of the second sacrificial material layer, and the second barrier material layer is formed at the top of the second sacrificial material layer.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The ions implanted in the ion implantation process are boron ions.
7. The method for forming a semiconductor structure according to claim 4, characterized in that, After the first source / drain doped layer is formed, the top surface of the first source / drain doped layer is flush with the top surface of the first barrier layer.
8. The method for forming a semiconductor structure according to claim 4, characterized in that, After the first dielectric layer is formed, the top surface of the first dielectric layer is higher than the top surface of the second barrier layer.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The first and second sacrificial layers are made of silicon doped with phosphorus in situ.
10. The method for forming a semiconductor structure according to claim 1, characterized in that, Before etching the fin stack structure using the gate structure as a mask, the process further includes: A sidewall is formed covering the second sacrificial layer, the second fin, and the sidewall of the gate structure; After the sidewalls are formed, the fin stack structure is etched using the sidewalls and the gate structure as a mask until the top surface of the first fin layer is exposed, forming the second fin and the second sacrificial layer.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The gate structure also has a gate etching hard mask layer on top; after the sidewall is formed, the sidewall covers the sidewall of the gate etching hard mask layer.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, After forming the second source / drain doped layer, the method further includes: removing the gate etching hard mask layer; After removing the gate etch hard mask layer, the second dielectric layer is formed on the second source / drain doped layer.
13. The method for forming a semiconductor structure according to claim 1, characterized in that, The chemical solution used to remove the first sacrificial layer, the second sacrificial layer, and the gate structure is a phosphoric acid solution, and the temperature of the phosphoric acid solution is 100°C to 250°C.
14. A semiconductor structure formed by a method for forming a semiconductor structure according to any one of claims 1-13, characterized in that, include: Base; A first fin located above the base, wherein the first fin and the base have a first cavity; A first source / drain doped layer is located on the substrate on both sides of the first fin, and the first source / drain doped layer covers the sidewall of the first fin; A second fin located above the first fin, with a second cavity between the second fin and the first fin; The first dielectric layer located on the first source / drain doped layer; A second source / drain doped layer is located on the first dielectric layer, and the second source / drain doped layer covers the sidewall of the second fin; The second dielectric layer is located on the second source / drain doped layer.
15. The semiconductor structure according to claim 14, characterized in that, The substrate includes: Semiconductor substrate; Multiple discrete protrusion structures are located on the semiconductor substrate, the protrusion structures being located below the first fin and the first source / drain doped layer; A bottom dielectric layer is located on the semiconductor substrate, and the top surface of the bottom dielectric layer is flush with the top surface of the protrusion structure.
16. The semiconductor structure according to claim 14, characterized in that, Also includes: A first barrier layer located on the first fin; The second barrier layer is located at the bottom of the second fin.
17. The semiconductor structure according to claim 16, characterized in that, The top surface of the first barrier layer is flush with the top surface of the first source / drain doped layer.
18. The semiconductor structure according to claim 16, characterized in that, The top surface of the first dielectric layer is higher than the top surface of the second barrier layer.