Stacked die radio frequency circuit and method of packaging the same

Abstract

Various embodiments of die stacking are disclosed to improve the integration and packaging performance of radio frequency circuits. In various arrangements, a first die can be inverted and stacked on a second die through one or more bump pillars disposed between the two dies. Bump pads can be mounted on the first die and / or the second die. The bump pads can include ground bump pads for ground connections, radio frequency signal bump pads for radio frequency signal transmission across the dies, and / or control bump pads for biasing or logic control. Additionally, the ground bump pads and the radio frequency signal pads can form a ground-signal-ground structure to smooth radio frequency signal transmission. Embodiments can integrate silicon-based dies and III-V semiconductor dies together to form small packages with well-defined ground definitions that can handle high power radio frequency signals at millimeter wave frequencies.

Description

Technical Field

[0001] This invention relates generally to radio frequency (RF) circuit structures, and more specifically to stacked die RF circuits. Background Technology

[0002] Radio frequency (RF) or microwave / millimeter-wave frequency circuits typically include dielectric materials, which generate excessive dielectric heat power loss at high RF frequencies. Advanced silicon-based manufacturing processes, such as bulk silicon complementary metal-oxide semiconductor (CMOS), silicon-on-insulator (SOI) CMOS, and silicon-germanium (SiGe) bipolar CMOS (BiCMOS), etc., are used to address this issue at high frequencies (i.e., f... t / f max It is known for its high performance (over 300 GHz) and high integration. The high integration enables the combination of analog / RF / microwave / millimeter-wave circuits and digital circuits in a single chip.

[0003] However, for silicon-based processes, integrating a back-side ground (GND) plane with through-substrate vias is extremely difficult and expensive. Having a well-defined RF ground reference at millimeter-wave frequencies has always been a recognized challenge. Furthermore, for silicon-based technologies, due to the lower breakdown voltage of the devices, it is difficult to output high-power signals (e.g., saturated output power exceeding 15 dBm), especially at millimeter-wave frequencies.

[0004] III-V semiconductors (such as GaAs, GaN, and InP) have been widely used in high-performance millimeter-wave circuits. They can be easily integrated with back-side ground planes featuring through-substrate vias. Due to their higher breakdown voltage compared to silicon-based processes, RF circuits using III-V semiconductors can output high-power signals (saturation output power greater than 15 dBm). However, III-V semiconductor processes are difficult to integrate with digital logic circuits and basic analog circuits, such as operational amplifiers, low-dropout (LDO) regulators, DC-DC level converters, and negative voltage generators. Therefore, the integration level of circuits based on III-V semiconductors is limited.

[0005] Therefore, it is necessary to provide systems and methods for integrating radio frequency (RF) circuits to address the aforementioned problems and improve RF circuit performance. Summary of the Invention

[0006] This invention provides several embodiments of systems and methods for die stacking to improve the integration and packaging performance of radio frequency (RF) circuits. In several listed layouts, a first die may be inverted and stacked on a second die via one or more bump posts coupled between the first and second dies. Bump pads may be provided on the first and / or second dies. The bump pads may include ground bump pads for ground connections, signal bump pads for cross-die RF signal transmission, and / or control bump pads for bias or logic control.

[0007] In one or more embodiments, the first die may be a silicon-based RF chip, including an RF signal path coupled to the second die via at least one signal bump post connected to a corresponding signal bump pad. The second die may be a III-V process semiconductor die such as GaAs / GaN, having a backside ground layer and one or more through-substrate ground vias to provide a well-defined ground reference. Furthermore, the second die may include an RF amplifier with a saturated output power greater than 15 dBm. This integration of the silicon-based die and the III-V process semiconductor die provides a small package with a well-defined ground, enabling the processing of high-power RF signals at millimeter-wave frequencies.

[0008] In one or more embodiments, the first die may include a guard ring, which may be a closed ring or an open ring with at least one opening. The guard ring structure may be connected to one or more ground bump pads on the first die, which are grounded to the back ground layer on the second die via one or more ground bump posts. This ground guard ring also provides a well-defined ground for the first die. Furthermore, the ground bump pads and RF signal bump pads may form ground-signal-ground, ground-signal, or signal-ground pad structures that have characteristic impedances similar to the RF signal paths on the first / second die to achieve smooth RF signal transmission between the first and second dies.

[0009] In one or more embodiments, the first die may further include one or more first die control bump pads, which are respectively connected to the second die control bump pads via corresponding bump posts to form a control / bias interface between the first die and the second die to realize bias or logic control.

[0010] Various layouts of the two stacked dies provide miniaturized RF applications, especially when small size is required or preferred. This stacking structure also provides a well-defined ground reference for both dies. Various embodiments of cross-die RF connection structures, such as ground-signal-ground, ground-signal, or signal-ground pad / pillar structures, facilitate reducing or minimizing RF signal transmission losses between the stacked dies. Attached Figure Description

[0011] The accompanying drawings illustrate exemplary embodiments of the invention for reference, and these drawings are intended to illustrate rather than limit the invention. While the invention has been generally described in the embodiments, this is not intended to limit the scope of the invention to the specific technical features of the described embodiments.

[0012] Figure 1 This is a top view of a first layout of two stacked dies in one or more embodiments of the present invention;

[0013] Figure 2A This is a first cross-sectional view of a first layout of two stacked dies in one or more embodiments of the present invention;

[0014] Figure 2B This is a second cross-sectional view of a first layout of two stacked dies in one or more embodiments of the present invention;

[0015] Figure 3 This is a top view of a second layout of two stacked dies in one or more embodiments of the present invention;

[0016] Figure 4 This is a top view of a third layout of two stacked dies in one or more embodiments of the present invention;

[0017] Figure 5 The present invention illustrates a process flow for forming two stacked die packages in one or more embodiments.

[0018] Those skilled in the art will recognize that various embodiments and examples of the invention can be implemented based on the specification. All such embodiments and examples should be included within the scope of protection of this invention. Detailed Implementation

[0019] In the following description, specific details of the invention will be set forth to facilitate understanding of the invention. However, the invention may be practiced even without some or all of the specific details described. The embodiments of the invention described below may be incorporated into many different electrical components, circuits, devices, and systems. The structures and devices shown in the block diagrams of the accompanying drawings are used to illustrate exemplary embodiments of the invention, but are not intended to obscure the broad guidance of the invention. The connections between elements shown in the drawings are not limited to direct connections. Rather, the connections between elements can be modified, reconfigured, or otherwise altered through intermediate components.

[0020] References to "one embodiment" or "a particular embodiment" in the specification indicate that a specific feature, structure, characteristic, or function related to the embodiment under discussion is included in at least one contemplated embodiment of the invention. Therefore, the phrase "in one embodiment" appearing in different places in the specification does not constitute multiple references to a single embodiment of the invention. Each reference / document mentioned in this patent document is incorporated herein by reference in its entirety. It should be noted that any example provided in this patent is provided by way of illustration, and the implementation of the example is carried out under specific conditions using specific embodiments; therefore, these examples should not be used to limit the scope of disclosure of the present patent document.

[0021] With the development of semiconductor technology, the integration level of radio frequency (RF) circuits is constantly increasing to achieve performance improvements. For silicon-based manufacturing processes, providing a back-side GND plane with integrated through-substrate vias and outputting high-power signals, even if possible, is extremely challenging. For III-V semiconductors, the integration level is limited due to the difficulty in integrating digital logic circuits and basic analog / mixed-signal circuits, such as logic inverters, operational amplifiers (OPAs), low-dropout regulators (LDOs), and analog-to-digital converters (ADCs).

[0022] Several die stacking methods have been proposed for different applications. US Patent 9,929,123B2 discloses a stacking structure including a first die and a second die flip-chip mounted on the first die. The first die has bump pads electrically coupled to both ends of a first capacitor element. The bumps electrically connect the second capacitor element of the second die in parallel with the first capacitor element of the first die. The purpose of this stacking structure is to increase the quality factor of the LC resonant circuit.

[0023] This patent describes embodiments of a die stacking system and method for improving the integration and packaging performance of radio frequency circuits.

[0024]

Example 1

[0025] Figure 1 This is a top view of a first layout of two stacked dies in one or more embodiments of the present invention. Figure 2A and Figure 2B They respectively show along Figure 1Cross-sectional views of lines A-A' and B-B'. The stacked structure 100 includes a first die 110 and a second die 120 coupled together by one or more bump posts for mechanical and electrical connections between the first and second dies. The one or more bump posts may include an RF bump post 130 for RF signal transmission and ground bump posts 132 and 134 for GND connection. The first die 110 may be a flip chip inverted and connected to the second die 120. The first die 110 may be a silicon-based die, and the second die 120 may be a III-V process semiconductor die, such as gallium arsenide (GaAs) or gallium nitride (GaN) die. The III-V process semiconductor die refers to a die manufactured using semiconductor elements from groups III and V of the periodic table as substrate materials.

[0026] In one or more embodiments, the second die 120 includes a backside ground layer 122 and one or more through-substrate ground vias, such as 127 and 129, to provide a well-defined ground reference for the second die 120. The one or more through-substrate ground vias are electrically connected to one or more second die ground bump pads, such as 126 and 128. The first die 110 includes a guard ring 115 electrically connected to one or more first die ground bump pads, such as 116 and 118. When the first die 110 and the second die 120 are stacked together, the one or more first die ground bump pads are electrically connected to corresponding through-substrate ground vias (127 and 129) via corresponding ground bump posts (132 and 134) and second die ground bump pads (126 and 128), thereby grounding the guard ring 115 and providing a well-defined ground reference for the first die.

[0027] In one or more embodiments, the protective ring 115 is an open ring (having at least one opening) or a closed ring that laterally surrounds the first die 110. The protective ring 115 may be constructed from a stacked back-to-end (BEOL) metal structure that extends through a thin film layer 211 (e.g., oxide or SiN), a low-k dielectric layer 212, and a semiconductor layer 213. Figure 2A and Figure 2B As shown, the first die 110 is a flip die and also includes an insulating layer 214 and a wafer substrate 215 located on the semiconductor layer 213.

[0028] Furthermore, the first die ground bump pads 116 and 118 can be disposed on both sides of the RF signal bump pad 114 to form a ground-signal-ground (GSG) pad structure 119, the characteristic impedance of which is matched with the characteristic impedance of the RF signal path 112 for smooth or low-loss RF signal transmission into and out of the first die 110. Through the matched characteristic impedance, a voltage standing wave ratio (VSWR), i.e., the ratio between the transmitted and reflected voltage standing waves, can be achieved to be equal to or less than 2:1 during RF signal transmission. Ground bump post 132 electrically connects the first die ground bump pad 116 to the second die ground bump pad 126. Ground bump post 134 electrically connects the first die ground bump pad 118 to the second die ground bump pad 128. RF bump post 130 electrically connects the RF signal bump pad 114 to the second die signal pad 124. The RF bump pillar 130, and the ground bump pillars 132 and 134, can also form a GSG pillar structure whose characteristic impedance matches that of the GSG pad structure 119. Those skilled in the art will understand that, although... Figure 1 The radio frequency (RF) signal path shown is a straight line, but the RF signal path may include various RF signal processing components, such as RF signal splitters or combiners, and may include various transmission line forms such as microstrip lines, coplanar waveguides (CPWs), or grounded coplanar waveguides (CPWGs). Such variations should also fall within the protection scope of this invention.

[0029] Those skilled in the art should also understand that ground bump pads and RF signal bump pads can form not only GSG pad structures, but also ground-signal (GS) or signal-ground (SG) pad structures. Similarly, ground bump posts and signal bump posts can form GS (or SG) post structures, not just GSG post structures. Such variations should also fall within the scope of protection of this invention.

[0030] In one or more embodiments, the first die 110 may further include one or more first die control bump pads 142, which are respectively connected to the second die control pads 144 via corresponding second die bump posts (located below and connected to the first die control bump pads 142) to form a bias / control interface between the first die 110 and the second die 120 for bias or logic control.

[0031] Various embodiments of the first layout of two stacked dies provide miniaturized RF applications, especially when small size is required or preferred. This type of stacking structure provides a well-defined ground reference for the two dies and the cross-die connection structure to reduce or minimize RF signal transmission losses between the stacked dies. These advantages are beneficial for RF signal processing, particularly RF signals at millimeter-wave frequencies.

[0032]

Example 2

[0033] Figure 3 This is a top view of a second layout of two stacked dies in one or more embodiments of the present invention. The stacked structure 300 includes a first die 310 and a second die 320 coupled together by one or more bump pillars, which may include RF bump pillars for RF signal transmission and ground bump pillars for GND connection. The first die 310 may be a flip chip inverted and connected to the second die 320. The first die 310 may be a silicon-based die, and the second die 320 may be a III-V process semiconductor die, such as a GaAs / GaN die. The second die has a backside ground layer and a through-substrate ground via, such as 326, to provide a well-defined ground reference for the RF signals of the first and second dies.

[0034] The first die 310 may include a guard ring 315 electrically connected to one or more first die ground bump pads, such as 316, which are electrically connected to corresponding through-substrate ground vias, such as 326, via corresponding ground bump posts. Therefore, the guard ring 315 grounding provides a well-defined ground reference for the first die. The first die 310 has a first die signal input bump pad 314 electrically connected to a second die signal input pad 324 via RF input bump posts to enable RF signal transmission. Similar to... Figure 1 , Figure 2A and Figure 2B In the first layout shown, the first die ground bump pad and the first die signal bump pad can form a first GSG (or GS or SG) pad structure 318, the characteristic impedance of which is matched with the characteristic impedance of the first die RF signal path 312 for smooth or low-loss RF signal transmission from the second die to the first die. The first die 310 also has a first die signal output bump pad 317 coupled to the first die RF signal path 312. The first die signal output bump pad 317 is coupled to the second die RF signal path 322 via RF bump posts. The characteristic impedance of the second die RF signal path 322 can be close to the characteristic impedance of the first die RF signal path 312 to achieve smooth or low-loss RF signal transmission. The first die signal output bump pad 317 can also form a second GSG (or GS or SG) pad structure 319 with one or more nearby first die ground bump pads (e.g., 313). This pad structure can be similar to or different from the first GSG (or GS or SG) pad structure 318. For example, as... Figure 3As shown, the first pad structure 318 is a GSG pad structure, while the second pad structure 319 is an SG pad structure. In one or more embodiments, the characteristic impedances of the first pad structure 318 and the second pad structure 319 are matched, for example, having an impedance difference lower than a preset threshold. By matching the characteristic impedances, a VSWR of less than or equal to 2:1 can be achieved during RF signal transmission.

[0035] The second die 320 may be a III-V process semiconductor die, such as a GaAs / GaN die, including an RF amplifier 330 with a saturated output power level greater than 15dBm. The input of the RF amplifier 330 is coupled to the first die RF signal path 312 via the second die RF signal path 322, and its output is coupled to the second die signal output pad 334 to output an amplified RF signal.

[0036] Similar to Figure 1 In the stacked structure 100 and stacked structure 300 shown, the first die 310 may further include one or more first die control bump pads 342, which are respectively connected to the second die control bump pads 344 through corresponding bump posts to form a control interface between the first die 310 and the second die 320 to realize bias or logic control of the two stacked dies.

[0037] Various embodiments of the second layout of two stacked dies provide a solution for miniaturization in RF applications, enabling both dies to have well-defined ground references and handle RF signals at millimeter-wave frequencies. Furthermore, this layout can output high-power RF signals with a saturation output power greater than 15 dBm, making it ideal for RF applications requiring small size and high power output.

[0038]

Example 3

[0039] Figure 4 This is a top view of a third layout of two stacked dies in one or more embodiments of the present invention. The stacked structure 400 includes a first die 410 and a second die 420, which are coupled together by one or more bump posts to achieve mechanical and electrical connections. The first die 410 may be a flip chip inverted and connected to the second die 420. The first die 410 may be a silicon-based die, and the second die 420 may be a III-V process semiconductor die, such as a GaAs / GaN die. The second die 420 has a backside ground layer and a through-substrate ground via, such as 430, to provide a well-defined ground reference for the radio frequency signals of the first and second dies.

[0040] The first die 410 may include control circuitry (e.g., digital logic circuitry or analog bias circuitry) for logic control or biasing of the second die 420. The second die may include radio frequency circuitry 412, such as radio frequency transmission lines, switches, digital attenuators, digital phase shifters, voltage-controlled oscillators, or amplifiers. The first die 410 may also include one or more first die control bump pads 422, which are respectively connected to corresponding second die control bump pads 444 via corresponding bump posts to form a control interface 440 between the first die 410 and the second die 420 to achieve biasing or logic control of the two stacked dies.

[0041] The RF circuit 412 is coupled to the second die signal output pad 434 via the second die RF signal path 422 for RF signal output. In one or more embodiments, the second die signal output pad 434 and at least one second die ground pad (e.g., 436) can form a GSG pad structure 450, the characteristic impedance of which matches the characteristic impedance of the second die RF signal path 422 to minimize RF transmission loss. The second die ground pad 436 can be grounded to the back ground layer via a through-substrate ground via 430.

[0042] In one or more embodiments, the first die 410 may include a guard ring 415 laterally surrounding the first die 410. The guard ring 415 may be electrically floated or grounded via one or more first die grounding bump pads, which are connected to one or more through-substrate grounding vias via corresponding grounding bump posts to provide a well-defined ground reference for the first die. The guard ring 415 may be a closed ring or an open ring including at least one opening.

[0043] Various embodiments of the third layout of two stacked dies can integrate digital logic and / or analog circuitry onto a small-package III-V process semiconductor die, which has a well-defined ground reference and the ability to process radio frequency signals at millimeter-wave frequencies. This type of stacked die structure layout is advantageous for millimeter-wave applications with tight space constraints.

[0044]

Example 4

[0045] Figure 5This invention illustrates a process flow for forming a two-stacked die package according to one or more embodiments. In step 505, a first circuit is fabricated on a first die. The first circuit may include radio frequency (RF) circuitry, digital logic circuitry, or analog bias circuitry. The first die may be a silicon-based die and may include one or more bump pads. In one or more embodiments, the first die may include a guard ring laterally surrounding the first die. The guard ring may be a closed ring or an open ring with at least one opening. In step 510, a second circuit is fabricated on a second die. The second circuit may include RF circuitry, such as an RF transmission line, switch, digital attenuator, digital phase shifter, voltage-controlled oscillator, or RF amplifier. The second die may be a III-V process semiconductor die with a back-side ground plane, such as a GaAs / GaN die. The second die may include one or more bump pads. In one or more embodiments, a GSG (GS or SG) pad structure as shown in a first, second, or third layout may be formed. The characteristic impedance of the GSG pad structure may be matched with the characteristic impedance of the RF signal path in the first or second die to achieve low-loss RF signal transmission. By matching the characteristic impedance, it is possible to achieve a VSWR of less than or equal to 2:1 during radio frequency signal transmission.

[0046] In step 515, one or more bump posts are formed on at least one of the first die and the second die. The one or more bump posts may include one or more ground bump posts for GND connection, one or more radio frequency signal bump posts for cross-die radio frequency signal transmission, and one or more control bump posts for bias or logic control. In one or more embodiments, a GSG (GS or SG) post structure may be formed. The characteristic impedance of the GSG post structure may be matched with the characteristic impedance of the radio frequency signal path in the first die or the second die to achieve low-loss radio frequency signal transmission.

[0047] In step 520, the first die is inverted and stacked on top of the second die to form a stacked structure having one or more bump pillars coupled between the first and second dies. In step 525, the stacked structure is packaged in a plastic or ceramic package, and the pads of the second die are connected to the package pins via leads.

[0048] The invention has been described above to make it clear and understandable, but it is not intended to limit the invention to the precise forms disclosed. Various modifications within the scope of the appended claims and their equivalents are also possible.

[0049] Those skilled in the art should understand that the embodiments and examples described above are exemplary and not intended to limit the scope of protection of the present invention. All substitutions, enhancements, equivalents, combinations, and modifications that are obvious to those skilled in the art after reading the present invention specification and studying the accompanying drawings should fall within the true spirit and scope of protection of the present invention.

[0050] It should also be noted that the elements in each claim can be arranged in different ways, including various dependencies, structures, and combinations. For example, in some embodiments, the subject matter of each claim can be combined with other claims.

Claims

1. A stacked die RF circuit structure, characterized in that, include: The first die includes one or more ground bump pads and a first die radio frequency signal path, wherein the first die radio frequency signal path is coupled to the radio frequency signal bump pads disposed on the first die. The second die includes a second die signal pad, a back ground layer, and one or more through-substrate ground vias; and One or more bump pillars are coupled between the first die and the second die. The one or more bump pillars include one or more ground bump pillars and one or more radio frequency bump pillars. The one or more ground bump pads are grounded to the back ground layer through the one or more ground bump pillars and the one or more through-substrate ground vias. The radio frequency signal bump pads are coupled to the signal pad of the second die through one of the one or more radio frequency bump pillars.

2. The stacked die RF circuit structure according to claim 1, characterized in that, The first die is a silicon-based flip chip die, and the second die is a III-V process semiconductor die.

3. The stacked die RF circuit structure according to claim 1, characterized in that, The first die also includes a protective ring.

4. The stacked die RF circuit structure according to claim 3, characterized in that, The guard ring is a closed loop, and the guard ring is coupled to at least one of the one or more ground bump pads.

5. The stacked die RF circuit structure according to claim 3, characterized in that, The protective ring includes a stacked downstream process metal structure, which extends through a thin film layer, a porous dielectric material layer, and a semiconductor layer.

6. The stacked die RF circuit structure according to claim 1, characterized in that, The one or more ground bump pads include at least one ground bump pad, which is disposed next to the radio frequency signal bump pad to form a pad structure.

7. The stacked die RF circuit structure according to claim 6, characterized in that, The pad structure is a ground-signal-ground pad structure, a ground-signal pad structure, or a signal-ground pad structure, and the characteristic impedance of the pad structure is matched with the characteristic impedance of the first die RF signal path.

8. The stacked die RF circuit structure according to claim 1, characterized in that, The second die also includes a radio frequency amplifier, which is coupled to the radio frequency signal path of the first die through the radio frequency signal path of the second die, and the characteristic impedance of the radio frequency signal path of the second die is matched with the characteristic impedance of the radio frequency signal path of the first die.

9. The stacked die RF circuit structure according to claim 1, characterized in that, The first die has a first circuit fabricated on it, the first circuit including a radio frequency circuit; the second die has a second circuit fabricated on it, the second circuit including a radio frequency circuit.

10. The stacked die RF circuit structure according to claim 1 or 9, characterized in that, A first circuit is fabricated on the first die, the first circuit including a digital logic circuit or an analog bias circuit, and a control interface is formed between the first die and the second die for bias or logic control.

11. The stacked die RF circuit structure according to claim 10, characterized in that, The first die further includes one or more first die control bump pads, which are connected to second die control bump pads via their respective corresponding bump posts to form the control interface located between the first die and the second die.

12. A packaging method for stacked die RF circuits, characterized in that, Includes the following steps: A first radio frequency (RF) circuit is fabricated on a first die. The first RF circuit includes one or more ground pads and RF signal bump pads, the RF signal bump pads being coupled to an RF signal path on the first die. A second radio frequency circuit is fabricated on a second die, the second die including a second die signal pad, a back ground layer, and one or more through-substrate ground vias; Multiple bump posts are formed on the first die or the second die, including one or more ground bump posts and one or more radio frequency bump posts; and The first die is inverted and stacked on the second die through the plurality of bump posts. The one or more ground bump pads are grounded to the back ground layer through the one or more ground bump posts and the one or more through-substrate ground vias. The RF signal bump pads are coupled to the signal pads of the second die through one of the one or more RF bump posts.

13. The packaging method for stacked die RF circuits according to claim 12, characterized in that, It also includes the following steps: The stacked first die and second die are packaged in a plastic or ceramic package, and the pads of the second die are connected to the package pins via leads.

14. The packaging method for stacked die RF circuits according to claim 12, characterized in that, The first die is a silicon-based flip chip die, and the second die is a III-V process semiconductor die.

15. The packaging method for stacked die RF circuits according to claim 12, characterized in that, The first radio frequency circuit includes a guard ring coupled to at least one of the one or more ground bump pads.

16. The packaging method for stacked die RF circuits according to claim 15, characterized in that, The protective ring includes a stacked downstream process metal structure, which extends through a thin film layer, a porous dielectric material layer, and a semiconductor layer.

17. The packaging method for stacked die RF circuits according to claim 12, characterized in that, The one or more ground bump pads include at least one ground bump pad, which is disposed next to the radio frequency signal bump pad to form a pad structure.

18. The packaging method for stacked die RF circuits according to claim 17, characterized in that, The pad structure is a ground-signal-ground pad structure, a ground-signal pad structure, or a signal-ground pad structure, and the characteristic impedance of the pad structure is matched with the characteristic impedance of the radio frequency signal path.

19. The packaging method for stacked die RF circuits according to claim 18, characterized in that, The at least one ground bump pad located next to the radio frequency signal bump pad is coupled to the second die through at least one ground bump post. The at least one ground bump post and the radio frequency bump post constitute a GSG bump post structure, a GS bump post structure, and an SG bump post structure.

20. The packaging method for stacked die RF circuits according to claim 12, characterized in that, The first die is fabricated with digital logic circuits or analog bias circuits, and a control interface is formed between the first die and the second die for bias or logic control.

21. The packaging method for stacked die RF circuits according to claim 20, characterized in that, The first die further includes one or more first die control bump pads, which are connected to second die control bump pads via their respective corresponding bump posts to form the control interface located between the first die and the second die.

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