A silicon controlled static protection device for integrated circuits

Abstract

The application discloses a silicon controlled electrostatic protection device for integrated circuits, which comprises a substrate and a device area arranged on the substrate, the device area comprises an N well and a P well arranged adjacently, the N well is provided with a first N+ injection area, a first P+ injection area and a second P+ injection area, the P well is provided with a second N+ injection area, a third N+ injection area and a third P+ injection area, the device area is further provided with a first polysilicon and a second polysilicon, the first polysilicon, the first P+ injection area, the N well and the second P+ injection area form a PMOS tube, the second polysilicon, the second N+ injection area, the P well and the third N+ injection area form an NMOS tube, the first P+ injection area, the first polysilicon and the second N+ injection area are connected through a metal wire and connected to an electrical anode, the second P+ injection area, the second polysilicon and the third N+ injection area are connected through a metal wire and connected to an electrical cathode, and the first N+ injection area and the third P+ injection area are connected through a metal wire.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electrostatic protection, in particular to a silicon controlled rectifier electrostatic protection device for integrated circuits. BACKGROUND

[0002] Electro-static Discharge (ESD) is a common natural phenomenon in life, the essence of which is the transfer of static electricity between two or more different charged objects, so the charging of objects is the prerequisite for the occurrence of ESD phenomenon. Different types of ESD phenomenon will bring different consequences, which may cause people to feel uncomfortable, or even cause spacecraft failure and casualties.

[0003] The ESD phenomenon occurs in a very short time, so it usually does not cause great harm to people, but in the field of integrated circuits, semiconductor components and chips are very fragile, and ESD will generate a large transient current and transient voltage when it occurs, so ESD will bring great loss to the field of integrated circuits. Especially with the continuous advancement of semiconductor process stages and the continuous increase of integrated circuit scale, the impact of ESD on integrated circuits is becoming more and more significant. The high voltage and large current of ESD may cause irreversible integrated circuit failure such as MOS gate oxide breakdown, device thermal damage, metal interconnection melting failure, etc., and may also cause latch-up effect, device performance degradation, etc. which affect the normal work of the chip. These all show that the ESD protection design of integrated circuits has become an essential research focus in chip design.

[0004] The ESD protection design needs to be realized by a series of ESD protection devices. The most commonly used ESD protection devices are diodes, bipolar transistors (BJT), MOS tubes and silicon controlled rectifiers (SCR). These ESD protection devices have their own advantages and disadvantages, and need to be reasonably selected according to the actual situation. However, in general, ESD protection devices need to meet three conditions of transparency, effectiveness and robustness, that is, the protection device should be in an off state when the integrated circuit is working normally, and should be turned on quickly to discharge the ESD current when the ESD pulse comes. The protection device itself also needs to have a certain resistance to ESD pulses.

[0005] The three basic conditions of transparency, effectiveness and robustness can be concluded from the electrical characteristics that the trigger voltage of the ESD protection device is lower than the breakdown voltage of the protected device, the holding voltage of the protection device is higher than the normal working voltage of the chip, and for safety, there is usually a safety margin of 10-15%, and the secondary failure current of the protection device is high enough. However, with the continuous progress of integrated circuit process and the continuous reduction of device size, the satisfaction of these conditions has become increasingly demanding. For example, the reduction of internal circuit breakdown voltage requires the trigger voltage of the protection device to be reduced, but the reduction speed of the chip working voltage is not so great, making the design window of the ESD protection device become increasingly narrow.

[0006] In the protection of input / output (I / O) pins and power domains of integrated circuit chips, SCR is one of the most commonly used structures. Compared with diodes and MOS tubes, the unit area robustness of SCR is the highest, that is, the layout area occupied by SCR is the smallest to achieve the same protection level. However, SCR also has some shortcomings, such as high trigger voltage and low holding voltage, which makes the traditional SCR structure unable to effectively protect the gate oxide layer of the MOS tube of the integrated circuit input / output terminal. SUMMARY

[0007] To solve the problems in the prior art, the application provides a silicon controlled static protection device for integrated circuits.

[0008] A silicon controlled static protection device for integrated circuits, comprising a substrate and a device region provided on the substrate, the device region comprising an N-well and a P-well arranged adjacent to each other,

[0009] The N-well is provided with a first N+ implantation region, a first P+ implantation region and a second P+ implantation region,

[0010] The P-well is provided with a second N+ implantation region, a third N+ implantation region and a third P+ implantation region,

[0011] The device region is further provided with a first polysilicon and a second polysilicon, the first polysilicon, the first P+ implantation region, the N-well and the second P+ implantation region form a PMOS tube; the second polysilicon, the second N+ implantation region, the P-well and the third N+ implantation region form an NMOS tube;

[0012] The first P+ implantation region, the first polysilicon and the second N+ implantation region are connected by a metal wire and connected to an electrical anode; the second P+ implantation region, the second polysilicon and the third N+ implantation region are connected by a metal wire and connected to an electrical cathode; the first N+ implantation region and the third P+ implantation region are connected by a metal wire.

[0013] Specifically, the electrostatic protection device comprises four current inflow / outflow paths:

[0014] The diode string is formed by the first P+ implantation region, the N well, the first N+ implantation region, the third P+ implantation region, the P well and the third N+ implantation region.

[0015] The PMOS is formed by the first polysilicon, the first P+ implantation region, the N well and the second P+ implantation region.

[0016] The NMOS is formed by the second polysilicon, the second N+ implantation region, the P well and the third N+ implantation region.

[0017] The PNPN thyristor path is formed by the first P+ implantation region, the N well, the P well and the third N+ implantation region.

[0018] When the electrostatic discharge occurs, the diode string formed by the first P+ implantation region, the N well, the first N+ implantation region, the third P+ implantation region, the P well and the third N+ implantation region is first turned on, the current flows from the first P+ implantation region to the N well, then from the N well to the first N+ implantation region, then from the first N+ implantation region to the third P+ implantation region through the metal wire, then from the third P+ implantation region to the P well, and finally from the P well to the third N+ implantation region; as the electrostatic discharge current in the electrostatic protection device gradually increases, the avalanche breakdown occurs between the N well and the second P+ implantation region and between the second N+ implantation region and the P well, the PMOS path formed by the first P+ implantation region, the N well and the second P+ implantation region and the NMOS path formed by the second N+ implantation region, the P well and the third N+ implantation region are turned on; as the electrostatic discharge current in the electrostatic protection device further increases, the avalanche breakdown occurs between the N well and the P well, the PNPN thyristor discharge path formed by the first P+ implantation region, the N well, the P well and the third N+ implantation region is turned on, and a large part of the current is discharged.

[0019] The structure of the embedded diode string and MOS tube can promote the avalanche breakdown between the N well and the P well, reduce the trigger voltage of the electrostatic protection device, and the thyristor discharge path is long, thereby improving the holding voltage of the electrostatic protection device.

[0020] Preferably, the first N+ implantation region, the first P+ implantation region and the second P+ implantation region are sequentially arranged in the N well towards the direction close to the P well; and the second N+ implantation region, the third N+ implantation region and the third P+ implantation region are sequentially arranged in the P well towards the direction away from the N well.

[0021] Preferably, a plurality of isolation grooves for preventing leakage are arranged on the N well and the P well.

[0022] The isolation grooves comprise:

[0023] a first isolation groove arranged between the first N+ implantation region and the first P+ implantation region,

[0024] a second isolation groove arranged between the second P+ implantation region and the second N+ implantation region,

[0025] a third isolation groove arranged between the third N+ implantation region and the third P+ implantation region.

[0026] a fourth isolation groove arranged between the first N+ implantation region and the N-well edge,

[0027] a fifth isolation groove arranged between the third P+ implantation region and the P-well edge.

[0028] Preferably, the first isolation groove, the third isolation groove, the fourth isolation groove and the fifth isolation groove have equal dimensions along the length direction of the substrate,

[0029] the second isolation groove has a dimension along the length direction of the substrate which is 1.5-2.5 times the dimension along the length direction of the substrate of the first isolation groove.

[0030] In particular, each isolation groove is generally a cuboid with a rectangular cross section, which is easy to process and has good anti-creeping effect; the second isolation groove has a dimension along the length direction of the substrate which is generally twice the dimension along the length direction of the substrate of the first isolation groove, and the other dimensions of the second isolation groove are equal to those of the first isolation groove, so the volume of the second isolation groove is twice that of the first isolation groove.

[0031] Preferably, the second isolation groove is arranged at the junction of the N-well and the P-well and partially in the N-well and partially in the P-well.

[0032] In particular, the volume of the second isolation groove in the P-well is equal to that of the second isolation groove in the N-well.

[0033] Preferably, the substrate is a P-type substrate.

[0034] Compared with the prior art, the present application has the following advantages:

[0035] In this structure, the first P+ injection region, N-well, first N+ injection region, third P+ injection region, P-well, and third N+ injection region form a diode string. The first polysilicon, first P+ injection region, N-well, and second P+ injection region form a PMOS. The second polysilicon, second N+ injection region, P-well, and third N+ injection region form an NMOS. That is, the structure with embedded diode string and MOS transistor in the device region can provide initial conduction current to promote avalanche breakdown between N-well and P-well, thereby reducing the trigger voltage of the ESD protection device. Moreover, the first P+ injection region, N-well, P-well, and third N+ injection region form a PNPN thyristor path with a longer discharge path, which improves the sustaining voltage of the ESD protection device. At the same time, four current inflow / outflow paths are formed in the ESD protection device, which significantly enhances the robustness of the ESD protection device. Attached Figure Description

[0036] Figure 1 A schematic diagram of the overall structure of the silicon controlled rectifier electrostatic discharge (SCR) device for integrated circuits provided by the present invention.

[0037] Figure 2 A simulation diagram of the initial discharge path of the thyristor electrostatic discharge protection device for integrated circuits provided by the present invention.

[0038] Figure 3 A simulation diagram of the thyristor discharge path after being turned on in the thyristor electrostatic protection device for integrated circuits provided by the present invention.

[0039] Figure 4 This is a schematic diagram of the test results for the silicon controlled rectifier (SCR) electrostatic discharge (ESD) device for integrated circuits provided by the present invention. Detailed Implementation

[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0041] like Figure 1 As shown, a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device for integrated circuits includes a substrate 10 and a device region disposed on the substrate 10, wherein the device region includes an N-well 20 and a P-well 30 disposed adjacently.

[0042] The substrate 10 is a P-type substrate.

[0043] The N-well 20 is provided with a first N+ injection region 21, a first P+ injection region 22, and a second P+ injection region 23.

[0044] The P-well 30 is provided with a second N+ injection region 31, a third N+ injection region 32, and a third P+ injection region 33.

[0045] The device region is further provided with a first polysilicon 41 and a second polysilicon 42, the first polysilicon 41 and the first P+ implantation region 22, the N well 20 and the second P+ implantation region 23 form a PMOS tube; the second polysilicon 42 and the second N+ implantation region 31, the P well 30 and the third N+ implantation region 32 form an NMOS tube;

[0046] The first P+ implantation region 22, the first polysilicon 41, the second N+ implantation region 31 are connected by metal wires and connected to the electrical anode (Anode); the second P+ implantation region 23, the second polysilicon 42, the third N+ implantation region 32 are connected by metal wires and connected to the electrical cathode (Cathode); the first N+ implantation region 21 and the third P+ implantation region 33 are connected by metal wires.

[0047] Under this structure, the electrostatic protection device includes four current inflow / outflow paths:

[0048] A diode string is formed by the first P+ implantation region 22, the N well 20, the first N+ implantation region 21, the third P+ implantation region 33, the P well 30 and the third N+ implantation region 32;

[0049] A PMOS is formed by the first polysilicon 41, the first P+ implantation region 22, the N well 20, the second P+ implantation region 23;

[0050] An NMOS is formed by the second polysilicon 42, the second N+ implantation region 31, the P well 30 and the third N+ implantation region 32;

[0051] A PNPN thyristor path is formed by the first P+ implantation region 22, the N well 20, the P well 30 and the third N+ implantation region 32;

[0052] The first N+ implantation region 21, the first P+ implantation region 22 and the second P+ implantation region 23 are sequentially arranged in the N well 20 towards the direction close to the P well 30; the second N+ implantation region 31, the third N+ implantation region 32 and the third P+ implantation region 33 are sequentially arranged in the P well 30 towards the direction away from the N well 20.

[0053] The N well 20 and the P well 30 are both provided with a plurality of isolation grooves (STI) for preventing leakage.

[0054] The isolation grooves include:

[0055] A first isolation groove 51 is arranged between the first N+ implantation region 21 and the first P+ implantation region 22,

[0056] A second isolation groove 52 is arranged between the second P+ implantation region 23 and the second N+ implantation region 31,

[0057] A third isolation groove 53 is provided between the third N+ injection region 32 and the third P+ injection region 33.

[0058] A fourth isolation groove 54 is provided between the edge of the first N+ injection region 21 and the N-well 20.

[0059] A fifth isolation groove 55 is located between the edge of the third P+ injection region 33 and the P-well 30.

[0060] The first isolation trench 51, the third isolation trench 53, the fourth isolation trench 54, and the fifth isolation trench 55 have equal dimensions along the length of the substrate 10.

[0061] The dimension of the second isolation trench 52 along the length of the substrate 10 is twice the dimension of the first isolation trench 51 along the length of the substrate 10.

[0062] Each isolation groove is typically a cuboid with a rectangular cross-section. This type of isolation groove is easy to process and has a good anti-leakage effect. The dimension of the second isolation groove 52 along the length of the substrate 10 is typically twice that of the first isolation groove 51. All other dimensions of the second isolation groove 52 are equal to those of the first isolation groove 51. Therefore, the volume of the second isolation groove 52 is twice that of the first isolation groove 51.

[0063] The second isolation groove 52 is located at the connection between N-well 20 and P-well 30, with a portion located in N-well 20 and another portion located in P-well 30.

[0064] The volume of the second isolation groove 52 located in the P-well 30 is equal to the volume of the second isolation groove 52 located in the N-well 20.

[0065] like Figure 2 As shown, when electrostatic discharge occurs, the diode string consisting of the first P+ injection region 22, N-well 20, first N+ injection region 21, third P+ injection region 33, P-well 30, and third N+ injection region 32 is turned on first. Current flows from the first P+ injection region 22 into the N-well 20, then from the N-well 20 into the first N+ injection region 21, and then through the metal wire, the current flows from the first N+ injection region 21 to the third P+ injection region 33, then from the third P+ injection region 33 into the P-well 30, and finally from the P-well 30 into the third N+ injection region 32. As the electrostatic discharge current inside the electrostatic protection device gradually increases, avalanche breakdown occurs between the N-well 20 and the second P+ injection region 23, and between the second N+ injection region 31 and the P-well 30. The PMOS path consisting of the first P+ injection region 22, N-well 20, and second P+ injection region 23, and the NMOS path consisting of the second N+ injection region 31, P-well 30, and third N+ injection region 32 are turned on.

[0066] like Figure 3As shown, as the internal current of the electrostatic discharge protection device further increases, avalanche breakdown occurs between N-well 20 and P-well 30, and the PNPN thyristor discharge path formed by the first P+ injection region 22, N-well 20, P-well 30 and the third N+ injection region 32 is opened, discharging most of the current.

[0067] The structure of embedded diode string and MOSFET provides initial conduction current that can promote avalanche breakdown between N-well 20 and P-well 30, reducing the trigger voltage of the electrostatic discharge device. In addition, the thyristor discharge path is longer, which improves the sustaining voltage of the electrostatic discharge device.

[0068] like Figure 4 The TLP (Transmission Line Pulse) test results shown in the figure indicate that the trigger voltage of the SCR (Silicon Controlled Rectifier) ​​device using the integrated circuit provided in this embodiment is 8.5V and the sustaining voltage is 3.2V. This represents a significant improvement compared to the traditional SCR's high trigger voltage of 16V and sustaining voltage of 2.5V. Furthermore, the failure current of this embodiment is approximately 2.7A, providing protection equivalent to 4KV of HBM (Human Body Model).

Claims

1. A silicon controlled static protection device for integrated circuits comprising a substrate and a device region disposed on the substrate, characterized by, The device region comprises an N well and a P well arranged adjacently, The N well is provided with a first N+ implantation region, a first P+ implantation region and a second P+ implantation region, The P well is provided with a second N+ implantation region, a third N+ implantation region and a third P+ implantation region, The device region is further provided with a first polysilicon and a second polysilicon, the first polysilicon, the first P+ implantation region, the N well and the second P+ implantation region form a PMOS tube; the second polysilicon, the second N+ implantation region, the P well and the third N+ implantation region form an NMOS tube; The first P+ implantation region, the first polysilicon and the second N+ implantation region are connected by a metal wire and connected to an electrical anode; the second P+ implantation region, the second polysilicon and the third N+ implantation region are connected by a metal wire and connected to an electrical cathode; The first N+ implantation region and the third P+ implantation region are connected by a metal wire; When electrostatic discharge occurs, a diode string formed by the first P+ implantation region, the N well, the first N+ implantation region, the third P+ implantation region, the P well and the third N+ implantation region is first turned on, the current flows from the first P+ implantation region to the N well, then from the N well to the first N+ implantation region, then through the metal wire, the current flows from the first N+ implantation region to the third P+ implantation region, then from the third P+ implantation region to the P well, and finally from the P well to the third N+ implantation region; As the current of the electrostatic discharge inside the electrostatic protection device gradually increases, avalanche breakdown occurs between the N well and the second P+ implantation region and between the second N+ implantation region and the P well, the PMOS path formed by the first P+ implantation region, the N well and the second P+ implantation region and the NMOS path formed by the second N+ implantation region, the P well and the third N+ implantation region are opened; as the current inside the electrostatic protection device further increases, avalanche breakdown occurs between the N well and the P well, and the PNPN thyristor discharge path formed by the first P+ implantation region, the N well, the P well and the third N+ implantation region is opened, and a large part of the current is discharged; The initial conduction current provided by the structure of the embedded diode string and MOS tube promotes the avalanche breakdown between the N well and the P well, reduces the trigger voltage of the electrostatic protection device, and the thyristor discharge path is long, which improves the holding voltage of the electrostatic protection device.

2. The silicon controlled static protection device for integrated circuits according to claim 1, wherein The first N+ implantation region, the first P+ implantation region and the second P+ implantation region are sequentially arranged in the N well towards the P well; the second N+ implantation region, the third N+ implantation region and the third P+ implantation region are sequentially arranged in the P well away from the N well.

3. The silicon controlled static protection device for integrated circuits according to claim 2, wherein The N well and the P well are each provided with a plurality of isolation grooves for preventing leakage.

4. The silicon controlled static protection device for integrated circuits according to claim 3, wherein The isolation grooves comprise: a first isolation groove between the first N+ implantation region and the first P+ implantation region, a second isolation groove between the second P+ implantation region and the second N+ implantation region, a third isolation groove between the third N+ implantation region and the third P+ implantation region.

5. The silicon controlled static protection device for integrated circuits according to claim 4, wherein The isolation grooves further comprise: a fourth isolation groove between the first N+ implantation region and the edge of the N well, a fifth isolation groove between the third P+ implantation region and the edge of the P well.

6. The silicon controlled static protection device for integrated circuits according to claim 5, wherein The first isolation groove, the third isolation groove, the fourth isolation groove and the fifth isolation groove have equal dimensions along the length direction of the substrate. The size of the second isolation groove along the length direction of the substrate is 1.5-2.5 times the size of the first isolation groove along the length direction of the substrate.

7. The silicon controlled static protection device for integrated circuits according to claim 4, wherein The second isolation groove is arranged at the connection of the N well and the P well and partially located in the N well and partially located in the P well.

8. The silicon controlled static protection device for integrated circuits according to claim 1, wherein The substrate is a P-type substrate.

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