Memory cell and memory device

Abstract

The present application discloses a storage cell and a storage device. The storage cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to the other side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall facing each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0185964, filed on December 29, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor devices, and more particularly, to a memory cell and a memory device having improved integration. Background Art

[0004] Since the integration of two - dimensional (2D) memory devices is mainly determined based on the area occupied by a unit memory cell, it is affected by fine patterning technology. Fine patterning generally requires very expensive equipment, but there are still limitations in improving the integration of 2D memory devices. To improve the integration, three - dimensional memory devices including memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] Embodiments of the present invention are directed to a memory cell and a memory device having improved integration.

[0006] According to an embodiment of the present invention, a memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to the other side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting the active layer, wherein the word line includes a first notch - shaped sidewall and a second notch - shaped sidewall facing each other.

[0007] According to another embodiment of the present invention, a memory cell includes: a substrate; a bit line extending in a direction perpendicular to the surface of the substrate; a capacitor laterally spaced apart from the bit line; and a transistor located between the bit line and the capacitor, wherein the transistor includes: an active layer extending laterally between the bit line and the capacitor; and a notch - shaped word line and a notch - shaped shielding word line facing each other and having the active layer therebetween.

[0008] According to another embodiment of the present invention, a memory cell includes: a substrate; a bit line extending in a direction perpendicular to the surface of the substrate; a capacitor laterally spaced apart from the bit line; an active layer extending laterally between the bit line and the capacitor; a notch - shaped word line and a notch - shaped shielding word line facing each other and having the active layer therebetween; and a vertical cell isolation layer supporting the notch - shaped word line and the notch - shaped shielding word line and extending in a direction perpendicular to the surface of the substrate.

[0009] According to another embodiment of the present invention, a memory device includes: a substrate; a memory cell array including a plurality of memory cells stacked in a direction perpendicular to the surface of the substrate; and a cell isolation layer extending along the direction in which the memory cells are stacked and supporting the memory cells, wherein each memory cell includes: a bit line extending in a direction perpendicular to the surface of the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally extending between the bit line and the capacitor; and a notch-shaped word line and a notch-shaped mask word line facing each other with the active layer therebetween.

[0010] According to another embodiment of the present invention, a memory cell includes: a substrate; an active layer spaced apart from the surface of the substrate and including a channel extending in a direction parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to the other side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting the active layer, wherein the channel of the active layer includes an arcuate sidewall having a protrusion vertically overlapping the word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a perspective view showing a schematic structure of a memory device according to an embodiment of the present invention.

[0012] Figure 2A is along Figure 1 the cross-sectional view taken along line A-A' shown in

[0013] Figure 2B is along Figure 2A the layout of a single memory cell taken along line B-B' shown in

[0014] Figure 2C is Figure 2A the detailed view of the transistor shown in

[0015] Figure 3 is Figure 2A the detailed layout of the word line shown in

[0016] Figure 4A and 4B are layouts showing a word line according to another embodiment of the present invention.

[0017] Figure 5A is a detailed layout showing a single memory cell according to another embodiment of the present invention.

[0018] Figure 5B is Figure 5A the detailed plan view of the active layer shown in

[0019] Figure 5C is Figure 5A the detailed layout of the word line and the active layer shown in

[0020] Figure 6A and 6B is a perspective view illustrating a memory device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the present disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

[0022] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0023] The drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer is present between the first layer and the second layer or the substrate.

[0024] A memory device according to an embodiment of the present invention may include a plurality of memory cells, and each memory cell may include a lateral active layer, a lateral word line, a vertical bit line, and a lateral capacitor.

[0025] Figure 1 is a perspective view showing a schematic structure of a memory device according to an embodiment of the present invention. Figure 2A is along Figure 1 the cross-sectional view taken along the line A-A' shown in Figure 2B is along Figure 2A the layout of a single memory cell taken along the line B-B' shown in Figure 2C is Figure 2A the detailed view of the transistor shown in

[0026] Referring to Figure 1 , 2A , 2B, and 2C, the memory device 100 may include a plurality of memory cells MC, and the memory cells MC may be located above the substrate LS. The memory cells MC may be vertically stacked from the substrate LS in a first direction D1. The memory cells MC may include memory cells of a dynamic random access memory (DRAM). Each memory cell MC may have a three-dimensional structure.

[0027] Each memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The bit line BL may be vertically oriented along a first direction D1 above a substrate LS. Memory cells MC stacked along the first direction D1 may share the bit line BL. The transistor TR and the capacitor CAP may be positioned in a lateral arrangement from the bit line BL along a second direction D2. The second direction D2 may intersect the first direction D1, and a third direction D3 may intersect the first direction D1 and the second direction D2. The memory cell MC may include a memory cell of a three-dimensional (3D) DRAM having a 1T-1C (1 transistor - 1 capacitor) structure. The transistor TR may include a word line WL. The word line WL may extend along the third direction D3. The third direction may be parallel to the upper surface of the substrate LS. The plate line PL may extend along the third direction D3 while being vertically oriented along the first direction D1. The plate line PL may be coupled to the capacitor CAP.

[0028] The substrate LS may be a material suitable for semiconductor processing, including at least one of, for example, a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed above the substrate LS. The substrate LS may include a semiconductor substrate. The substrate LS may be formed of a material containing silicon. The substrate LS may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof. The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate LS may include a silicon-on-insulator (SOI) substrate.

[0029] The substrate LS may include a peripheral circuit portion PC. The peripheral circuit portion PC may include a plurality of control circuits for controlling the memory cell MC. The peripheral circuit portion PC may be located at a lower plane than the memory cell MC. At least one control circuit of the peripheral circuit portion PC may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion PC may include an address decoder circuit, a read circuit, and a write circuit. At least one control circuit of the peripheral circuit portion PC may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin-type channel transistor (FinFET), etc.

[0030] For example, the peripheral circuit portion PC may include a sense amplifier. The sense amplifier may be coupled to the bit line BL of the memory cell MC. The peripheral circuit portion PC may further include a word line driver, and the word line driver may be coupled to the word line WL of the memory cell MC.

[0031] Although not shown, the plate line PL may be coupled to another peripheral circuit portion or may be coupled to the substrate LS.

[0032] The peripheral circuit portion PC may be located in a plane lower than the memory cell array MCA. Accordingly, the memory device 100 may have a PUC (Peripheral Circuit Under Cell) structure.

[0033] According to another embodiment of the present invention, the memory cell array MCA may be located under the peripheral circuit portion PC. Accordingly, the memory device 100 may have a CUP (Cell Under Peripheral circuit) structure.

[0034] The bottom of the bit line BL may be coupled to the substrate LS. The bit line BL may have a cylindrical shape. The bit line BL may be referred to as a vertically oriented bit line or a columnar bit line. The bit line BL may include a low-resistance conductive material. The bit line BL may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with an N-type impurity or titanium nitride (TiN). The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). The bit line BL may further include an ohmic contact layer, such as a metal silicide. The bit line BL may include columnar tungsten and titanium nitride on the outer wall surrounding the columnar tungsten.

[0035] The bit line contact node BLC may be formed between the bit line BL and the first source / drain region SR. The bit line contact node BLC may surround the bit line BL. The bit line contact node BLC may extend in a first direction D1 perpendicular to the substrate LS. The bit line contact node BLC may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The bit line contact node BLC may include a silicon-based material, a metal-based material, or a combination thereof. The bit line contact node BLC may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line contact node BLC may include polysilicon doped with an N-type impurity (hereinafter referred to as N-type doped polysilicon). According to another embodiment of the present invention, the bit line contact node BLC may include a stack of N-type doped polysilicon and titanium nitride (TiN).

[0036] The transistor TR may include an active layer ACT and a word line WL. The active layer ACT may be laterally oriented in a second direction D2 between a bit line BL and a capacitor CAP. The active layer ACT may extend from the bit line BL to the capacitor CAP. The active layer ACT may include a channel CH, a first source / drain region SR, and a second source / drain region DR. The first source / drain region SR may be coupled to the bit line BL, and the second source / drain region DR may be coupled to the capacitor CAP. The channel CH may be laterally located between the first source / drain region SR and the second source / drain region DR. The word line WL may extend in a third direction D3 and overlap the channel. Two edge portions of the word line WL may respectively overlap the first source / drain region SR and the second source / drain region DR partially. The transistor TR may include a lateral transistor.

[0037] The active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon-germanium-containing layer. For example, the active layer ACT may include doped polysilicon, undoped polysilicon, amorphous silicon, silicon germanium, or a combination thereof. The active layer ACT may include nanowires or nanosheets, and the nanowires and nanosheets may be formed of a semiconductor material.

[0038] According to another embodiment of the present invention, the active layer ACT may include an oxide semiconductor material. According to another embodiment of the present invention, the active layer ACT may include a compound of a transition metal and a chalcogen element. The active layer ACT may include InGaZnO x (IGZO), InSnZnO x , ZnSnO x , MoS2, WS2, or MoSe2. The first source / drain region SR and the second source / drain region DR may be respectively located at two ends of the active layer ACT. For example, the first source / drain region SR and the second source / drain region DR may be formed at two ends of the active layer ACT by ion implantation of impurities or plasma doping.

[0039] The word line WL may include notch-shaped sidewalls facing each other in the second direction D2. For example, Figure 1The word line WL shown includes a plurality of rectangular-shaped notches spaced apart in a third direction D3 in each of its sidewalls. The word line WL may have a linear shape intersecting the upper and lower surfaces of the active layer ACT. The word line WL may include a low-resistance conductive material. The word line WL may include a low-resistance metal material. The word line WL may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The word line WL may include a silicon-based material, a metal-based material, or a combination thereof. The word line WL may include tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbonitride (TaCN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), cobalt (Co), or a combination thereof. The word line WL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the word line WL may include a stack of titanium nitride and tungsten (TiN / W). The word line WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 or less, while the P-type work function material may have a high work function of about 4.5 or greater. The word line WL may include a stack of a barrier material BM and a gate electrode GM. The barrier material BM may include titanium nitride, and the gate electrode GM may include tungsten. The barrier material BM may partially surround the gate electrode GM. For example, the side of the gate electrode GM adjacent to the bit line BL may not be covered by the barrier material BM. The other side of the gate electrode GM adjacent to the capacitor CAP may be covered by the barrier material BM. The upper and lower surfaces of the gate electrode GM may be covered by the barrier material BM.

[0040] According to an embodiment of the present invention, each memory cell MC may include a pair of word lines WL facing each other, with the active layer ACT disposed between the pair of word lines WL. For example, in the pair of word lines WL, the word line WL located above the active layer ACT may be referred to as an upper-level word line, and the word line WL located below the active layer ACT may be referred to as a lower-level word line WL. The pair of word lines WL may be formed of the same material. The pair of word lines WL may have different potentials. For example, in each memory cell MC, a word line drive voltage may be applied to the upper-level word line WL, and a ground voltage may be applied to the lower-level word line WL. The lower-level word line WL may be used to block interference of the upper-level word line WL between the memory cells MC vertically positioned in the first direction D1. The lower-level word line WL may be referred to as a back word line or a shielding word line. According to another embodiment of the present invention, a word line drive voltage may be applied to the lower-level word line WL, and a ground voltage may be applied to the upper-level word line WL. The upper-level word line WL may be used to block interference of the lower-level word line WL between the memory cells MC vertically positioned in the first direction D1. Each of the lower-level word line WL and the upper-level word line WL may include a stack of a barrier material BM and a gate electrode GM. As described above, the word line WL may have a dual word line structure. According to another embodiment of the present invention, a pair of word lines WL may have the same potential.

[0041] The gate dielectric layer GD can be located between the word line WL and the active layer ACT. The gate dielectric layer GD can include silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The gate dielectric layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, and HfSiON, etc.

[0042] Return reference Figure 2C The transistor TR can include an active layer ACT extending along a second direction D2 and word lines WL facing each other and separated by the active layer ACT therebetween. The word line WL can include a stack of a barrier material BM and a gate electrode GM. The active layer ACT can include a first source / drain region SR, a second source / drain region DR, and a channel CH between the first source / drain region SR and the second source / drain region DR. The word line WL and the channel CH can overlap perpendicularly to each other in a first direction D1. The thickness D11 of the channel CH in the first direction D1 can be thinner than the thickness D12 of the second source / drain region DR. The thickness D11 of the channel CH in the first direction D1 can be the same as the thickness D13 of the first source / drain region SR. The channel CH can be referred to as a thin channel or a thin body. The lower surface of the upper-level word line WL can be located on a plane lower than the upper surface of the second source / drain region DR. The upper surface of the lower-level word line WL can be located on a plane higher than the lower surface of the second source / drain region DR.

[0043] Due to the thin channel CH, the distance between the word lines WL becomes closer, and thus, the pitch between the memory cells MC stacked in the first direction D1 can be reduced. When the pitch between the memory cells MC is reduced, the integration degree of the memory cells MC can be increased.

[0044] According to another embodiment of the present invention, the thickness D11 of the channel CH in the first direction D1 can be smaller than the thickness D12 of the second source / drain region DR and the thickness D13 of the first source / drain region SR. In other words, the first source / drain region SR can be thicker than the channel CH and the same as the second source / drain region DR.

[0045] The capacitor CAP can include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN of the capacitor CAP can be coupled to the second source / drain region DR. The plate node PN of the capacitor CAP can be coupled to a plate line PL. The plate node PN and the plate line PL can have an integrated structure.

[0046] The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a dielectric constant higher than that of silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of about 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the above-described high-k materials.

[0047] The dielectric layer DE can be formed of a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconia (ZrO2). The stacked structure including zirconia (ZrO2) can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on zirconia (ZrO2). The ZAZ stack can have a structure in which zirconia (ZrO2), alumina (Al2O3), and zirconia (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack can be referred to as zirconia (ZrO2) base layers. According to another embodiment of the present invention, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnia (HfO2). The stacked structure including hafnia (HfO2) can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can have a structure in which alumina (Al2O3) is stacked on hafnia (HfO2). The HAH stack can have a structure in which hafnia (HfO2), alumina (Al2O3), and hafnia (HfO2) are stacked in sequence. The HA stack and the HAH stack can be referred to as hafnia (HfO2) base layers. In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al2O3) can have a larger bandgap than zirconia (ZrO2) and hafnia (HfO2). Alumina (Al2O3) can have a dielectric constant lower than that of zirconia (ZrO2) and hafnia (HfO2). Thus, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material, and the bandgap of the high-bandgap material is larger than the bandgap of the high-k material. In addition to alumina (Al2O3), the dielectric layer DE can also include silicon dioxide (SiO2) as the high-bandgap material. Since the dielectric layer DE contains the high-bandgap material, leakage current can be suppressed. The high-bandgap material can be very thin. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE can include a laminated structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO3 / Al2O3 / HfO3 / Al2O3 / HfO2). In the above laminated structure, alumina (Al2O3) can be very thin.

[0048] According to another embodiment of the present invention, the dielectric layer DE can include a stacked structure, a laminated structure, or a hybrid structure including zirconia, hafnia, and alumina.

[0049] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0050] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a stack of titanium nitride / tungsten (TiN / W), a stack of tungsten nitride / tungsten (WN / W). The plate node (PN) may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN), silicon germanium may serve as a gap filling material for filling the inside of the cylindrical shape of the storage node SN, while titanium nitride (TiN) may substantially serve as the plate node of the capacitor CAP. Tungsten nitride may be a low-resistance material.

[0051] The storage node SN may have a three-dimensional structure, and the storage node SN having a three-dimensional structure may have a lateral three-dimensional structure parallel to the second direction D2. As an example of the three-dimensional structure, the storage node SN may have a cylindrical shape, a columnar shape, or a column-cylindrical shape. Here, the column-cylindrical shape may refer to a structure combining a columnar shape and a cylindrical shape.

[0052] A part of the storage node SN and a part of the dielectric layer DE may partially cover an edge on one side of the second source / drain region DR.

[0053] The unit isolation layers LIL and VIL can be formed between respective memory cells MC. The unit isolation layers LIL and VIL can include a dielectric material. The unit isolation layers LIL and VIL can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbon oxide (SiCO), silicon carbonitride (SiCN), or a combination thereof. The unit isolation layers LIL and VIL can include a lateral unit isolation layer LIL and a vertical unit isolation layer VIL. The lateral unit isolation layer LIL can extend laterally along the second direction D2, and in this case, it can be located between memory cells MC stacked in the first direction D1. The vertical unit isolation layer VIL can extend vertically along the first direction D1, and in this case, it can be located between memory cells MC adjacent to each other in the third direction D3. The unit isolation layers LIL and VIL can protect the word line WL from collapse and bending. The unit isolation layers LIL and VIL can serve as a support for the sidewalls of the word line WL. The bit line BL can pass through the vertical unit isolation layer VIL. A part of the vertical unit isolation layer VIL can contact one side of the word line WL.

[0054] Figure 3 is Figure 2A the detailed layout of the word line shown in.

[0055] Reference Figure 3 , the word line WL can include a first sidewall SW1 extending in the third direction D3 and a second sidewall SW2 facing the first sidewall SW1. The first sidewall SW1 can include a first flat surface WLP1 and a first recessed surface WLR1. The first flat surface WLP1 and the first recessed surface WLR1 can be alternately repeated in the third direction D3. The first flat surface WLP1 can be a flat sidewall, and the first recessed surface WLR1 can be a recessed sidewall. The first recessed surface WLR1 can have a profile such as a rectangular shape, but other profiles can also be used. Each first flat surface WLP1 can be adjacent to the bit line BL. The first flat surface WLP1 and the bit line BL can be laterally adjacent to each other in the second direction D2. The first recessed surface WLR1 can be spaced apart from the bit line BL. The distance between the first flat surface WLP1 and the bit line BL can be shorter than the distance between the first recessed surface WLR1 and the bit line BL.

[0056] Like the first sidewall SWl, the second sidewall SW2 can include a second flat surface WLP2 and a second recessed surface WLR2. The second flat surface WLP2 and the second recessed surface WLR2 can be alternately repeated in the third direction D3.

[0057] The first flat surface WLP1 and the second flat surface WLP2 can face each other. The first recessed surface WLR1 and the second recessed surface WLR2 can face each other. The distance D1 between the first flat surface WLP1 and the second flat surface WLP2 can be longer than the distance D2 between the first recessed surface WLR1 and the second recessed surface WLR2. The first recessed surface WLR1 and the second recessed surface WLR2 can have a flat shape. For example, each of the first recessed surface WLR1 and the second recessed surface WLR2 can have a rectangular notch shape and they can be symmetric to each other.

[0058] As described above, the word line WL can be a notched word line, and the notches (i.e., the first recessed surface WLRl and the second recessed surface WLR2) provided on the first sidewall SWl and the second sidewall SW2 can be symmetric to each other. A pair of word lines WL can be the same notched word line. The first recessed surface WLR1 and the second recessed surface WLR2 can be supported by the cell isolation layers LIL and VIL.

[0059] By forming the notched word line, the bridging effect occurring between adjacent memory cells can be prevented. In addition, by forming the notched word line, the capacitance between the word lines can be reduced.

[0060] Figure 4A and 4B are diagrams showing the layout of word lines according to another embodiment of the present invention. In Figure 4A and 4B the first flat surface WLP1 and the second flat surface WLP2 can be the same as the first flat surface WLP1 and the second flat surface WPL2 shown in Figure 3 .

[0061] Referring to Figure 4A , the word line WL can include a first sidewall SW1 extending in a third direction D3 and a second sidewall SW2 facing the first sidewall SW1. The first sidewall SW1 can include a first flat surface WLP1 and a first recessed surface WLR1'. The first flat surface WLP1 and the first recessed surface WLR1' can be alternately repeated in the third direction D3. The first flat surface WLP1 can be a flat sidewall, and the first recessed surface WLR1' can be a recessed sidewall. Each first flat surface WLP1 can be positioned adjacent to the bit line BL. Each first flat surface WLP1 can be aligned with the corresponding bit line in a second direction D2, but can not be in contact with the corresponding bit line BL. The cell isolation layer VIL can be disposed between the first flat surface WLP1 and the corresponding bit line. The first flat surface WLP1 and the bit line BL can be laterally adjacent to each other in the second direction D2. The first recessed surface WLR1' can be spaced apart from the bit line BL. The distance between the first flat surface WLP1 and the bit line BL can be shorter than the distance between the first recessed surface WLR1' and the bit line BL.

[0062] Similar to the first sidewall SW1, the second sidewall SW2 may include a second flat surface WLP2 and a second recessed surface WLR2'. The second flat surface WLP2 and the second recessed surface WLR2' may alternately repeat in the third direction D3.

[0063] The first flat surface WLP1 and the second flat surface WLP2 may face each other. The first recessed surface WLR1' and the second recessed surface WLR2' may face each other. The distance between the first flat surface WLP1 and the second flat surface WLP2 may be longer than the distance between the first recessed surface WLR1' and the second recessed surface WLR2'. The first recessed surface WLR1' and the second recessed surface WLR2' may have an arc shape or a curved shape. For example, the first recessed surface WLR1' and the second recessed surface WLR2' may each have a hemispherical notch shape, and they may be symmetric to each other.

[0064] Reference Figure 4B , the word line WL may include a first sidewall SW1 extending in the third direction D3 and a second sidewall SW2 facing the first sidewall SW1. The first sidewall SW1 may include a first flat surface WLP1 and a first recessed surface WLR1". Similar to the first sidewall SW1, the second sidewall SW2 may include a second flat surface WLP2 and a second recessed surface WLR2".

[0065] The first flat surface WLP1 and the second flat surface WLP2 may face each other. The first recessed surface WLR1" and the second recessed surface WLR2" may face each other. The distance between the first flat surface WLP1 and the second flat surface WLP2 may be longer than the distance between the first recessed surface WLR1" and the second recessed surface WLR2". The first recessed surface WLR1" and the second recessed surface WLR2" may have an angled shape. For example, the first recessed surface WLR1" and the second recessed surface WLR2" may each have a triangular notch shape, and they may be symmetric to each other.

[0066] Figure 5A is a detailed layout showing a single memory cell MC' according to another embodiment of the present invention.

[0067] Reference Figure 5A , the memory cell MC' may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL.

[0068] The transistor TR may include: an active layer ACT', which includes a channel CH'; and a first source / drain region SR' and a second source / drain region DR' on both sides of the channel CH'. The transistor TR may further include a word line WL that vertically overlaps the active layer ACT'. The active layer ACT' may extend laterally along a second direction D2. A bit line BL and a bit line contact node BLC may be coupled to one side of the active layer ACT', i.e., the first source / drain region SR'. A capacitor CAP may be coupled to the other side of the active layer ACT', i.e., the second source / drain region DR'.

[0069] The channel CH' may include channel protrusions CHP that are symmetric with each other in a third direction D3. The distance between the channel protrusions CHP may be greater than the lengths of the first source / drain region SR' and the second source / drain region DR' in the third direction D3. The word line WL may extend along the third direction D3 and may vertically overlap the channel CH' of the active layer ACT'.

[0070] Figure 5B is Figure 5A a detailed plan view of the active layer ACT' shown in

[0071] Reference Figure 5B , the active layer ACT' may include first sidewalls S1 to fourth sidewalls S4. The first sidewall S1 and the second sidewall S2 may face each other in the second direction D2, and the third sidewall S3 and the fourth sidewall S4 may face each other in the third direction D3. The first sidewall S1 and the second sidewall S2 may be flat sidewalls, and the third sidewall S3 and the fourth sidewall S4 may be arc-shaped sidewalls or curved sidewalls.

[0072] The third sidewall S3 may include channel protrusions CHP and arc-shaped sub-sidewalls S31 and S32, and the arc-shaped sub-sidewalls S31 and S32 are symmetric with each other and the channel protrusion CHP is located between them.

[0073] The fourth sidewall S4 may include channel protrusions CHP and arc-shaped sub-sidewalls S41 and S42, and the arc-shaped sub-sidewalls S31 and S32 are symmetric with each other and the channel protrusion CHP is located between them.

[0074] The channel protrusions CHP of the third sidewall S3 and the channel protrusions CHP of the fourth sidewall S4 may face each other or be aligned in the third direction D3.

[0075] Figure 5C is Figure 5A a detailed layout of the word line and the active layer shown in Figure 5A a part of an array of memory cells MC' of

[0076] Reference Figure 5CThe word line WL may include a notch-shaped first sidewall SW1 extending along a third direction D3 and a notch-shaped second sidewall SW2 facing the first sidewall SW1. The first sidewall SW1 may include a first flat surface WLP1 and a first recessed surface WLR1. The first flat surface WLP1 and the first recessed surface WLR1 may alternately repeat in the third direction D3. The first flat surface WLP1 may be a flat sidewall, and the first recessed surface WLR1 may be a recessed curved sidewall.

[0077] Similar to the first sidewall SW1, the second sidewall SW2 may include a second flat surface WLP2 and a second recessed surface WLR2. The second flat surface WLP2 and the second recessed surface WLR2 may alternately repeat in the third direction D3.

[0078] The first flat surface WLP1 and the second flat surface WLP2 may face each other. The first recessed surface WLR1 and the second recessed surface WLR2 may face each other. The distance between the first flat surface WLP1 and the second flat surface WLP2 may be longer than the distance between the first recessed surface WLR1 and the second recessed surface WLR2. The first recessed surface WLR1 and the second recessed surface WLR2 may have an arc shape or a curved shape. For example, the first recessed surface WLR1 and the second recessed surface WLR2 may each have a hemispherical notch shape, and they may be symmetric with each other.

[0079] The word line WL and the channel protrusion CHP of the channel CH’ may overlap each other.

[0080] In the above embodiment, an ONPN stack may be used to form an individual memory cell MC. For example, silicon oxide, first silicon nitride, polysilicon, and second silicon nitride may be stacked in sequence, and then the first silicon nitride and the second silicon nitride may be replaced with word lines.

[0081] Figure 6A and 6B is a perspective view showing a memory device according to another embodiment of the present invention.

[0082] Reference Figure 6A and 6B Each of the memory devices 301 and 302 may include a peripheral circuit portion 310 and a memory cell array 320. The memory cell array 320 may include Figure 1 the memory cell array MCA shown. The memory cell array 320 may include a DRAM memory cell array. The memory cell array 320 may include the memory cells MC and MC’ as described above.

[0083] Reference Figure 6A, the memory cell array 320 may be located above the peripheral circuit portion 310. Accordingly, the memory device 301 may have a PUC (Peripheral Circuit Under Memory Cell) structure.

[0084] Reference Figure 6B , the memory cell array 320 may be located below the peripheral circuit portion 310. Accordingly, the memory device 302 may have a CUP (Memory Cell Under Peripheral Circuit) structure.

[0085] The peripheral circuit portion 310 may include, for example, a semiconductor substrate 312 and a sense amplifier 313 disposed on the semiconductor substrate 312. The sense amplifier 313 may include a transistor having the semiconductor substrate 312 as a channel, and the transistor may be a planar channel transistor whose channel is parallel to the surface of the semiconductor substrate 312. In addition to the planar channel transistor, the transistor structure in the sense amplifier 313 may include a recessed channel transistor, a buried gate transistor, and a fin-type channel transistor (FinFET).

[0086] The bit line BL of the memory cell array 320 may be electrically connected to the transistor of the sense amplifier 313. Although not shown, the bit line BL and the transistor of the sense amplifier 313 may be coupled to each other through a multi-level metal line MLM. The multi-level metal line MLM may be formed by a damascene process.

[0087] Although not shown, according to another embodiment of the present invention, each of the memory devices 301 and 302 may include a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate. The memory cell array 320 may be formed on the first semiconductor substrate, and the peripheral circuit portion 310 may be formed on the second semiconductor substrate. Each of the first semiconductor substrate and the second semiconductor substrate may include a conductive pad, and the first semiconductor substrate and the second semiconductor substrate may be bonded through the conductive pads. Accordingly, the memory cell array 320 and the peripheral circuit portion 310 may be electrically connected.

[0088] According to an embodiment of the present invention, a memory device may include transistors and capacitors stacked in three dimensions on a substrate. Accordingly, the integration degree of the memory device may be improved.

[0089] According to an embodiment of the present invention, a mask word line may block interference between memory cells vertically positioned in a memory device.

[0090] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention as defined in the following claims.

Claims

1. A memory cell, comprising: A substrate; An active layer spaced apart from a surface of the substrate and extending in a direction parallel to the surface of the substrate; A bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; A capacitor coupled to the other side of the active layer and spaced apart from the surface of the substrate; And A word line vertically spaced apart from the active layer and extending in a direction intersecting the active layer, Wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall facing each other, Wherein the active layer includes: A channel vertically overlapping the word line; Wherein the channel includes a protrusion protruding in a direction in which the word line extends.

2. The memory cell according to claim 1, wherein, Each of the first notch-shaped sidewall and the second notch-shaped sidewall includes a plurality of flat surfaces and a plurality of recessed surfaces.

3. The memory cell according to claim 2, wherein, The flat surfaces and the recessed surfaces alternate in a direction in which the word line extends.

4. The memory cell according to claim 2, wherein, The flat surfaces are closer to the bit line than the recessed surfaces.

5. The memory cell according to claim 2, wherein, The recessed surfaces include a hemispherical notch shape, a triangular notch shape, or a rectangular notch shape.

6. The memory cell according to claim 1, further comprising: A dielectric support supporting the first notch-shaped sidewall and the second notch-shaped sidewall of the word line.

7. The memory cell according to claim 1, wherein, The active layer further includes: A first source / drain region located on one side of the channel; and A second source / drain region located on the other side of the channel.

8. The memory cell according to claim 1, wherein, The word line has a dual word line structure in which two word lines face each other and the active layer is disposed between the two word lines.

9. The memory cell according to claim 1, wherein, The word line includes a notch-shaped word line and a notch-shaped shielding word line facing each other, and the active layer is disposed between the notch-shaped word line and the notch-shaped shielding word line.

10. A memory device, comprising: A substrate; A memory cell array including a plurality of memory cells stacked in a direction perpendicular to the surface of the substrate; And A cell isolation layer extending in a direction in which the memory cells are stacked and supporting the memory cells, Wherein each of the memory cells includes: A bit line extending in a direction perpendicular to the surface of the substrate; A capacitor laterally spaced apart from the bit line; An active layer extending laterally between the bit line and the capacitor; and A notch-shaped word line and a notch-shaped shielding word line facing each other, and the active layer is located between the notch-shaped word line and the notch-shaped shielding word line, Wherein the active layer includes: A channel vertically overlapping the word line; Wherein the channel includes a protrusion protruding in a direction in which the word line extends.

11. The memory device according to claim 10, wherein, The cell isolation layer includes: A vertical cell isolation layer supporting the notch-shaped word line and the notch-shaped shielding word line and extending in a direction perpendicular to the surface of the substrate.

12. The storage device according to claim 11, wherein, The vertical cell isolation layer directly contacts a notch of the notch-shaped word line and a notch of the notch-shaped shielding word line.

13. The storage device according to claim 11, wherein, The bit line passes through the vertical cell isolation layer.

14. The memory device according to claim 10, wherein, Each of the notch-shaped word line and the notch-shaped shielding word line includes a first notch-shaped sidewall and a second notch-shaped sidewall facing each other, Wherein, the first notch-shaped sidewall is closer to the bit line than the second notch-shaped sidewall, and the second notch-shaped sidewall is closer to the capacitor than the first notch-shaped sidewall.

15. The memory device according to claim 14, wherein, Each of the first notch-shaped sidewall and the second notch-shaped sidewall includes a plurality of flat surfaces and a plurality of recessed surfaces.

16. The memory device according to claim 15, wherein, The flat surfaces and the recessed surfaces alternate in a direction in which the notch-shaped word line and the notch-shaped mask word line extend.

17. The storage device according to claim 15, wherein, The recessed surfaces include a hemispherical notch shape, a triangular notch shape, or a rectangular notch shape.

18. The memory device according to claim 17, wherein, The distance between the flat surface and the bit line is shorter than the distance between the recessed surface and the bit line.

19. The memory device according to claim 10, wherein, The substrate includes a peripheral circuit portion coupled to the bit line, and The peripheral circuit portion is located on a plane higher or lower than the memory cell array.

20. The memory device according to claim 10, wherein, The active layer further includes: A first source / drain region located on one side of the channel; and A second source / drain region located on the other side of the channel.

21. A memory cell, comprising: A substrate; An active layer spaced apart from a surface of the substrate and including a channel extending in a direction parallel to the surface of the substrate; A bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; A capacitor coupled to the other side of the active layer and spaced apart from the surface of the substrate; And A word line vertically spaced apart from the active layer and extending in a direction intersecting the active layer, Wherein, the channel of the active layer includes an arc-shaped sidewall having a protrusion perpendicularly overlapping with the word line, Wherein, the channel includes: A first arc-shaped sidewall having a first protrusion; and A second arc-shaped sidewall having a second protrusion, Wherein, the first arc-shaped sidewall and the second arc-shaped sidewall face each other in a direction in which the word line extends.

22. The memory cell according to claim 21, wherein, The first arc-shaped sidewall includes first arc-shaped sub-sidewalls that are symmetric to each other, and the first protrusion is between the first arc-shaped sub-sidewalls, and The second arc-shaped sidewall includes second arc-shaped sub-sidewalls that are symmetric to each other, and the second protrusion is between the second arc-shaped sub-sidewalls.

23. The memory cell according to claim 21, wherein, The word line includes a first notch-shaped sidewall and a second notch-shaped sidewall facing each other.

24. The memory cell according to claim 23, wherein, Each of the first notch-shaped sidewall and the second notch-shaped sidewall includes a plurality of flat surfaces and a plurality of recessed surfaces.

25. The memory cell according to claim 24, wherein, The flat surfaces and the recessed surfaces alternate in a direction in which the word line extends.

26. The memory cell according to claim 25, wherein, The flat surface is closer to the bit line than the recessed surface.

27. The memory cell according to claim 25, wherein, The recessed surfaces include a hemispherical notch shape, a triangular notch shape, or a rectangular notch shape.

28. The memory cell according to claim 23, further comprising: A dielectric support supporting each of the first notch-shaped sidewall and the second notch-shaped sidewall of the word line.

29. The memory cell according to claim 21, wherein, The word line has a double word line structure in which two word lines face each other perpendicularly, and the active layer is disposed between the two word lines.

30. The memory cell according to claim 21, wherein, The word line includes a notch-shaped word line and a notch-shaped mask word line facing each other perpendicularly, and the active layer is disposed between the notch-shaped word line and the notch-shaped mask word line.

Images