Semiconductor memory devices and their fabrication methods

Abstract

This invention discloses a semiconductor memory element and a method for fabricating the same. The semiconductor memory element includes a substrate comprising a first active region and a second active region adjacent to the first active region; a trench isolation region disposed between the first and second active regions; a source line region disposed in the first active region and adjacent to the trench isolation region; an erase gate disposed on the source line region; a floating gate disposed on a first side of the erase gate; a first control gate disposed on the floating gate; a first character line adjacent to and insulated from the floating gate and the first control gate; a second control gate disposed on a second side of the erase gate and directly on the trench isolation region; and a second character line adjacent to and insulated from the second control gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flash memory device and a method for manufacturing the same. Background Technology

[0002] Flash memory is a type of storage device that can be erased and reprogrammed in blocks. Flash memory consists of a memory array with a large number of memory cells. Each memory cell includes a floating-gate field-effect transistor (FET) capable of retaining charge. The memory cells are typically divided into blocks, and by charging the floating gate, the individual memory cells within a block can be electrically programmed randomly. The data in a memory cell depends on the presence or absence of charge in the floating gate, and the charge can be removed from the floating gate through a block erase operation.

[0003] One problem with conventional flash memory is source line bias error, which is particularly severe in memory architectures with a large number of cells whose sources are connected together via source lines to ground. Parallel sensing of these cells can cause a significant current to flow through the source lines. Because the source lines have resistance, a voltage drop occurs, affecting the accuracy of the sensing operation. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor memory element and its manufacturing method to overcome the shortcomings and disadvantages of the prior art.

[0005] The present invention provides a semiconductor memory element comprising: a substrate including a first active region and a second active region adjacent to the first active region; a trench isolation region disposed between the first active region and the second active region; a source line region disposed in the first active region and adjacent to the trench isolation region; an erase gate disposed on the source line region; a floating gate disposed on a first side of the erase gate; a first control gate disposed on the floating gate; a first character line adjacent to and insulated from the floating gate and the first control gate; a second control gate disposed on a second side of the erase gate and located on the trench isolation region; and a second character line adjacent to and insulated from the second control gate.

[0006] According to an embodiment of the present invention, the semiconductor memory element further includes: a first drain doped region disposed in the first active region and adjacent to the first character line.

[0007] According to an embodiment of the present invention, the semiconductor memory element further includes: a second drain doped region disposed in the second active region and adjacent to the second character line.

[0008] According to an embodiment of the present invention, the semiconductor memory element further includes: a heavily doped region disposed in the first active region and located directly below the first character line.

[0009] According to an embodiment of the present invention, the heavily doped region is connected to the first drain doped region and spaced apart from the source line region.

[0010] According to an embodiment of the present invention, the heavily doped region, the first drain doped region, and the source line region are N-type doped regions. + Doped region.

[0011] According to an embodiment of the present invention, the semiconductor memory element further includes: an erase gate contact, which is disposed directly above the erase gate.

[0012] According to an embodiment of the present invention, the first active region and the second active region extend along a first direction, and the source line region, the erase gate, the first character line and the second character line extend along a second direction.

[0013] According to an embodiment of the present invention, the first direction is orthogonal to the second direction.

[0014] According to an embodiment of the present invention, the erase gate is a T-shaped erase gate, and a apex corner of the floating gate points to an inner corner of the T-shaped erase gate.

[0015] Another aspect of the present invention provides a method for fabricating a semiconductor memory element, comprising: providing a substrate, the substrate including a first active region and a second active region adjacent to the first active region; forming a trench isolation region between the first active region and the second active region; forming a floating gate on the first active region; forming a first control gate on the floating gate and forming a second control gate on the trench isolation region; performing a first ion implantation process to form a source line region adjacent to the trench isolation region in the first active region, and to form a heavily doped region separated from the source line region in the first active region; forming an erase gate on the source line region; forming a first character line adjacent to the floating gate and the first control gate; and forming a second character line adjacent to the second control gate.

[0016] According to an embodiment of the present invention, after forming the second character line adjacent to the second control gate, the method further includes: performing a second ion implantation process to form a first drain doped region adjacent to the first character line in the first active region, and to form a second drain doped region adjacent to the second character line in the second active region.

[0017] According to an embodiment of the present invention, the heavily doped region is connected to the first drain doped region.

[0018] According to an embodiment of the present invention, the heavily doped region, the first drain doped region, and the source line region are N-type doped regions. + Doped region.

[0019] According to an embodiment of the present invention, the method further includes: forming an erase gate contact directly above the erase gate.

[0020] According to an embodiment of the present invention, the first active region and the second active region extend along a first direction, while the source line region, the erase gate, the first character line and the second character line extend along a second direction.

[0021] According to an embodiment of the present invention, the first direction is orthogonal to the second direction.

[0022] According to an embodiment of the present invention, the erase gate is a T-shaped erase gate, and a apex corner of the floating gate points to an inner corner of the T-shaped erase gate.

[0023] According to an embodiment of the present invention, the method further includes: forming an oxide-nitride-oxide (ONO) dielectric layer between the floating gate and the first control gate.

[0024] According to an embodiment of the present invention, after forming the first control gate on the floating gate and forming the second control gate on the trench isolation region, the method further includes: forming a first gap wall on a sidewall of the first control gate and forming a second gap wall on a sidewall of the second control gate. Attached Figure Description

[0025] Figure 1 This is a partial layout diagram of the semiconductor memory elements shown in the embodiments of the present invention;

[0026] Figure 2 It is along Figure 1 A schematic cross-sectional view shown by the tangent line I-I';

[0027] Figures 3 to 8 This is a schematic diagram illustrating a method for manufacturing a semiconductor memory element according to an embodiment of the present invention.

[0028] Explanation of main component symbols

[0029] 1. Semiconductor memory device

[0030] 100 base

[0031] 100a main surface

[0032] 120 Contact Etching Stop Layer

[0033] 140 interlayer dielectric layers

[0034] 200 storage units

[0035] 300 source line pullback component

[0036] 400 First Ion Implantation Fabrication Process

[0037] 500 Second Ion Implantation Fabrication Process

[0038] AA, AAPD active (active) region

[0039] AA-1 First Active Zone

[0040] AA-2 Second Active Zone

[0041] CD dielectric layer

[0042] CG control gate

[0043] CG-1 First Control Gate

[0044] CG-2 Second Control Gate

[0045] CH Channel Area

[0046] CT metal contact

[0047] CT-1 First Drain Contact

[0048] CT-2 Second Drain Contact

[0049] CT-EG gate contact erasure

[0050] D drain region

[0051] D-1 First Drain Doped Region

[0052] D-2 Second Drain Doped Region

[0053] ED (Electronic Dielectric Layer Erasure)

[0054] EG gate erasure

[0055] EGS (Eraser Gate Interconnect Layer)

[0056] FD floating gate dielectric layer

[0057] FG Floating Gate

[0058] FGP Floating Gate Polysilicon Layer

[0059] HDR heavily doped region

[0060] IC internal angle

[0061] IPD dielectric layer

[0062] S source region

[0063] SL source pole region

[0064] SP gap wall

[0065] SP-1 First gap wall

[0066] SP-2 Second Spacer Wall

[0067] STI, STI-1 trench isolation zone

[0068] TC apex

[0069] TS1, TS2 top surface

[0070] WD gate dielectric layer

[0071] WL character line

[0072] WL-1 First character line

[0073] WL-2 Second character line Detailed Implementation

[0074] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0075] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0076] Please see Figure 1 and Figure 2 ,in, Figure 1 This is a partial layout diagram of semiconductor memory element 1 drawn according to an embodiment of the present invention. Figure 2 It is along Figure 1 A schematic cross-sectional view shown by the tangent line I-I'. Figure 1 As shown, on substrate 100, for example, a P-type doped silicon substrate, a plurality of active regions AA extending along a first direction, such as a reference X-axis direction, and active regions AAPD located between the plurality of active regions AA, wherein the active regions AAPD also extend along the reference X-axis direction. A source line region SL extends along a second direction or a reference Y-axis direction, intersecting with the active regions AA and AAPD. According to an embodiment of the present invention, the first direction and the second direction are orthogonal. A trench isolation region STI is provided between the active regions AA and AAPD. According to an embodiment of the present invention, the active regions AAPD are discontinuous in the reference X-axis direction.

[0077] According to an embodiment of the present invention, multiple memory cells 200 are respectively disposed on multiple active regions AA, for example, a so-called embedded super flash 3rd generation (ESF3) structure. According to an embodiment of the present invention, for example, the memory cell 200 may include a source region S, for example, N + The source doped region includes an erase gate EG directly above it, a control gate CG adjacent to the erase gate EG, a floating gate FG located directly below the control gate CG, a character line WL adjacent to the control gate CG and the floating gate FG, and a drain region D located next to the character line WL. For example, N... + The drain doped region, in which the erase gate EG, control gate CG, and character line WL all extend along the reference Y-axis direction. According to an embodiment of the invention, the source region S of the memory cell 200 is electrically connected to the source line region SL. Typically, the memory cell 200 has a mirror-symmetric structure with respect to the source line region SL. Since the ESF3 structure is a well-known technology, its details will not be elaborated further.

[0078] As mentioned earlier, a problem with conventional flash memory is source line bias error, which is particularly severe in memory architectures with a large number of memory cells whose sources are connected together via source lines to ground. Parallel sensing of these memory cells can cause a large current to flow through the source lines. Because the source lines have resistance, a voltage drop occurs, affecting the accuracy of the sensing operation. The semiconductor memory element 1 disclosed in this invention specifically solves the problems of the prior art described above.

[0079] like Figure 1 and Figure 2As shown, the semiconductor memory element 1 includes a source line pull-back (SLPD) element 300 disposed on the active region AAPD. According to an embodiment of the present invention, the active region AAPD extending along a first direction or a reference X-axis direction includes a first active region AA1 and a second active region AA2 adjacent to the first active region AA-1, a trench isolation region STI-1 that isolates the first active region AA-1 and the second active region AA-2, a source line region SL disposed in the first active region AA-1 and adjacent to the trench isolation region STI-1, an erase gate EG disposed on the source line region SL, a floating gate FG disposed on the first side of the erase gate EG, a first control gate CG-1 disposed on the floating gate FG, a first character line WL-1 adjacent to and insulated from the floating gate FG and the first control gate CG-1, a second control gate CG-2 disposed on the second side of the erase gate EG and located on the trench isolation region STI-1, and a second character line WL-2 adjacent to and insulated from the second control gate CG-2. The first active region AA-1 and the second active region AA-2 extend along a first direction, while the source line region SL, the erase gate EG, the first character line WL-1, and the second character line WL-2 extend along a second direction. According to an embodiment of the present invention, the first direction and the second direction are orthogonal.

[0080] According to an embodiment of the present invention, the semiconductor memory element 1 further includes a first drain doped region D-1 disposed in the first active region AA-1 and adjacent to the first character line WL-1, and a second drain doped region D-2 disposed in the second active region AA-2 and adjacent to the second character line WL-2. According to an embodiment of the present invention, the semiconductor memory element 1 further includes a heavily doped region HDR disposed in the first active region AA-1 and located directly below the first character line WL-1. According to an embodiment of the present invention, the heavily doped region HDR overlaps with and is connected to the first drain doped region D-1 and is spaced apart from the source line region SL. According to an embodiment of the present invention, for example, the heavily doped region HDR, the first drain doped region D-1, and the source line region SL can be N... + Doped region. According to an embodiment of the present invention, a channel region CH is located between the heavily doped region HDR and the source line region SL, wherein the channel region CH is located directly below the floating gate FG. The heavily doped region HDR located directly below the first character line WL-1 can improve the source line voltage drop pull-back efficiency.

[0081] like Figure 2As shown, according to an embodiment of the present invention, the erase gate EG can be a T-shaped erase gate, specifically characterized in that a apex corner TC of the floating gate FG points to an inner corner IC of the T-shaped erase gate to improve erasure efficiency. According to an embodiment of the present invention, for example, a dielectric layer CD, such as an oxide-nitride-oxide (ONO) dielectric layer, can be disposed between the first control gate CG-1 and the floating gate FG, and between the second control gate CG-2 and the trench isolation region STI-1. According to an embodiment of the present invention, for example, a floating gate dielectric layer FD can be disposed between the floating gate FG and the substrate 100. According to an embodiment of the present invention, for example, an erase gate dielectric layer ED can be disposed between the erase gate EG and the substrate 100. According to an embodiment of the present invention, for example, the thickness of the erase gate dielectric layer ED can be greater than that of the floating gate dielectric layer FD, but is not limited thereto. According to an embodiment of the present invention, for example, a dielectric layer IPD can be disposed between the erase gate EG and the floating gate FG. A spacer wall SP may be provided on the sidewall of the first control gate CG-1 so that it can be electrically isolated from the adjacent erase gate EG or the first character line WL-1.

[0082] According to an embodiment of the present invention, the contact etch stop layer 120 can be deposited conformally on the substrate 100, and an interlayer dielectric layer 140 can be disposed on the contact etch stop layer 120. According to an embodiment of the present invention, a plurality of metal contacts CT can be disposed in the interlayer dielectric layer 140 and the contact etch stop layer 120, for example, including a first drain contact CT-1 electrically connected to a first drain doped region D-1, a second drain contact CT-2 electrically connected to a second drain doped region D-2, and an erase gate contact CT-EG electrically connected to the erase gate EG. According to an embodiment of the present invention, the erase gate contact CT-EG can be electrically connected to the erase gate interconnect layer EGS, and then electrically connected to an erase gate voltage through an upper metal interconnect (not shown).

[0083] This invention further reduces the size of the memory array by placing the source line pull-back element 300 directly below the erased gate interconnect layer (EGS). However, those skilled in the art should understand that the source line pull-back element 300 does not necessarily have to be placed directly below the erased gate interconnect layer (EGS).

[0084] Please see Figures 3 to 8 This is a schematic diagram illustrating a method for fabricating a semiconductor memory element according to an embodiment of the present invention, wherein the same regions, layers, materials, and elements are still represented by the same symbols. Figure 3As shown, a substrate 100 is first provided, for example, a p-type doped silicon substrate. The substrate 100 includes a first active region AA-1 and a second active region AA-2 adjacent to the first active region AA-1. A trench isolation region STI-1 is formed between the first active region AA-1 and the second active region AA-2. The upper portion of the trench isolation region STI-1 slightly protrudes from the main surface 100a of the substrate 100. According to an embodiment of the present invention, the first active region AA-1 and the second active region AA-2 are along a first direction (e.g., Figure 1 (Extend the reference X-axis in the middle).

[0085] Next, a floating gate polysilicon layer FGP is formed on the first active region AA-1, wherein the top surface TS1 of the floating gate polysilicon layer FGP is approximately flush with the top surface TS2 of the trench isolation region STI-1. According to an embodiment of the present invention, a floating gate dielectric layer FD may be formed before forming the floating gate polysilicon layer FGP. According to an embodiment of the present invention, the floating gate dielectric layer FD may comprise silicon dioxide, but is not limited thereto.

[0086] like Figure 4 As shown, a first control gate CG-1 is then formed on the floating gate polysilicon layer FGP, and a second control gate CG-2 is formed on the trench isolation region STI-1. Then, the floating gate polysilicon layer FGP is etched using an etching process to define the floating gate FG. According to an embodiment of the present invention, before forming the first control gate CG-1 and the second control gate CG-2, a dielectric layer CD, such as an oxide-nitride-oxide (ONO) dielectric layer, can be formed on the floating gate FG and the trench isolation region STI-1. Subsequently, a first spacer SP-1 can be formed on the sidewall of the first control gate CG-1, and a second spacer SP-2 can be formed on the sidewall of the second control gate CG-2.

[0087] like Figure 5 As shown, a first ion implantation fabrication process 400 is then performed to form a source line region SL adjacent to the trench isolation region STI-1 in the first active region AA-1, and a heavily doped region HDR separated from the source line region SL in the first active region AA-1. According to an embodiment of the present invention, for example, the heavily doped region HDR and the source line region SL can be N... + Doped region.

[0088] like Figure 6As shown, an erase gate EG is then formed on the source line region SL, and a first character line WL-1 adjacent to the floating gate FG and the first control gate CG-1, and a second character line WL-2 adjacent to the second control gate CG-2 are formed. The method for forming the erase gate EG, the first character line WL-1, and the second character line WL-2 may include, but is not limited to, polysilicon deposition and etch-back. A gate dielectric layer WD is formed between the first character line WL-1 and the heavily doped region HDR. The second control gate CG-2 is formed on a portion of the trench isolation region STI-1. According to an embodiment of the present invention, a channel region CH is formed between the heavily doped region HDR and the source line region SL, wherein the channel region CH is located directly below the floating gate FG.

[0089] According to an embodiment of the present invention, the erase gate EG is a T-shaped erase gate, specifically characterized in that a apex corner TC of the floating gate EG points to an inner corner IC of the T-shaped erase gate. According to an embodiment of the present invention, the source line region SL, the erase gate EG, the first character line CG-1, and the second character line CG-2 are along a second direction (e.g., Figure 1 (Extended along the reference Y-axis). According to embodiments of the present invention, for example, the erase gate dielectric layer ED can be formed before forming the erase gate EG. According to embodiments of the present invention, for example, the thickness of the erase gate dielectric layer ED can be greater than that of the floating gate dielectric layer FD, but is not limited thereto.

[0090] like Figure 7 As shown, a second ion implantation fabrication process 500 is then performed, forming a first drain doped region D-1 adjacent to the first character line WL-1 in the first active region AA-1, and a second drain doped region D-2 adjacent to the second character line WL-2 in the second active region AA-2. According to an embodiment of the present invention, the heavily doped region HDR overlaps with the first drain doped region D-1. According to an embodiment of the present invention, the first drain doped region D-1 and the second drain doped region D-2 are N... + Doped region.

[0091] like Figure 8As shown, a contact etch stop layer 120 is then deposited conformally on the substrate 100 using a chemical vapor deposition process, followed by the deposition of an interlayer dielectric layer 140 on the contact etch stop layer 120. Next, a plurality of metal contacts CTs are formed in the interlayer dielectric layer 140 and the contact etch stop layer 120, including, for example, a first drain contact CT-1 electrically connected to a first drain doped region D-1, a second drain contact CT-2 electrically connected to a second drain doped region D-2, and an erase gate contact CT-EG electrically connected to the erase gate EG. For example, the metal contacts CTs can be tungsten metal plugs, but are not limited thereto. According to an embodiment of the present invention, the erase gate contact CT-EG can be electrically connected to the erase gate interconnect layer EGS, and then electrically connected to an erase gate voltage through an upper metal interconnect (not shown).

[0092] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory element, characterized in that, Include: The substrate includes a first active region and a second active region adjacent to the first active region; A trench isolation zone is positioned between the first active zone and the second active zone; The source electrode region is located in the first active region and adjacent to the trench isolation region; The gate is erased and disposed on the source line region; A floating gate is disposed on the first side of the erase gate; A first control gate is disposed on the floating gate; The first character line is adjacent to and insulated from the floating gate and the first control gate; A second control gate is disposed on the second side of the erase gate and located on the trench isolation region; The second character line is adjacent to and insulated from the second control gate; as well as The heavily doped region is located in the first active region and directly below the first character line.

2. The semiconductor memory element according to claim 1, wherein, Also includes: The first drain doped region is disposed in the first active region and adjacent to the first character line.

3. The semiconductor memory element according to claim 2, wherein, Also includes: The second drain doped region is disposed in the second active region and adjacent to the second character line.

4. The semiconductor memory element according to claim 2, wherein, The heavily doped region is connected to the first drain doped region and is separated from the source line region.

5. The semiconductor memory element according to claim 2, wherein, The heavily doped region, the first drain doped region, and the source line region are N. + Doped region.

6. The semiconductor memory element according to claim 1, wherein, Also includes: The erase gate contact is positioned directly above the erase gate.

7. The semiconductor memory element according to claim 1, wherein, The first active region and the second active region extend along a first direction, and the source line region, the erase gate, the first character line and the second character line extend along a second direction.

8. The semiconductor memory element according to claim 7, wherein, The first direction is orthogonal to the second direction.

9. The semiconductor memory element according to claim 1, wherein, The erase gate is a T-shaped erase gate, wherein the apex of the floating gate points to the inner angle of the T-shaped erase gate.

10. A method for manufacturing a semiconductor memory element, comprising: A substrate is provided, the substrate comprising a first active region and a second active region adjacent to the first active region; A trench isolation zone is formed between the first active region and the second active region; A floating gate is formed on the first active region; A first control gate is formed on the floating gate, and a second control gate is formed on the trench isolation region; A first ion implantation process is performed to form a source line region adjacent to the trench isolation region in the first active region, and a heavily doped region separated from the source line region in the first active region. An erase gate is formed on the source line region; Forming a first character line adjacent to the floating gate and the first control gate; and A second character line is formed adjacent to the second control gate. The heavily doped region is located directly below the first character line.

11. The method according to claim 10, wherein, After forming the second character line adjacent to the second control gate, the method further includes: A second ion implantation process is performed to form a first drain doped region adjacent to the first character line in the first active region, and a second drain doped region adjacent to the second character line in the second active region.

12. The method according to claim 11, wherein, The heavily doped region is connected to the first drain doped region.

13. The method according to claim 11, wherein, The heavily doped region, the first drain doped region, and the source line region are N. + Doped region.

14. The method of claim 10, wherein, Also includes: An erase gate contact is formed directly above the erase gate.

15. The method according to claim 10, wherein, The first active region and the second active region extend along a first direction, while the source line region, the erase gate, the first character line, and the second character line extend along a second direction.

16. The method according to claim 15, wherein, The first direction is orthogonal to the second direction.

17. The method according to claim 10, wherein, The erase gate is a T-shaped erase gate, wherein the apex of the floating gate points to the inner angle of the T-shaped erase gate.

18. The method according to claim 10, wherein, Also includes: An oxide-nitride-oxide (ONO) dielectric layer is formed between the floating gate and the first control gate.

19. The method according to claim 10, wherein, After forming the first control gate on the floating gate and the second control gate on the trench isolation region, the method further includes: A first gap wall is formed on the sidewall of the first control gate, and a second gap wall is formed on the sidewall of the second control gate.

Images