Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a first well region of a first conductivity type and a second well region of a second conductivity type disposed in the substrate, wherein the first conductivity type and the second conductivity type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along an interface region between the first well region and the second well region. The first dummy structures each include a first conductive region and a first doped region, and the first doped region is located between the first conductive region and the first well region.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure including dummy structures. BACKGROUND

[0002] Dummy structures are often provided in integrated circuit devices to improve process margin and reduce process variation, so as to obtain more consistent manufacturing results. However, if the dummy structures are not designed properly, they can cause leakage current through the well regions and affect the performance of the integrated circuit devices. SUMMARY

[0003] The present invention provides a semiconductor structure including dummy structures disposed along the junctions of well regions of different conductivity types. In one embodiment, the dummy structures can include a conductive region (e.g., a metal silicide) and a doped region of the same conductivity type as the well region in which the conductive region is disposed. The doped region can increase the barrier for the injection of free carriers (e.g., holes) from the conductive region into the well region, thereby reducing the through-well leakage current. In another embodiment, the dummy structures can also include a dummy diffusion region and a dummy portion completely covering the dummy diffusion region, so as to prevent the dummy diffusion region from forming a conductive region (e.g., a metal silicide), again reducing the through-well leakage current.

[0004] A semiconductor structure according to one embodiment of the present invention includes a substrate, a first well region and a second well region disposed in the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type, the first and second conductivity types being complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction region between the first well region and the second well region, wherein each of the plurality of first dummy structures includes a first conductive region and a first doped region, and the first doped region is disposed between the first conductive region and the first well region.

[0005] A semiconductor structure according to another embodiment of the present invention includes a substrate, a first well region and a second well region disposed in the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type, the first and second conductivity types being complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction region between the first well region and the second well region, wherein each of the plurality of first dummy structures includes a first dummy portion disposed on a first dummy diffusion region. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 、 Figure 1A and Figure 1B is a schematic diagram of a semiconductor structure according to a first embodiment of the present invention, whereinFigure 1 is a partial plan view of a semiconductor structure, Figure 1A and Figure 1B are partial cross-sectional views of the semiconductor structure, respectively;

[0007] Figure 2 , Figure 2A and Figure 2B are schematic views of a semiconductor structure according to a second embodiment of the present application, wherein Figure 2 is a partial plan view of a semiconductor structure, Figure 2A and Figure 2B are partial cross-sectional views of the semiconductor structure, respectively;

[0008] Figure 3 , Figure 3A and Figure 3B are schematic views of a semiconductor structure according to a third embodiment of the present application, wherein Figure 3 is a partial plan view of a semiconductor structure, Figure 3A and Figure 3B are partial cross-sectional views of the semiconductor structure, respectively;

[0009] Figure 4 , Figure 4A and Figure 4B are schematic views of a semiconductor structure according to a fourth embodiment of the present application, wherein Figure 4 is a partial plan view of a semiconductor structure, Figure 4A and Figure 4B are partial cross-sectional views of the semiconductor structure, respectively;

[0010] Figure 5 and Figure 5A are schematic views of a semiconductor structure according to a fifth embodiment of the present application, wherein Figure 5 is a partial plan view of a semiconductor structure, Figure 5A is a partial cross-sectional view of the semiconductor structure.

[0011] Explanation of main element symbols

[0012] 10 substrate

[0013] 20 isolation structure

[0014] 20A first isolation region

[0015] 20B second isolation region

[0016] 20C third isolation region

[0017] 22 interlayer dielectric layer

[0018] 30 contact plug

[0019] 100 first dummy structure

[0020] 102 First Conductive Region

[0021] 104 First Doped Region

[0022] 110 First Virtual Structure

[0023] 112 First Virtual Department

[0024] 114 First Virtual Diffusion Zone

[0025] 116 Metal silicides

[0026] 118 First Doped Region

[0027] 120 First Virtual Structure

[0028] 200 Second Dummy Structure

[0029] 202 Second Conductive Region

[0030] 210 Second Virtual Structure

[0031] 212 Second Virtual Department

[0032] 214 Second Virtual Diffusion Zone

[0033] 216 Metal silicides

[0034] 300 Third Dummy Structure

[0035] 302 Third Conductive Region

[0036] 304 Third Doped Region

[0037] 310 Third Dummy Structure

[0038] 312 Third Virtual Department

[0039] 314 Third Virtual Diffusion Zone

[0040] 316 Metal silicide

[0041] 318 Third Doped Region

[0042] 320 Third Dummy Structure

[0043] 400 Fourth Dummy Structure

[0044] 402 Fourth Conductive Region

[0045] 410 Fourth Dummy Structure

[0046] 412 Fourth Virtual Department

[0047] 414 Fourth Virtual Diffusion Zone

[0048] 416 metal silicide

[0049] 500 fifth dummy structure

[0050] 502 fifth conductive region

[0051] 504 fifth doped region

[0052] 510 fifth dummy structure

[0053] 512 fifth dummy portion

[0054] 514 fifth dummy diffusion region

[0055] 516 metal silicide

[0056] 518 fifth doped region

[0057] 520 fifth dummy structure

[0058] 600 sixth dummy structure

[0059] 602 sixth conductive region

[0060] 610 sixth dummy structure

[0061] 612 sixth dummy portion

[0062] 614 sixth dummy diffusion region

[0063] 616 metal silicide

[0064] 700 active region

[0065] 702 conductive region

[0066] 704 doped region

[0067] 720 well pick-up region

[0068] 722 conductive region

[0069] 724 doped region

[0070] 10A first well region

[0071] 10B second well region

[0072] 10BB middle well region

[0073] 10C third well region

[0074] 10D fourth well region

[0075] BN1 junction region

[0076] BN2 junction region

[0077] BN3 junction region

[0078] D1 first distance

[0079] D2 second distance

[0080] D3 third distance

[0081] DR1 depletion region

[0082] DR2 depletion region

[0083] DR3 depletion region DETAILED DESCRIPTION

[0084] In order to make the above objectives, features and advantages of the present application more comprehensible, specific preferred embodiments along with attached drawings are described in detail below. The attached drawings are schematic and not drawn to scale, and the same or similar features are generally designated with the same reference numerals. The embodiments described herein and the drawings are for reference and illustration only, and are not intended to limit the present application. The scope of the present application is defined by the claims. Those having an equivalent meaning to the claims of the present application should also be included in the scope of the present application.

[0085] Figure 1 、 Figure 1A and Figure 1B is a schematic diagram of a semiconductor structure according to a first embodiment of the present application. Figure 1 is a partial plan view of the semiconductor structure. Figure 1A is a schematic cross-sectional view taken along the X direction of Figure 1 through the first well region 10A, the second well region 10B, the third well region 10C, and the middle well region 10BB. Figure 1B is a schematic cross-sectional view taken along the Y direction of Figure 1 through the first well region 10A and the fourth well region 10D. For simplicity of illustration, Figure 1 some structures such as the active region 700, the interlayer dielectric layer 22, and the contact plug 30 are not shown. Figure 1A Figure 1B Please refer to

[0086] Please refer to Figure 1 ​The semiconductor structure includes a substrate 10, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or the like, but is not limited thereto. The substrate 10 has a first well region 10A and a second well region 10B formed therein. The first well region 10A can include dopants of a first conductivity type and thus have the first conductivity type, and the second well region 10B can include dopants of a second conductivity type and thus have the second conductivity type. The first and second conductivity types are complementary. According to an embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type. In other words, the first well region 10A is a P-type well region and the second well region 10B is an N-type well region. In some embodiments, the second well region 10B can also be referred to as a deep N-well. According to an embodiment of the present application, the second well region 10B is entirely within the first well region 10A, and is surrounded by the first well region 10A on all sides and at the bottom, and the two directly contact each other. Since the first and second well regions 10A and 10B have complementary conductivity types, a depletion region DR1 having a width substantially along the junction BN1 therebetween is formed. The width of the depletion region DR1 is affected by the doping concentrations of the first and second well regions 10A and 10B, and varies with the electric field distribution of the first and second well regions 10A and 10B, which is a feature that can be understood by those skilled in the art. For simplicity of illustration and drawing, the width range of the depletion region DR1 is not shown in the figures. According to an embodiment of the present application, the substrate 10 can have the first conductivity type, such as P-type.

[0087] According to an embodiment of the present application, the semiconductor structure can further include a plurality of first dummy structures 100 disposed in the first well region 10A and adjacent to the second well region 10B, preferably arranged around the first well region 10A along the junction region BN1 between the first and second well regions 10A and 10B.

[0088] According to an embodiment of the present application, the semiconductor structure can further include a plurality of second dummy structures 200 disposed in the first well region 10A and located farther from the second well region 10B than the first dummy structures 100. In other words, some of the first dummy structures 100 are located between the second dummy structures 200 and the second well region 10B.

[0089] According to an embodiment of the present application, the semiconductor structure can further include a third well region 10C and a middle well region 10BB disposed in the second well region 10B. The third well region 10C can include a doping of a first conductivity type and have the first conductivity type, for example, P-type. The middle well region 10BB can include a doping of a second conductivity type and have the second conductivity type, for example, N-type. According to an embodiment of the present application, the third well region 10C and the middle well region 10BB are disposed adjacent to each other and are both entirely disposed in the second well region 10B, surrounded by and in direct contact with the second well region 10B on all sides and the bottom. Since the conductivity type of the third well region 10C is complementary to the conductivity types of the second well region 10B and the middle well region 10BB, a depletion region DR2 is formed substantially along the junction region BN2 of the third well region 10C and the second well region 10B and the middle well region 10BB. The width of the depletion region DR2 is affected by the doping concentrations of the third well region 10C, the second well region 10B and the middle well region 10BB and varies with the electric field distribution of the third well region 10C, the second well region 10B and the middle well region 10BB. For simplicity of illustration and drawing, the range of the width of the depletion region DR2 is not shown in the figure.

[0090] According to an embodiment of the present application, the semiconductor structure can further include a plurality of third dummy structures 300 disposed in the second well region 10B and a plurality of fourth dummy structures 400 disposed in the third well region 10C. The third dummy structures 300 are distributed between the junction region BN1 and the junction region BN2 and are arranged along the junction region BN1 on one side of the first dummy structures 100, in other words, the third dummy structures 300 and the first dummy structures 100 are respectively located on two sides of the junction region BN1. The third dummy structures 300 can also partially surround the third well region 10C and the middle well region 10BB along the junction region BN2.

[0091] According to an embodiment of the present application, the semiconductor structure can further include a fourth well region 10D disposed in the substrate 10 and adjacent to the first well region 10A. The fourth well region 10D can include a doping of a second conductivity type and have the second conductivity type, for example, N-type, in other words. The fourth well region 10D is an N-type well region. Since the conductivity type of the first well region 10A is complementary to the conductivity type of the fourth well region 10D, a depletion region DR3 is formed substantially along the junction region BN3 and has a width between the first well region 10A and the fourth well region 10D. The width of the depletion region DR3 is affected by the doping concentrations of the first well region 10A and the fourth well region 10D and varies with the electric field distribution of the first well region 10A and the fourth well region 10D. For simplicity of illustration and drawing, the range of the width of the depletion region DR3 is not shown in the figure.

[0092] According to an embodiment of the present application, the semiconductor structure can further include a plurality of fifth dummy structures 500 disposed in the fourth well region 10D and adjacent to the first well region 10A, preferably along the boundary region BN3 between the fourth well region 10D and the first well region 10A.

[0093] According to an embodiment of the present application, the semiconductor structure can further include a plurality of sixth dummy structures 600 disposed in the fourth well region 10D and located farther away from the first well region 10A than the fifth dummy structures 500. In other words, the fifth dummy structures 500 are located between the sixth dummy structures 600 and the first well region 10A.

[0094] Please refer to Figure 1A and Figure 1B . The first dummy structure 100 includes a first conductive region 102 and a first doped region 104 located below the first conductive region 102. The first doped region 104 is between the first conductive region 102 and the first well region 10A, such that the first conductive region 102 does not directly contact the first well region 10A. According to an embodiment of the present application, the first conductive region 102 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto. The first doped region 104 includes a doping of a first conductivity type, which is the same as the first well region 10A, such as a P-type, and the doping concentration of the first doped region 104 is greater than that of the first well region 10A.

[0095] The second dummy structure 200 includes a second conductive region 202, which directly contacts the first well region 10A. According to an embodiment of the present application, the second conductive region 202 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto.

[0096] The third dummy structure 300 includes a third conductive region 302 and a third doped region 304 located below the third conductive region 302. The third doped region 304 is between the third conductive region 302 and the second well region 10B, such that the third conductive region 302 does not directly contact the second well region 10B. According to an embodiment of the present application, the third conductive region 302 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto. The third doped region 304 includes a doping of a second conductivity type, which is the same as the second well region 10B, such as an N-type, and the doping concentration of the third doped region 304 is greater than that of the second well region 10B.

[0097] The fourth dummy structure 400 includes a fourth conductive region 402, respectively, and the fourth conductive region 402 directly contacts the third well region 10C. According to an embodiment of the present application, the fourth conductive region 402 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto.

[0098] The fifth dummy structure 500 includes a fifth conductive region 502 and a fifth doped region 504 under the fifth conductive region 502, respectively. The fifth doped region 504 is between the fifth conductive region 502 and the fourth well region 10D, so that the fifth conductive region 502 does not directly contact the fourth well region 10D. According to an embodiment of the present application, the fifth conductive region 502 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto. The fifth doped region 504 includes a doping of a second conductive type, and has the same second conductive type as the fourth well region 10D, such as an N-type. The doping concentration of the fifth doped region 504 is greater than that of the fourth well region 10D.

[0099] The sixth dummy structure 600 includes a sixth conductive region 602, respectively, and the sixth conductive region 602 directly contacts the fourth well region 10D. According to an embodiment of the present application, the sixth conductive region 602 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto.

[0100] Please continue to refer to Figure 1A and Figure 1B . The semiconductor structure can further include a plurality of active regions 700 disposed in the first well region 10A, the middle well region 10BB, the third well region 10C, and the fourth well region 10D, respectively. According to an embodiment of the present application, the active region 700 can include a conductive region 702 and a doped region 704 under the conductive region 702, respectively. The doped region 704 is between the conductive region 702 and the well region, so that the conductive region 702 does not directly contact the well region. According to an embodiment of the present application, the conductive region 702 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto.

[0101] The doping regions 704 can comprise doping with a first conductivity type or a second conductivity type. The conductivity type of the doping regions 704 is determined according to the application requirement. For example, in some embodiments, when the active regions 700 are used as well-pickup or substrate bias contact regions, the conductivity type of the doping regions 704 is the same as the well region where the doping regions 704 are located. For example, the doping regions 704 located in the first well region 10A can have a first conductivity type, such as P type; the doping regions 704 located in the middle well region 10BB can have a second conductivity type, such as N type; the doping regions 704 located in the third well region 10C can have a first conductivity type, such as P type; the doping regions 704 located in the fourth well region 10D can have a second conductivity type, such as N type, and the doping concentration of each of the doping regions 704 is greater than the doping concentration of the well region where the doping regions 704 are located. In other embodiments, when the active regions 700 are used as source / drain regions, the conductivity type of the doping regions 704 is complementary to the well region where the doping regions 704 are located. For example, the doping regions 704 located in a P type well region can have an N conductivity type, and the doping regions 704 located in an N type well region can have a P conductivity type.

[0102] According to an embodiment of the present application, the active regions 700, the first dummy structures 100, the second dummy structures 200, the third dummy structures 300, the fourth dummy structures 400, the fifth dummy structures 500 and the sixth dummy structures 600 are formed in the substrate 10 by the same fabrication process. For example, a photolithography and etching fabrication process can be performed to form trenches in the substrate 10 to define the pattern of the active regions 700, the first dummy structures 100, the second dummy structures 200, the third dummy structures 300, the fourth dummy structures 400, the fifth dummy structures 500 and the sixth dummy structures 600, and then a dielectric material (for example, silicon oxide, silicon nitride, or silicon oxynitride, but not limited to) is filled into the trenches and a chemical mechanical polishing fabrication process (CMP) is performed to remove the excess dielectric material outside the trenches and to planarize the surface of the substrate 10, thereby forming the isolation structures 20 and the active regions 700, the first dummy structures 100, the second dummy structures 200, the third dummy structures 300, the fourth dummy structures 400, the fifth dummy structures 500 and the sixth dummy structures 600 separated by the isolation structures 20. By providing the dummy structures, the problem of loading effect caused by the active regions 700 having different pattern densities in different regions of the substrate 10 during the chemical mechanical polishing fabrication process (CMP) can be improved, and a better planarization result can be obtained.

[0103] As Figure 1AAs shown, the isolation structure 20 can include a first isolation region 20A overlapping the junction region BN1 between the first well region 10A and the second well region 10B, and located between the first dummy structure 100 and the third dummy structure 300. The first dummy structure 100 and the third dummy structure 300 include a first distance D1, which is substantially the width of the first isolation region 20A. The isolation structure 20 can also include a second isolation region 20B overlapping the junction region BN2 between the second well region 10B and the third well region 10C, and located between the third dummy structure 300 and the fourth dummy structure 400. The third dummy structure 300 and the fourth dummy structure 400 include a second distance D2, which is substantially the width of the second isolation region 20B. As shown, the isolation structure 20 can also include a third isolation region 20C overlapping the junction region BN3 between the fourth well region 10D and the first well region 10A, and located between the first dummy structure 100 and the fifth dummy structure 500. The first dummy structure 100 and the fifth dummy structure 500 include a third distance D3, which is substantially the width of the third isolation region 20C. Figure 1B

[0104] The semiconductor structure further includes an interlayer dielectric layer 22 on the substrate 10, covering the active region 700, the first dummy structure 100, the second dummy structure 200, the third dummy structure 300, the fourth dummy structure 400, the fifth dummy structure 500, the sixth dummy structure 600, and the isolation structure 20. The interlayer dielectric layer 22 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable dielectric material. A plurality of contact plugs 30 are formed in the interlayer dielectric layer 22, and are in contact with and electrically connected to the conductive region 702 of the active region 700. The contact plugs 30 can include a conductive material, such as a metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN), but are not limited thereto. An external voltage can be applied to the active region 700 through the contact plugs 30 for operating the semiconductor structure.

[0105] ​It is worth noting that the first dummy structure 100, the second dummy structure 200, the third dummy structure 300, the fourth dummy structure 400, the fifth dummy structure 500 and the sixth dummy structure 600 are not provided with any contact plug 30 above them, which are electrically isolated from the conductive structures (not shown) on the substrate 10 by the interlayer dielectric layer 22, are not electrically connected with any conductive structure on the substrate 10, and do not receive external voltage from outside the substrate 10, and thus can be considered as electrically floating. According to an embodiment of the present application, the surfaces of the first dummy structure 100, the second dummy structure 200, the third dummy structure 300, the fourth dummy structure 400, the fifth dummy structure 500 and the sixth dummy structure 600 can be completely covered by the interlayer dielectric layer 22.

[0106] When an external voltage is applied to the well region during the operation of the semiconductor structure, the width of the depletion region of the junction region will become larger, or the fabrication process deviation will cause the depletion region to deviate, which can result in the partial overlap of the depletion region and the adjacent dummy structure. When the dummy structure is not designed properly, the free carrier injection into the depletion region can cause through-well leakage. In addition, when designing the layout of the semiconductor structure, the widths of the first isolation region 20A, the second isolation region 20B and the third isolation region 20C need to be large enough, i.e. the first distance D1, the second distance D2 and the third distance D3 need to be large enough, in order to reduce the through-well leakage. However, this causes difficulty in the chip size shrinkage.

[0107] To overcome the above problems, the present application particularly provides a doped region (i.e. the first doped region 104, the third doped region 304 and the fifth doped region 504) with the same conductivity type as the well region between the conductive region (i.e. the first conductive region 102, the third conductive region 302 and the fifth conductive region 502) of the first dummy structure 100, the third dummy structure 300 and the fifth dummy structure 500 located adjacent to the junction region BN1, the junction region BN2 and the junction region BN3 and the well region, which can adjust the energy band structure of this region, increase the barrier of the free carrier (e.g. hole) injection from the conductive region into the well region, reduce the opportunity of the free carrier injection from the first conductive region 102, the third conductive region 302 or the fifth conductive region 502 into the depletion region, and thus reduce the through-well leakage. Therefore, even when the chip size shrinkage causes the partial overlap of the depletion region and the dummy structure, the present application can ensure that the through-well leakage will not be too large, and a tighter layout and / or a smaller chip size can be achieved. According to an embodiment of the present application, the first distance D1 can be between 1.39 um and 3.5 um, the second distance D2 can be between 0.98 um and 3.2 um, and the third distance D3 can be between 1.6 um and 4.6 um.

[0108] It is particularly noted that,Figure 1 , Figure 1A and Figure 1B Although the fourth dummy structure 400 shown does not include a doped region, it is only an example. In other embodiments, a doped region may be provided between the fourth conductive region 402 and the third well region 10C of the fourth dummy structure 400 as needed.

[0109] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0110] Figure 2 , Figure 2A and Figure 2B The diagram shown is a schematic diagram of a semiconductor structure according to a second embodiment of the present invention. Figure 2 This is a partial planar schematic diagram of a semiconductor structure. Figure 2A For roughly along Figure 2 A schematic cross-sectional view of the X-direction through the first well region 10A, the second well region 10B, the third well region 10C, and the middle well region 10BB. Figure 2B For roughly along Figure 2 A schematic cross-sectional view of the Y-direction cutting through the first well region 10A and the fourth well region 10D. For simplicity, Figure 2 Not shown Figure 2A and Figure 2B Some structures, such as active region 700, interlayer dielectric layer 22, and contact plug 30. The difference between the second embodiment and the first embodiment is that the second embodiment replaces the second dummy structure 200, the fourth dummy structure 400 and the sixth dummy structure 600 of the first embodiment with the second dummy structure 210, the fourth dummy structure 410 and the sixth dummy structure 610.

[0111] In detail, the second dummy structure 210 includes a second dummy diffusion region 214, a second dummy portion 212 disposed on the second dummy diffusion region 214, and a metal silicide 216 disposed in the second dummy diffusion region 214 exposed from both sides of the second dummy portion 212. The fourth dummy structure 410 includes a fourth dummy diffusion region 414, a fourth dummy portion 412 disposed on the fourth dummy diffusion region 414, and a metal silicide 416 disposed in the fourth dummy diffusion region 414 exposed from both sides of the fourth dummy portion 412. The sixth dummy structure 610 includes a sixth dummy diffusion region 614, a sixth dummy portion 612 disposed on the sixth dummy diffusion region 614, and a metal silicide 616 disposed in the sixth dummy diffusion region 614 exposed from both sides of the sixth dummy portion 612.

[0112] According to an embodiment of the present invention, the second dummy diffusion region 214, the fourth dummy diffusion region 414, and the sixth dummy diffusion region 614 can be formed in the substrate 10 with the active region 700, the first dummy structure 100, the third dummy structure 300, and the fifth dummy structure 500 using the same fabrication process, and are separated from each other by the isolation structure 20. The fabrication steps are described above and will not be repeated here. The second dummy portion 212, the fourth dummy portion 412, and the sixth dummy portion 612 can be formed with the gate of a transistor (not shown) on the substrate 10 using the same fabrication process, such as a polysilicon gate fabrication process, a front metal gate fabrication process, or a back metal gate fabrication process (also known as a metal-replacement gate fabrication process), but are not limited thereto. The second dummy portion 212, the fourth dummy portion 412, and the sixth dummy portion 612 may each include a metal material or a polysilicon material. Metal silicides 216, 416, and 616 may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but are not limited thereto. In this embodiment, by providing second dummy portions 212, fourth dummy portions 412, and sixth dummy portions 612 on the second dummy diffusion region 214, fourth dummy diffusion region 414, and sixth dummy diffusion region 614, the pattern density of this region can be closer to the gate pattern density of other component regions during the gate fabrication process, thereby improving the fabrication process margin.

[0113] It should be noted that, Figure 2 , Figure 2A and Figure 2B The fourth virtual structure 410 is merely an example; in other embodiments, it can also be selected as needed. Figure 2 , Figure 2A and Figure 2B A fourth virtual structure 400 is set in the middle.

[0114] Figure 3 , Figure 3A and Figure 3B The diagram shown is a schematic diagram of a semiconductor structure according to a third embodiment of the present invention. Figure 3 This is a partial planar schematic diagram of a semiconductor structure. Figure 3A For roughly along Figure 3 A schematic cross-sectional view of the X-direction through the first well region 10A, the second well region 10B, the third well region 10C, and the middle well region 10BB. Figure 3B For roughly along Figure 3 A schematic cross-sectional view of the Y-direction cutting through the first well region 10A and the fourth well region 10D. For simplicity, Figure 3 Not shown Figure 3A and Figure 3BSome structures of the third embodiment, such as the active region 700, the ILD 22, and the contact plug 30, are similar to those of the second embodiment. The difference between the third embodiment and the second embodiment is that the first dummy structure 110, the third dummy structure 310, and the fifth dummy structure 510 of the third embodiment replace the first dummy structure 100, the third dummy structure 300, and the fifth dummy structure 500 of the second embodiment.

[0115] In detail, the first dummy structure 110 includes a first dummy diffusion region 114 and a first dummy portion 112 disposed on the first dummy diffusion region 114. The third dummy structure 310 includes a third dummy diffusion region 314 and a third dummy portion 312 disposed on the third dummy diffusion region 314. The fifth dummy structure 510 includes a fifth dummy diffusion region 514 and a fifth dummy portion 512 disposed on the fifth dummy diffusion region 514. The first dummy portion 112, the third dummy portion 312, and the fifth dummy portion 512 can be formed by the same fabrication process as the gate of a transistor (not shown) on the substrate 10, such as a polysilicon gate fabrication process, a front metal gate fabrication process, or a back metal gate fabrication process (also referred to as a replacement metal gate fabrication process), but are not limited thereto. The first dummy portion 112, the third dummy portion 312, and the fifth dummy portion 512 can each include a metal material or a polysilicon material. The present embodiment can further adjust the pattern density of the regions provided with the first dummy portion 112, the third dummy portion 312, and the fifth dummy portion 512 during the gate fabrication process, further improving the fabrication process margin. In addition, the first dummy diffusion region 114, the third dummy diffusion region 314, and the fifth dummy diffusion region 514 of the present embodiment are each completely covered by the first dummy portion 112, the third dummy portion 312, and the fifth dummy portion 512, and are not exposed, so that no metal silicide is formed in the first dummy diffusion region 114, the third dummy diffusion region 314, and the fifth dummy diffusion region 514, thereby avoiding the formation of a drain current through the well region caused by free carriers from the metal silicide.

[0116] Figure 4 、 Figure 4A and Figure 4B is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4 is a partial plan view of a semiconductor structure. Figure 4A is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4 is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4B is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4 is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4 is a schematic diagram of a semiconductor structure according to a fourth embodiment of the present application. Figure 4A and Figure 4BSome structures, such as active region 700, interlayer dielectric layer 22, and contact plug 30. The difference between the fourth embodiment and the second embodiment is that the fourth embodiment replaces the first dummy structure 100, the third dummy structure 300 and the fifth dummy structure 500 of the second embodiment with the first dummy structure 120, the third dummy structure 320 and the fifth dummy structure 520.

[0117] In detail, the first dummy structure 120 includes a first dummy diffusion region 114, a first dummy portion 112 disposed on the first dummy diffusion region 114, a metal silicide 116 disposed in the first dummy diffusion region 114 exposed from both sides of the first dummy portion 112, and a first doped region 118 disposed in the first dummy diffusion region 114 and surrounding the metal silicide 116, so that the metal silicide 116 does not directly contact the first well region 10A. The third dummy structure 320 includes a third dummy diffusion region 314, a third dummy portion 312 disposed on the third dummy diffusion region 314, a metal silicide 316 disposed in the third dummy diffusion region 314 exposed from both sides of the third dummy portion 312, and a third doped region 318 disposed in the third dummy diffusion region 314 and surrounding the metal silicide 316, so that the metal silicide 316 does not directly contact the second well region 10B. The fifth dummy structure 520 includes a fifth dummy diffusion region 514, a fifth dummy part 512 disposed on the fifth dummy diffusion region 514, a metal silicide 516 disposed in the fifth dummy diffusion region 514 exposed from both sides of the fifth dummy part 512, and a fifth doped region 518 disposed in the fifth dummy diffusion region 514 and surrounding the metal silicide 516, so that the metal silicide 516 does not directly contact the fourth well region 10D.

[0118] For the first dummy structure 120, the third dummy structure 320, and the fifth dummy structure 520 located near the junction regions BN1, BN2, and BN3, this embodiment specifically sets the first doped region 118, the third doped region 318, and the fifth doped region 518 to surround the metal silicide 116, the metal silicide 316, and the metal silicide 516, respectively. This increases the potential barrier for free carriers in the metal silicide 116, the metal silicide 316, and the metal silicide 516 to be injected into the well region, thereby reducing the leakage current through the well region.

[0119] Figure 5 and Figure 5A The diagram shown is a schematic diagram of a semiconductor structure according to a fifth embodiment of the present invention. Figure 5 This is a partial planar schematic diagram of a semiconductor structure. Figure 5A For roughly along Figure 5 A schematic cross-sectional view of the X-axis passing through the first well region 10A, the second well region 10B, the third well region 10C, and the middle well region 10BB. For simplicity, Figure 5Some structures, such as the active region 700, the ILD 22, and the contact plug 30, are not shown. Figure 5A

[0120] The fifth embodiment differs from the first embodiment in that the fifth embodiment further includes a well-pick up region 720 in the second well region 10B. The well-pick up region 720 is disposed within the second well region 10B, can have a closed ring shape surrounding along the periphery of the second well region 10B, and is substantially located between the first dummy structure 100 and the third dummy structure 300. The well-pick up region 720 can include a conductive region 722 and a doped region 724 disposed below the conductive region 722. The doped region 724 is between the conductive region 722 and the second well region 10B, such that the conductive region 722 does not directly contact the second well region 10B. According to an embodiment of the present application, the conductive region 722 includes a metal silicide, such as cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), or platinum silicide (PtSi), but is not limited thereto. The doped region 724 includes a doping of a second conductivity type, which is the same as the second well region 10B, such as N-type, and the doping concentration of the doped region 724 is greater than that of the second well region 10B. The conductive region 722 of the well-pick up region 720 can be in contact with and electrically connected to at least one contact plug 30. An external voltage is applied to the well-pick up region 720 through the contact plug 30, so as to control the electric field distribution of the second well region 10B.

[0121] In summary, the present application provides dummy structures disposed along the junctions of well regions of different conductivity types, and when the dummy structure includes a conductive region, such as a metal silicide, a doped region of the same conductivity type as the well region in which the conductive region is disposed is provided below the conductive region, so as to increase the barrier for the injection of free carriers (e.g., holes) of the conductive region into the well region, and to reduce the well punch-through current caused by the conductive region.

[0122] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be covered by the present application.​

Claims

1. A semiconductor structure, characterized by, comprising: a substrate; a first well region and a second well region disposed in the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type, the first conductivity type and the second conductivity type being complementary; and a plurality of first dummy structures disposed in the first well region in the substrate and arranged along a junction region between the first well region and the second well region, wherein the plurality of first dummy structures each comprises a first conductive region and a first doped region, the first doped region has the first conductivity type, and the first doped region is located between the first conductive region and the first well region.

2. The semiconductor structure of claim 1, further comprising a plurality of second dummy structures disposed in the first well region, wherein the plurality of second dummy structures each comprises a second conductive region, and the second conductive region is in direct contact with the first well region, the first dummy structures being arranged between the second dummy structures and the second well region.

3. The semiconductor structure of claim 1, wherein the first conductive region comprises a metal silicide.

4. The semiconductor structure of claim 1, further comprising: a third well region disposed in the second well region, the third well region having the first conductivity type; and a plurality of third dummy structures disposed in the second well region and surrounding the third well region, wherein the plurality of third dummy structures each comprises a third conductive region and a third doped region, and the third doped region is located between the third conductive region and the second well region.

5. The semiconductor structure of claim 4, further comprising: a first isolation region disposed between the plurality of first dummy structures and the plurality of third dummy structures, and overlapping the junction region between the first well region and the second well region.

6. The semiconductor structure of claim 5, wherein a first distance is comprised between the plurality of first dummy structures and the plurality of third dummy structures, wherein the first distance is between 1.39 um and 3.5 um.

7. The semiconductor structure of claim 4, further comprising: a plurality of fourth dummy structures disposed in the third well region, wherein the plurality of fourth dummy structures each comprises a fourth conductive region, and the fourth conductive region is in direct contact with the third well region.

8. The semiconductor structure of claim 7, further comprising: a second isolation region disposed between the plurality of third dummy structures and the plurality of fourth dummy structures, and overlapping a junction region between the second well region and the third well region.

9. The semiconductor structure of claim 8, wherein a second distance is comprised between the plurality of third dummy structures and the plurality of fourth dummy structures, wherein the second distance is between 0.98 um and 3.2 um.

10. The semiconductor structure of claim 1, further comprising: a plurality of third dummy structures disposed in the second well region, wherein the plurality of third dummy structures each comprises a third conductive region and a third doped region, and the third doped region is located between the third conductive region and the second well region.

11. The semiconductor structure of claim 10, wherein the second well region is a deep N-type well region.

12. The semiconductor structure of claim 1, further comprising: a fourth well region disposed in the substrate and abutting the first well region, the fourth well region having the second conductivity type; a plurality of fifth dummy structures disposed in the fourth well region and arranged along an interface region between the fourth well region and the first well region, wherein the plurality of fifth dummy structures each include a fifth conductive region and a fifth doped region, and the fifth doped region is located between the fifth conductive region and the fourth well region; and a plurality of sixth dummy structures disposed in the fourth well region, wherein the plurality of sixth dummy structures each include a sixth conductive region, and the sixth conductive region directly contacts the fourth well region, the fifth dummy structures being arranged between the first dummy structures and the sixth dummy structures.

13. The semiconductor structure of claim 12, further comprising: a third isolation region disposed between the plurality of first dummy structures and the plurality of fifth dummy structures and overlapping the interface region between the fourth well region and the first well region.

14. The semiconductor structure of claim 13, wherein a third distance is included between the plurality of first dummy structures and the plurality of fifth dummy structures, and the third distance is between 1.6 um and 4.6 um.

15. A semiconductor structure, characterized by comprising: a substrate; a first well region and a second well region disposed in the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type, the first conductivity type and the second conductivity type being complementary; and a plurality of first dummy structures disposed in the first well region and arranged along an interface region between the first well region and the second well region, wherein the plurality of first dummy structures each include a first dummy diffusion region and a first dummy portion disposed on the first dummy diffusion region; a plurality of second dummy structures disposed in the first well region, wherein the plurality of second dummy structures each include a second dummy diffusion region and a second dummy portion disposed on the second dummy diffusion region, and wherein the plurality of second dummy structures each further include a metal silicide disposed in the second dummy diffusion region on both sides of the second dummy portion.

16. The semiconductor structure of claim 15, wherein the first dummy portion includes a metal material or a polysilicon material.

17. The semiconductor structure of claim 16, wherein the first dummy portion completely covers the first dummy diffusion region.

18. The semiconductor structure of claim 15, further comprising: a third well region disposed in the second well region and having the first conductivity type; and a plurality of third dummy structures disposed in the second well region and surrounding the third well region, wherein the plurality of third dummy structures each include a third dummy diffusion region and a third dummy portion disposed on the third dummy diffusion region.

19. The semiconductor structure of claim 18, further comprising: a first isolation region disposed between the plurality of first dummy structures and the plurality of third dummy structures and overlapping the interface region between the first well region and the second well region.

20. The semiconductor structure of claim 18, further comprising: a plurality of fourth dummy structures disposed in the third well region, wherein the plurality of fourth dummy structures each include a fourth dummy diffusion region and a fourth dummy portion disposed on the fourth dummy diffusion region.

21. The semiconductor structure of claim 20, further comprising: a second isolation region disposed between the plurality of third dummy structures and the plurality of fourth dummy structures and overlapping a junction region between the second well region and the third well region.

22. The semiconductor structure of claim 15, further comprising: a fourth well region disposed in the substrate and adjacent to the first well region; a plurality of fifth dummy structures disposed in the fourth well region and arranged along a junction region between the fourth well region and the first well region, wherein the plurality of fifth dummy structures each include a fifth dummy diffusion region and a fifth dummy portion disposed on the fifth dummy diffusion region; and a plurality of sixth dummy structures disposed in the fourth well region, wherein the fifth dummy structures are arranged between the first dummy structures and the sixth dummy structures, the plurality of sixth dummy structures each include: a sixth dummy diffusion region; a sixth dummy portion disposed on the sixth dummy diffusion region; and a metal silicide disposed in the sixth dummy diffusion region on both sides of the sixth dummy portion.

23. The semiconductor structure of claim 22, further comprising: a third isolation region disposed between the plurality of first dummy structures and the plurality of fifth dummy structures and overlapping the junction region between the fourth well region and the first well region.

Images