Semiconductor device having a transistor and method of forming a semiconductor device having a transistor

Abstract

The present invention relates to a semiconductor device having a transistor and a method of forming a semiconductor device having a transistor. Embodiments of the semiconductor device can include a transistor having a first doped region and a second doped region extending laterally under a source, body, and drain of the transistor. The transistor can have embodiments including an additional bias contact to apply a bias potential to the first doped region and / or alternatively to the second doped region.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to a semiconductor device having a transistor and a method of forming a semiconductor device having a transistor, and more particularly, to a semiconductor, a structure of a semiconductor, and a method of forming a semiconductor device. BACKGROUND

[0002] In the past, the semiconductor industry has utilized various methods and structures to form high voltage transistors having high breakdown voltage and high switching rate. High voltage transistors are often required to withstand drain-source voltages of up to about 200 volts (200V) or higher. It is also desirable for high voltage transistors to have low on-resistance (Rdson). Typically, transistors are formed with various doped regions to achieve the desired operation.

[0003] In some applications, power dissipation sometimes occurs in the transistors during switching operation. In addition, some applications desire higher breakdown voltage. Some manufacturing methods are not compatible with established manufacturing operations.

[0004] Therefore, it is desirable to have a high voltage transistor having improved breakdown voltage and / or reduced power dissipation during switching operation. SUMMARY

[0005] To address the above-discussed deficiencies, it is the principal objective of the present invention to provide a semiconductor device having a transistor and a method of forming a semiconductor device having a transistor.

[0006] According to one aspect, a semiconductor device having a transistor is provided, the semiconductor device comprising: a semiconductor substrate; an insulator located on the semiconductor substrate; a source region covering the insulator and having a first conductivity type; a drift region covering the insulator and having the first conductivity type; a drain region located within the drift region, covering the insulator and having the first conductivity type, the drain region being spaced apart from the source region through at least a portion of the drift region; a first doped region located on the insulator, having a first doping concentration and having the first conductivity type, the first doped region being formed to extend continuously through the insulator below the source region, the drain region, and the drift region; and a confinement layer located on the first doped region, having a second doping concentration and having a second conductivity type, the second doping concentration being greater than [missing information]. The first doping concentration; the confinement layer is formed to continuously extend through the first doped region below the source region, the drain region, and the drift region; the epitaxial layer is located on the confinement layer and has the first conductivity type, the epitaxial layer has a third doping concentration, the third doping concentration being less than the second doping concentration and greater than the first doping concentration, wherein a portion of the epitaxial layer forms a PN junction with the confinement layer; the body region is located in the epitaxial layer and has the second conductivity type, wherein the source region is located in the body region, the body region is electrically coupled to the confinement layer, and the confinement layer receives a potential applied to the body region; and the bias contact is formed in the epitaxial layer and includes a second doped region having the first conductivity type, the bias contact is electrically coupled to the first doped region, wherein a potential applied to the bias contact is applied to a portion of the PN junction.

[0007] According to one aspect, a semiconductor device having a transistor is provided, the semiconductor device comprising: a first doped region having a first conductivity type and a first doping concentration; a drift region located within the first doped region and having the first conductivity type, the drift region having a drain region formed therein and having the first conductivity type; a body region spaced apart from the drift region and having a second conductivity type; a source region located within the body region and having the first conductivity type; and a channel region located within the body region. Between the source region and the drift region; a confinement layer having the second conductivity type and a second doping concentration greater than the first doping concentration, the confinement layer extending continuously below the body region, the source region, the channel region, the drift region, and the drain region, wherein the confinement layer is electrically connected to the body region; and a barrier layer having the first conductivity type and a third doping concentration less than the first doping concentration, the barrier layer being located below and adjacent to the confinement layer, wherein the potential of the barrier layer is substantially constant.

[0008] According to one aspect, a method of forming a semiconductor device having transistors is provided, the method comprising: providing a semiconductor substrate; forming a first doped region covering the semiconductor substrate and having a first conductivity type; forming a second doped region having a second conductivity type on the first doped region, the second doped region having a first doping concentration; forming a third doped region having the first conductivity type on the second doped region, the third doped region having a second doping concentration less than the first doping concentration; and forming a body region, a source region within the body region, a drift region within the first doped region, and a drain region within the drift region, wherein the first doped region and the second doped region extend to be continuously located below the source region, the drift region, and the drain region, and the second doped region is electrically coupled to the body region. Attached Figure Description

[0009] Figure 1 A partially enlarged plan view of a simplified example of a semiconductor device including a high-voltage transistor according to the present invention is shown;

[0010] Figure 2 The invention is shown Figure 1 An enlarged cross-sectional portion of an example embodiment of the transistor;

[0011] Figure 3 An example phase of an embodiment of the method for forming a transistor according to the present invention is shown. Figure 1 An enlarged cross-sectional view of an example embodiment of the transistor;

[0012] Figure 4 An enlarged cross-sectional portion of an example embodiment of a transistor is shown, which may have embodiments according to the present invention. Figure 1 Alternative embodiments of the transistors shown;

[0013] Figure 5 An enlarged cross-sectional portion of examples of different transistor embodiments is shown, which may have embodiments according to the present invention. Figure 4 Alternative embodiments of the transistors shown; and

[0014] Figure 6 An enlarged cross-sectional portion of an example embodiment of a transistor is shown, which may have embodiments according to the present invention. Figure 1 or Figure 4 or Figure 5 Alternative embodiments of the transistors shown. Detailed Implementation

[0015] To ensure clarity and simplicity, the components in the accompanying drawings are not necessarily drawn to scale, and some components may be exaggerated for ease of explanation. Unless otherwise stated, the same reference numerals in different drawings denote the same components. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and components may be omitted. As used herein, a current-carrying element or current-carrying electrode refers to a component in a device that carries the current flowing through the device, such as the source or drain of a transistor such as a MOS transistor or a High Electron Mobility Transistor (HEMT), or the emitter or collector of a bipolar transistor, or the cathode or anode of a diode. A control element or control electrode refers to a component in a device that controls the current flowing through the device, such as the gate of a MOS transistor, the gate of a HEMT, or the base of a bipolar transistor. Furthermore, a current-carrying element may carry current flowing through the device in one direction, such as current entering the device, and a second current-carrying element may carry current flowing through the device in the opposite direction, such as current leaving the device. While the device may be interpreted herein as some N-channel or P-channel device, or some N-type or P-type doped region, those skilled in the art will understand that complementary devices are also feasible according to the invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conduction occurs, such as conduction via holes or electrons; therefore, conductivity type refers not to doping concentration but to the doping type, such as P-type or N-type. Those skilled in the art will understand that the terms "during," "simultaneously," and "when" used herein in relation to circuit operation are not precise terms indicating that an action occurs immediately upon initiation, but there may be a small but reasonable delay, such as various propagation delays between reactions triggered by the initiation. Furthermore, the term "simultaneously" means that an action occurs at least for a portion of the duration of the initiation. The use of the terms "approximately" or "substantially" means that the value of the element has a parameter that is expected to be close to the set value or position. However, as is well known in the art, there are always small differences that prevent the value or position from perfectly matching the set value or position. It is well established in the art that a variance of at least 10 percent (or 20 percent (or 20 percent for some elements including semiconductor doping concentrations) is a reasonable variance that is perfectly consistent with the described ideal objective. In the claims and / or the detailed description in the drawings, the terms “first,” “second,” “third,” etc., used for some element names are used to distinguish similar elements and are not necessarily used to describe an order, whether temporal, spatial, sequential, or any other manner. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments described herein can be implemented in orders other than those described or illustrated herein.The phrase "in one embodiment" or "an embodiment" refers to a specific feature, structure, or characteristic described in connection with an embodiment being included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" or "an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment, but may refer to the same embodiment in some cases. Furthermore, in one or more embodiments, specific features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those skilled in the art. For clarity of the drawings, doped regions of the device structure are shown as having generally straight edges and precise corners. However, those skilled in the art will understand that due to the diffusion and activation of the dopant, the edges of the doped regions may not typically be straight, and the corners may not be precise angles.

[0016] Furthermore, this description illustrates a cellular design (where the main body region is a plurality of cellular areas) rather than a single-substrate design (where the main body region consists of a single area, the single area being formed in an elongated pattern, or in some embodiments, in a serpentine pattern). However, this description is intended to be applicable to both cellular and single-substrate implementations.

[0017] The embodiments shown and described below may have embodiments, and / or may be implemented in the absence of any elements not specifically disclosed herein. Figure 1 A partially enlarged plan view shows a simplified example of an embodiment of a semiconductor device 10 including a high-voltage transistor 11. In some embodiments, the device 10 may include... Figure 1 Other electrical devices or structures not shown. In one embodiment, transistor 11 may be formed as a plurality of transistor fingers or transistor elements, such as transistor elements 12 and 13, each functioning as a transistor. The plurality of elements are interconnected to function as a single transistor. For example, transistor element 12 may include a source region having a source electrode 15, the source region being formed adjacent to a gate region having a gate electrode 17, and the gate region being spaced apart from a drain region having a drain electrode 18. Transistor 11 may also include an optional bias contact having a bias electrode 55. The drain region and drain electrode 18 may be shared between elements 12 and 13. Element 13 may also include a gate region having a gate electrode 20 and a source region having a source electrode 21. In some embodiments, source electrode 21 may resemble source electrode 15, and gate electrode 20 may resemble gate electrode 17.

[0018] Axial centerline 14 denotes the center of elements 12 and 13, allowing transistor 11 to be substantially symmetrical about line 14. Those skilled in the art will understand that although transistor 11 is shown as having two elements 12 and 13, transistor 11 can be formed having a plurality of elements, such as elements 12 and 13. An isolation region or isolation structure 80 may be formed to isolate transistor 11 from other parts of device 10.

[0019] Figure 2 It shows along Figure 1 An enlarged cross-sectional portion of an example embodiment of transistor 11 obtained by cross-sectional line 2-2.

[0020] Figure 3 An enlarged cross-sectional view of an example embodiment of the method for forming transistor 11 is shown at an example stage. This description refers at least to Figure 2 and Figure 3 .

[0021] Transistor 11 may be formed on semiconductor substrate 25. Substrate 25 may be an embodiment of silicon-on-insulator (SOI) substrate or alternatively a silicon substrate. One embodiment may also include an insulating layer or insulator 26 that may be formed on substrate 25 to provide electrical isolation between substrate 25 and elements of transistor 11. Insulator 26 may be formed of silicon dioxide or silicon nitride or other insulating materials known to those skilled in the art of semiconductors. In some embodiments, insulator 26 may be replaced by a doped buried layer. One embodiment may include replacing insulator 26 with an N-type buried layer.

[0022] refer to Figure 3 A doped layer 34 can be formed on insulator 26. Embodiments of layer 34 may have p-type conductivity. One embodiment may include forming a portion of layer 34, such as layer 27, using a modulated doping process, where the active doping concentration of layer 27 is higher than that of different portions of layer 34, such as layer 28. Layer 28 may form a doped region that can be used as a barrier layer, and layer 27 may form a doped region that can be used as an anti-back gate layer. Embodiments of layer 28 may be formed having approximately 2E14 to approximately 1E15 atoms / cm². 3 The active doping concentration can be approximately 5E14 atoms / cm³. 3 The active doping concentration is then determined. Subsequently, a portion of layer 34 can be doped with the opposite type of conductivity to form layer 30, leaving layer 29 to comprise layers 27 and 28. One embodiment of layer 30 can be formed to have N-type conductivity and approximately 9E15 to approximately 2E16 atoms / cm². 3 Or alternatively, approximately 1E16 atoms / cm 3 The active doping concentration. Layer 30 may be formed over the entire length of layer 29, or alternatively may be formed having a width spanning layer 29, which is shorter than layer 29 or alternatively layer 28 by a distance 31. Alternatively, layer 29 may be formed on insulator 26 by epitaxial technology, and layer 30 may be formed on layer 29.

[0023] Subsequently, doped region 32 may be formed on layer 30. Embodiments of region 32 may be formed on layer 30 using epitaxy with a doping type opposite to that of layer 30. Alternatively, region 32 may be formed by doping different layers that may be formed on layer 30. Embodiments of region 32 may have p-type conductivity and an active doping concentration less than that of layer 30. The active doping concentration of region 32 may be approximately 2E15 to approximately 5E15, or alternatively approximately 2.6E15. Subsequently, isolation structure 80 may be formed. Isolation structure 80 may be formed as a deep trench isolation structure extending a distance from the surface 33 of region 32 into region 32 to intersect with insulator 26. Those skilled in the art will understand that structure 80 may be formed by forming trench openings in region 32 and forming an insulating material along the sidewalls of the trench openings. Subsequently, any openings in the insulating material may be filled with other materials, such as polysilicon. Structure 80 and insulator 26 form an isolation structure that isolates transistor 11 from any other part of device 10. Figure 1 ).

[0024] Back Figure 2 Other regions of transistor 11 may be formed within region 32. For example, a portion of region 32 may be doped to form the region. The body region 42 of transistor 11 may be formed as a doped region within region 32, and the source region 45 may be formed within region 42. In some embodiments, the source region 45 may include a source contact region 46 and an adjacent and / or lower source doped region, and in some embodiments, the source doped region may have a lower active doping concentration than the active doping concentration of the source contact region 46. A portion of region 42 may be located below and intersect with region 45. The body region 42 may include a body contact region 43 that facilitates forming a low-impedance contact with the body region 42. In one embodiment, a body conductor 44 may be connected to electrode 15 to form a connection between the body region 43 and the source region 45. The doped region 35 may be formed below and intersect with region 42, and also intersect with layer 30. Embodiments of region 35 may have a doping concentration greater than that of layer 28 and not less than, or alternatively greater than, the doping concentration of layer 30. The doping concentration in region 35 can be approximately 2E16 to 1E17 atoms / cm³. 3 And alternatively, it could be approximately 3E16 atoms / cm². 3 In some embodiments, region 35 may help reduce the surface electric field (Resurf) or, alternatively, increase the breakdown voltage of transistor 11; it may be referred to as the Resurf region.

[0025] A drift region can be formed as a doped region 37 on the surface of region 32 and extend vertically into region 32. Embodiments of region 37 may not intersect with or extend into layer 30, but embodiments may intersect with region 35. Embodiments of region 37 may have a doping concentration greater than that of layer 28 and not less than, or alternatively greater than, the doping concentration of layer 30. The doping concentration of region 37 may be approximately 5E15 to approximately 5E16 atoms / cm³. 3 And alternatively, it could be approximately 2E16 atoms / cm². 3 The drain region of transistor 11 may be the portion of region 37 located below the drain contact or contact region 40. Drain contact region 40 may be a doped region with a high active doping concentration to facilitate the formation of a low-impedance electrical connection for the drain region. For example, a low-impedance connection between drain electrode 18 and region 37. Optionally, a doped region 39 may be formed below region 40 and extend vertically into region 37. For example, region 39 may be formed within region 37, and region 40 may be formed within region 39, or alternatively, within region 37. Region 39 may help reduce charge congestion at the drain of transistor 11, thereby improving on-resistance. Region 35 may extend below a portion of region 37. In one embodiment, region 35 is not located below the drain region or regions 39-40. Because the drain region of transistor 11 may be shared by elements 12 and 13, another substantially similar portion of region 37 may also extend in the opposite direction about line 14 to facilitate the formation of element 13 ( Figure 1 Furthermore, a portion of region 35 may extend in the opposite direction to region 37 to facilitate the formation of element 13. A bias contact or bias region 54 may be formed as a doped region on the surface of region 32 and spaced apart from region 39. A contact region 53 with a high active doping concentration may be formed within region 54 to form a low-impedance connection for regions 54 and 32. One embodiment may include regions 42, 43, and 45 laterally located between region 54 and the drain, or alternatively between region 54 and region 40. Embodiments of transistor 11 may include layer 30 and regions 35, 42, and 43 being formed to have N-type conductivity, and regions 32, 37, 39, 40, 45, 46, 53, and 54 being formed to have P-type conductivity.

[0026] A gate structure may be formed as part of a coverage region 42 and covering the portion of region 32 laterally located between regions 42 and 37. The gate structure may include a gate insulator 61, which is formed to cover the portion of region 42 adjacent to region 45 and the portion of region 32 located between regions 42 and 37. Those skilled in the art will understand that insulator 61 is much thinner than insulators 48 and 26. A gate conductor 62 may be formed on insulator 61. Conductor 62 may be formed to cover the portion of region 42 laterally adjacent to region 45 and the portion of region 32 located between regions 37 and 42. The portion of region 42 located below conductor 62 forms the channel region of transistor 11. Embodiments of insulator 61 and conductor 62 may also be formed to cover the portion of region 37 adjacent to region 32. Insulator 61 and conductor 62 may be formed from various known appropriate insulating and gate conductor materials. Conductor 62 may be connected to electrode 17.

[0027] Insulators 48, 49, and 50 may be formed in region 32 and cover corresponding regions 37, 42, and the portion of region 32 extending from region 43 toward region 54. Insulators 48, 49, and 50 may help reduce leakage current between components of transistor 11. Embodiments of insulators 48-50 may be formed using shallow trench technology. One embodiment may include insulators 57, 58, and 59, which may be used to help maintain electrical isolation of some electrodes.

[0028] During operation, source region 45 typically receives a high voltage. For example, this high voltage may be greater than one hundred volts (100V) or as high as two hundred volts (200V) or higher. Body region 42, or alternatively, ground region 43, receives a voltage substantially similar to that received by region 45. Bias region 54 receives a voltage no greater than that received by the drain, or alternatively, may receive a substantially fixed reference voltage. An embodiment of the fixed reference voltage may be a ground reference voltage. In one embodiment, the voltage received by bias region 54 is substantially constant.

[0029] When transistor 11 is disabled, gate conductor 62 receives a voltage close to that of region 45, but the drain (e.g., region 40 or region 37 below region 40) may receive a much smaller voltage. In some embodiments, region 40 may receive a voltage close to a ground reference voltage. Layer 30 is electrically connected to body region 42 through region 35, and thus layer 30 is formed to receive a voltage applied to body region 42. Region 43 typically receives a voltage close to that applied to source region 45. The combination of these voltages causes the PN junction formed between layer 30 and region 32 along the interface with region 32 to be reverse biased, and also causes the PN junction along the interface between region 35 and regions 32 and 37 to be reverse biased. The depletion regions of these PN junctions are essentially depleted of carriers by voltage. The doping concentration of layer 30 contributes to the formation of depletion regions to essentially deplete carrier regions. For example, a doped layer 30 heavier than region 32 allows the depletion region to diffuse into region 32. The depletion region causes the electric field formed between the source region 45 and the drain region (e.g., region 40) to decrease through the depletion region, which helps to increase the breakdown voltage of transistor 11. Furthermore, although layer 28 is not a floating layer directly connected to a potential, a potential can be coupled to layer 28. For example, a voltage applied to contact electrode 55 or alternative ground region 54 can be coupled to layer 28 through layer 30, maintaining layer 28 at a potential between that applied to regions 54 and 43. In one embodiment, the potential (V28) on layer 28 can be the potential (V54) on region 54 plus a percentage (X%) of the difference between the potential (V54) on region 54 and the potential (V43) on region 43. V28 = V54 + (X% * (V43 - V54)). One embodiment may include a percentage (X%) between approximately 25% and approximately 75%. Another embodiment may include approximately 50%. For example, if region 54 is close to zero and region 43 is approximately 200 volts, then layer 28 may have a potential of approximately 100 volts (X = 50%). One embodiment may include: the potentials on regions 54 and 43 may be substantially constant during operation, and therefore the potential on layer 28 may be substantially constant.

[0030] When transistor 11 is enabled, the drain receives a voltage a fraction of a volt less than that received by region 45. For example, this could be approximately 0.1 to approximately 0.5 volts. One embodiment may include a drain receiving a voltage no more than approximately one volt less than that received by region 45 for operation in the linear region of the transistor characteristics. Alternatively, the drain may receive a voltage approximately 10 volts less than that received by region 45 for operation in the saturation region of the transistor characteristics. In an example embodiment, for a source voltage of approximately 200 volts (200V), the drain voltage may be between approximately zero volts and approximately 199.5 or approximately 199.9 volts. Bias region 54 receives the same voltage as before, this lower voltage applied to region 32 below region 54, but layer 30 is subjected to a higher voltage from region 43. Therefore, the PN junction between layer 30 and region 32 below region 54 depletes carriers. Furthermore, the depletion region of the PN junction between layer 30 and the portion of region 32 below region 37 is also depleted. The voltage applied to region 54 is coupled through layer 30 to layer 28. Therefore, as described above, layer 28 is at a potential between the potentials applied to regions 53 and 43. It can be seen that, for the enabled and disabled states of transistor 11, the potential from the bias contact keeps layer 28 at a substantially constant voltage. One embodiment may include a potential in region 43 that differs from the potential in source region 45. Therefore, in one embodiment, the voltage or potential of layer 28 may be independent of the voltage applied to the drain or source.

[0031] In an alternative embodiment, layer 30 may be formed with a shorter distance 31 than layer 28. The distance 31 may be approximately two to approximately three (2-3) micrometers. However, as described above, the potential of layer 28 remains at a substantially constant voltage.

[0032] The depletion region helps isolate layer 28 from the voltage applied to the drain. In some applications, the depletion region formed along layer 30 can help minimize the current flowing from the drain region through layer 30 to the substrate 25. For example, this current might be a parasitic AC current. The substantially constant potential of layer 28 helps minimize the capacitive coupling from region 32 through insulator 26 to substrate 25. Reducing capacitive coupling lowers power losses during transistor 11 switching. Therefore, layers 28 and 30 help increase the breakdown voltage of transistor 11 and help reduce power losses during transistor 11 switching.

[0033] Figure 4 An enlarged cross-sectional view of an example embodiment of transistor 85 is shown. Embodiments of transistor 85 may include transistor 11. Figure 2An alternative embodiment is described. Transistor 85 is substantially similar to transistor 11, except that it has additional doped regions 86 and 88. Transistor 85 also includes an additional gate structure having a gate insulator 89 and a gate conductor 90 that are substantially the same as those of insulator 61 and conductor 62. As shown by the dashed lines, gate conductor 90 is connected to region 42. Region 88 is formed extending from surface 33 into region 32 and has at least a portion located below region 54. Region 88 has the same conductivity type and substantially the same doping concentration as region 37. Region 86 is formed by region 42 and is adjacent to region 43.

[0034] During operation, region 88 serves as a drift region similar to region 37. The voltage on region 88 varies laterally across region 88 as region 88 is depleted. Region 54 serves as a drain region. One embodiment may include region 54 being maintained at a substantially fixed reference potential. Gate conductor 90 is maintained at the potential of region 86. As shown in the usual manner with dashed lines, region 86 is electrically connected to regions 42 and 43. This voltage configuration helps to maintain the potential of layer 28 at a substantially constant voltage during the enable and disable states of transistor 85 and during switching of transistor 85.

[0035] Figure 5 An enlarged cross-sectional view of an example embodiment of transistor 92 is shown. Embodiments of transistor 92 may include transistor 85. Figure 4 Alternative embodiments of the above are provided. In addition to omitting the doped region 88 and having region 50 extend laterally beneath the insulator 89, alternatively extending to... Figure 4 Below the region occupied by the insulator 89, transistor 92 is essentially similar to transistor 85. Regions 86, 42, and 54 form a parasitic PNP transistor. When a large voltage is applied between regions 86 and 54, the PNP transistor can absorb some energy.

[0036] Figure 6 An enlarged cross-sectional view of an example embodiment of transistor 94 is shown. Embodiments of transistor 94 may include transistor 11. Figure 1 An alternative embodiment of either transistor 85 or 92. Except that regions 53-54 are moved and positioned relative to elements 12 and 13. Figure 1 Apart from the two sets of similar elements, transistor 94 is substantially the same as transistor 11. Therefore, regions 53-54 are moved from their adjacency to structure 80 to different locations between the two sets of elements. For example, they could be located between two source regions, or alternatively between two body regions. Those skilled in the art will understand that the gate insulator, gate electrode, and other elements are omitted for clarity of the drawings and to aid in illustrating the alternative locations of regions 53-54.

[0037] Based on all the above descriptions, those skilled in the art will understand that a semiconductor device having a transistor may include:

[0038] Semiconductor substrate, such as substrate 25;

[0039] An insulator located on a semiconductor substrate, such as insulator 26;

[0040] A source region covered by an insulator and having a first conductivity type, such as P-type, for example, region 45;

[0041] A drift region covered by an insulator and having a first type of conductivity, such as region 37;

[0042] A drain region, such as region 40, located within the drift region, covered by an insulator and having a first conductivity type, is separated from the source region by at least a portion of the drift region;

[0043] A first doped region, such as layer 28, located on an insulator, having a first doping concentration and a first conductivity type, is formed to extend continuously through the insulator below the source region, drain region, and drift region.

[0044] A confinement layer, such as layer 30, is located on the first doped region, has a second doping concentration and a second conductivity type, such as N-type, and the second doping concentration is greater than the first doping concentration. The confinement layer is formed to extend continuously through the first doped region below the source region, drain region and drift region.

[0045] An epitaxial layer, such as layer 32, is located on the confinement layer and has a first conductivity type. The epitaxial layer has a third doping concentration, which is less than the second doping concentration and greater than the first doping concentration. A portion of the epitaxial layer forms a PN junction with the confinement layer.

[0046] A host region located in the epitaxial layer and having a second conductivity type, such as one of regions 35 / 42 / 43, wherein a source region is located in the host region, the host region is electrically coupled to a confinement layer, and the confinement layer receives a potential applied to the host region; and

[0047] A bias contact, such as one of regions 53 / 54, is formed in the epitaxial layer and includes a second doped region having a first conductivity type. The bias contact is electrically coupled to the first doped region, wherein a potential applied to the bias contact is applied to a portion of the PN junction.

[0048] Implementations may include: the depletion region along the confinement layer is substantially depleted within the transistor-disabled region.

[0049] The transistor may have embodiments in which the depletion region along the confinement layer is substantially depleted within the region where the transistor is disabled.

[0050] An embodiment of the transistor may include a first doped region having a substantially constant potential for a first region where the transistor is enabled and a second region where the transistor is disabled.

[0051] The embodiments may also include a third doped region, such as region 35, which is located in the epitaxial layer, has a second conductivity type, and extends to adjoin the confinement layer and the body region.

[0052] In one embodiment, the third doped region may be located below a portion of the host region, source region, and drift region, but not below the drain region.

[0053] An embodiment may include a limiting layer located below the bias contact.

[0054] In one embodiment, a portion of the epitaxial layer may extend between and adjacent to the bias contact and the confinement layer.

[0055] Implementations may include: the limiting layer is not located below the bias contact.

[0056] Another embodiment may include: the first doped region being located below the bias contact.

[0057] One possible embodiment of the transistor is in which the confinement layer is indeed located below the bias contact.

[0058] Those skilled in the art will understand that an embodiment of a semiconductor device having a transistor may include:

[0059] A first doped region, such as region 32, having a first conductivity type, such as P-type, and a first doping concentration;

[0060] A drift region located within a first doped region and having a first conductivity type, such as region 37, and a drain region formed in the drift region and having a first conductivity type, such as region 40 or below region 40;

[0061] A main region, such as region 42, is separated from the drift region by a certain distance and has a second conductivity type, such as N-type.

[0062] A source region located within the main region and having a first conductivity type, such as region 45;

[0063] The channel region located between the source region and the drift region;

[0064] A confinement layer, such as layer 30, having a second conductivity type and a second doping concentration greater than a first doping concentration, extends continuously beneath the host region, source region, channel region, drift region, and drain region, wherein the confinement layer is electrically connected to the host region, such as region 35; and

[0065] A barrier layer, such as layer 28, having a first conductivity type and a third doping concentration, wherein the third doping concentration is less than the first doping concentration, is located below and adjacent to the confinement layer, wherein the potential of the barrier layer is substantially constant.

[0066] The transistor may also include a second doped region having a second conductivity type, such as region 35, the second doped region being formed on the confinement layer and extending to contact the host region.

[0067] In one embodiment, the second doped region may be located below at least a portion of the host region and the drift region, but not below the drain region.

[0068] In one embodiment, when the transistor is enabled, at least a portion of the confinement layer along its length can substantially deplete the carriers.

[0069] The embodiments may include bias contacts, such as one of regions 53 / 54, which are formed in the first doped region as a second doped region having a first conductivity type.

[0070] One possible embodiment of a transistor is one in which the potential of the barrier layer remains substantially constant when the transistor is enabled and disabled.

[0071] Those skilled in the art will understand that embodiments of a method for forming a semiconductor device having transistors may include:

[0072] Provide semiconductor substrates;

[0073] A first doped region, such as layer 28, is formed covering the semiconductor substrate and having a first conductivity type, such as P-type.

[0074] A second doped region having a second conductivity type, such as N-type, is formed on the first doped region, for example, region 30, and the second doped region has a first doping concentration;

[0075] A third doped region having a first conductivity type is formed on the second doped region, for example, layer 32. The third doped region has a second doping concentration, which is less than the first doping concentration.

[0076] A host region is formed, a source region is formed within the host region, a drift region is formed within a first doped region, and a drain region is formed within the drift region, wherein the first doped region and the second doped region extend to be continuously located below the source region, the drift region and the drain region, and the second doped region is electrically coupled to the host region.

[0077] One possible embodiment of the method may include forming a bias contact having a first conductivity type within a third doped region, the bias contact serving as a fourth doped region, such as region 53 or 54, wherein the potential of the first doped region is substantially constant for the transistor’s enabled and disabled operating states.

[0078] One embodiment may include forming a fourth doped region to receive a potential independently of the voltages applied to the source region, body region, and drain region.

[0079] In view of all that has been described above, a novel device and method are disclosed. Among other features, this includes forming a transistor with a barrier layer and a confinement layer. The barrier layer is maintained at a substantially constant voltage, which reduces power losses during transistor switching. The confinement layer is coupled to the body region and forms a depletion region, which helps to improve the transistor's breakdown voltage.

[0080] While the subject matter of this description has been described using specific preferred and exemplary embodiments, the foregoing drawings and descriptions merely depict typical and non-limiting examples of embodiments of the subject matter and should not be construed as limiting the scope of the subject matter. Obviously, many alternatives and variations will be apparent to those skilled in the art. For example, the subject matter has been described with respect to a specific P-channel or P-type MOS transistor, but the method is directly applicable to N-channel or N-type MOS transistors. Those skilled in the art will understand that this structure is also applicable to diodes and transistors.

[0081] As reflected in the claims below, the inventive step may not lie in all the features of the single embodiments disclosed above. Therefore, the claims described below are expressly incorporated herein by reference to the detailed description of the accompanying drawings, each claim being an independent embodiment of the invention. Furthermore, as those skilled in the art will understand, while some embodiments described herein include other features not included in other embodiments, combinations of features from different embodiments are also intended to be within the scope of the invention and to form different embodiments.

Claims

1. A semiconductor device having a transistor, characterized in that, The semiconductor device includes: Semiconductor substrate; An insulator located on the semiconductor substrate; A source region that covers the insulator and has a first conductivity type; A drift region, the drift region covering the insulator and having the first conductivity type; A drain region located within the drift region, covering the insulator and having the first conductivity type, wherein the drain region is spaced apart from the source region by at least a portion of the drift region; A first doped region is located on the insulator, has a first doping concentration, and has the first conductivity type. The first doped region is formed to extend continuously through the insulator below the source region, the drain region, and the drift region. A confinement layer is located on the first doped region, has a second doping concentration and a second conductivity type, the second doping concentration being greater than the first doping concentration, and the confinement layer is formed to extend continuously through the first doped region below the source region, the drain region and the drift region; An epitaxial layer is located on the confinement layer and has the first conductivity type. The epitaxial layer has a third doping concentration, which is less than the second doping concentration and greater than the first doping concentration. A portion of the epitaxial layer forms a PN junction with the confinement layer. A body region, located within the epitaxial layer and having the second conductivity type, wherein a source region is located within the body region, the body region is electrically coupled to the confinement layer, and the confinement layer receives a potential applied to the body region; and A bias contact is formed in the epitaxial layer and includes a second doped region having the first conductivity type. The bias contact is electrically coupled to the first doped region, wherein a potential applied to the bias contact is applied to a portion of the PN junction.

2. The semiconductor device as claimed in claim 1, wherein, The depletion region along the limiting layer is substantially depleted within the range where the transistor is disabled.

3. The semiconductor device as claimed in claim 1, wherein, The limiting layer is not located below the bias contact.

4. A semiconductor device having a transistor, characterized in that, The semiconductor device includes: A first doped region, the first doped region having a first conductivity type and a first doping concentration; A drift region, the drift region being located within the first doped region and having the first conductivity type, the drift region having a drain region formed in the drift region and having the first conductivity type; The main body region is separated from the drift region by a certain distance and has a second conductivity type; A source region, wherein the source region is located within the body region and has the first conductivity type; The channel region is located between the source region and the drift region; A confinement layer having a second conductivity type and a second doping concentration, the second doping concentration being greater than the first doping concentration, the confinement layer extending continuously beneath the body region, the source region, the channel region, the drift region, and the drain region, wherein the confinement layer is electrically connected to the body region; and A barrier layer having a first conductivity type and a third doping concentration less than the first doping concentration, the barrier layer being located below and adjacent to the confinement layer, wherein the potential of the barrier layer is substantially constant.

5. The semiconductor device as claimed in claim 4, wherein, The semiconductor device further includes a second doped region having the second conductivity type, the second doped region being formed on the confinement layer and extending to contact the host region.

6. The semiconductor device of claim 4, wherein, When the transistor is enabled, at least a portion of the confinement layer along its length substantially depletes the carriers.

7. The semiconductor device of claim 4, wherein, The potential of the barrier layer remains substantially constant when the transistor is enabled and disabled.

8. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; A first doped region having a first conductivity type, the first doped region covering the semiconductor substrate and having a first doping concentration; A second doped region having a second conductivity type, the second doped region being located on the first doped region and having a second doping concentration; A third doped region having the first conductivity type, the third doped region being located on the second doped region and having a third doping concentration, the third doping concentration being less than the second doping concentration; and The main region in the third doped region; The source region within the main body region; The drift region within the third doping region has a fourth doping concentration, which is greater than the first doping concentration; The drain region within the drift region; The first doped region and the second doped region extend continuously below the source region, the drift region and the drain region, and the second doped region is electrically coupled to the body region.

9. The semiconductor device of claim 8, wherein, The semiconductor device further includes a bias contact formed within the third doped region as a fourth doped region having the first conductivity type, wherein the potential of the first doped region is substantially constant for both the enabled and disabled operating states of the semiconductor device.

10. The semiconductor device of claim 9, wherein, The fourth doped region is coupled to receive the potential independently of the voltage applied to the source region, the body region, and the drain region.

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